Abstract: A switching converter controller includes: a stopband controller having a stopband controller input and a stopband controller output, the stopband controller is configured to provide stopband information at the stopband controller output responsive to a reference signal; a pulse-frequency modulation (PFM) controller having a first PFM controller input, a second PFM controller input and a PFM controller output, the first PFM controller input configured to receive a feedback error signal, the second PFM controller input coupled to the stopband controller output, and the PFM controller configured to selectively adjust a clock signal at the PFM controller output based on the feedback error signal and the stopband information; and a driver circuit having a driver circuit input coupled to the PFM controller output and configured to receive the clock signal, and having a driver circuit output adapted to be coupled to a power stage switch.

Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

Abstract: A power supply system includes first and second power supply lines to respectively connect positive and negative electrode terminals of a load with a main power supply. First and second voltage detection lines are respectively connected to the first and second power supply lines via first and second resistances. First and second inspection power supplies respectively supply power and provide potential differences to the first and second voltage detection lines from the first and second power supply lines. Occurrence of a short circuit in one of the first and second voltage detection lines is recognized when corresponding one of the first and second inspection power supplies supplies power and a difference between a preset voltage and a voltage caused between the first and second voltage detection lines is a threshold value or more.

Abstract: A circuit for controlling a power converter includes an SR switching device, a light load detection circuit generating a load detection signal in response to a conduction signal and an operation mode signal, and an SR driver generating a control signal having a value according to the load detection signal and provide the control signal to the SR switching device. A method of controlling a power converter includes generating a load detection signal in response to a conduction signal and an operation mode signal and generating a control signal having a value according to the load detection signal. The control signal has a first value when the load detection signal is asserted and has a second value when the load detection signal is de-asserted.

Abstract: An apparatus is provided which includes: a first set of devices which is digitally controlled by a first feedback loop that includes a first comparator; and a second set of devices which is controlled by an analog circuitry which is part of a second feedback loop that includes an amplifier, wherein the first set of devices is coupled in parallel to the second set of devices.

Abstract: A power supply protection circuit and a method is described herein. The power supply protection circuit comprises a current control unit, a voltage feedback unit, and a current pull-up unit. The voltage feedback unit is connected to the current control unit, the voltage feedback unit obtains a feedback voltage of an output voltage and feeds back the feedback voltage to the current control unit, and the current control unit uses the feedback voltage to control the current control unit to regulate an output current. The current pull-up unit is connected to a feedback terminal of the voltage feedback unit, and the current pull-up unit provides the voltage feedback unit with a pull-up current to determine whether the feedback terminal of the voltage feedback unit is short-circuited.

Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.

Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: A light-emitting diode chain comprising a plurality of light-emitting diodes (LED1 . . . LED4) connected in series and fed by a current source, in which each light-emitting diode is assigned a control circuit (5), which has a series connection, connected in parallel with the light-emitting diode, between a reference voltage sink (D1) of the voltage (Uref) and a controlled switch (Q) and is designed to compare the control voltage (Ust) at a control line (4) common to all control circuits, measured against is base point of the LED series circuit, with the voltage at the connection between the switch and the subsequent LED in the chain or the base point, and to close or to open the switch if the control voltage (Ust) falls below a predefined value or rises above a predefined value respectively.

Abstract: In one embodiment, a load detection circuit may include a first circuit configured to control a first transistor to form a load current to a load in a first operating mode of the load detection circuit, a second circuit configured to be coupled to form at least a portion of the load current in a second operating mode of the load detection circuit, and a detection circuit configured to detect the control electrode of the first transistor having a value that is less than a threshold value of the first transistor.

Abstract: A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal.

Abstract: A circuit includes a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage. The clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold. A first switch supplies the reference voltage to the comparator. The first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage. A second switch is coupled to the input voltage and a second feedback path in the comparator. The second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.

Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.

Abstract: A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.

Abstract: Some embodiments relate to a level detector, comprising a current mirror including first and second current legs to carry first and second signals, respectively. The first current leg includes a first variable resistor and the second current leg includes a second variable resistor. During a calibration mode, a switching element provides a predetermined reference voltage across first and second control terminals of the first and second variable resistors, respectively. During a non-calibration mode, the switching element decouples the predetermined reference voltage from the first and second control terminals, and provides a signal across the first and second control terminals. Other embodiments are also disclosed.

Abstract: Disclosed is a low voltage detection circuit. The low voltage detection circuit includes, a voltage comparison circuit, an output stage, an electric current circuit, and a judgment circuit. When the voltage comparison circuit detects that the voltage of the detection target is a predetermined voltage value or less, an output state of the output stage is promptly changed. When the voltage comparison circuit detects that the voltage of the detection target is a predetermined voltage value or more, the output state of the output stage is changed after a delay time obtained by the electric current circuit.

Abstract: The present invention provides a comparator with novel output logic. The comparator makes a comparison between an input voltage and a reference voltage. A differential amplifying circuit includes a first input transistor with a control terminal applied with the reference voltage and a second input transistor with a control terminal applied with the input voltage. An output section receives an export signal of the differential amplifying circuit and outputs an output signal that corresponds to the export signal and denotes a result of the comparison. A feedback circuit receives the output signal of the output section, and if the output signal is changed from a first level to a second level, the output signal feeds back to the differential amplifying circuit or the output section while it is restored to the negated level.

Abstract: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals.

Abstract: A comparator comprises a differential amplifier type including input MOSFETs receiving differential input of a reference voltage and an input voltage, load MOSFETs for the input MOSFETs, and a constant current source to supply the sources of the input MOSFETs. The comparator comprises a Zener diode that is connected between the gate and source of the input MOSFETs and exhibits a breakdown voltage lower than the withstand voltage of the gate oxide film of the input MOSFET. Another comparator further comprises a feedback MOSFET that performs negative feedback of an output voltage of a main body comparator to the gates of the load MOSFETs to restrict the amplitude of the output voltage. Still another comparator further comprises a semiconductor rectifying element that exhibits a reverse-blocking characteristic higher than the power supply voltage and is interposed between the constant current source and the source of each of the input MOSFETs.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

Abstract: The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.

Abstract: A method of monitoring supply voltage includes providing a single reference voltage, providing a single ratioed supply voltage, comparing the reference voltage to the ratioed supply voltage to provide an output signal, wherein the output signal comprises a first logic value in first and second operating conditions, and a second logic value in a third operating condition, wherein the first, second, and third operating conditions are determined by two crossing points of the reference voltage and ratioed supply voltage characteristics. The first and second operating conditions can represent undervoltage and overvoltage conditions, and the third operating condition can represent a normal operating condition. The reference voltage can be provided by a bandgap reference circuit.

Abstract: A comparator circuit for generating a signal representing a comparison of an input signal and a reference signal. In an embodiment, the comparator circuit includes a first stage and a second stage to provide respective signal amplification, where switch circuitry of the second stage switchedly couples respective elements of the first and second stages. The comparator circuit further includes a third stage to generate an output signal based on an intermediate signal of the second stage. In another embodiment, feedback circuitry of the comparator circuit is to selectively control a voltage of the output stage based on the output signal.

Abstract: An oscillator circuit includes an oscillator output signal generating circuit configured to generate an oscillator output signal using an oscillator as a resonator, an amplitude detection circuit configured to detect the amplitude of the oscillator output signal and compare the detected amplitude with a threshold; and a boost circuit configured to boost the oscillator output signal according to the result of the comparison at the amplitude detection circuit. The amplitude detection circuit includes an absolute value circuit configured to obtain an absolute value signal of the oscillator output signal, a low-pass filter configured to convert the absolute value signal into a low-frequency signal, and a comparator configured to compare the low-frequency signal with the threshold.

Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.

Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.

Abstract: A power-up signal generation circuit of a semiconductor apparatus includes a driver configured to generate a power-up signal in response to a first voltage. The power-up signal generation circuit may also comprise a power control unit configured to provide the first voltage or a second voltage as a power supply voltage to the driver in response to the power-up signal.

Abstract: An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a VCC into N states SK, and acquires the border voltages VK and VK+1 corresponding to the SK through a resistor divider. The threshold selector acquires a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine and then sends the acquired VK as VH to a first comparator, and acquires a corresponding voltage VK+1 and sends the acquired VK+1 as VL to a second comparator. The state machine determines whether or not the VH and the VL are matched with the current state SK. If matched, the OSC of the state machine will be turned off, otherwise, the next state Sk+1 or Sk?1 of the SK will be outputted.

Abstract: The present invention provides a high-side signal sensing circuit. The high-side signal sensing circuit comprises a signal-to-current converter, a second transistor and a resistor. The signal-to-current converter has a first transistor generating a mirror current in response to an input signal. The second transistor cascaded with the first transistor is coupled to receive the mirror current. The resistor generates an output signal in response to the mirror current. Wherein, the level of the output signal is corrected to the level of the input signal.

Abstract: A resistor-capacitor (RC) calibration circuit includes: a current source, providing a current to a first node; a first switch, coupled between the first node and a second node; a second switch, coupled between the first node and a third node; a resistor, coupled between a reference terminal and the second node; a variable capacitor, coupled between the reference terminal and the third node; a third switch, coupled between the third node and the reference terminal; a comparator, comprising a first input coupled to the second node and a second input coupled to the third node; and a logic controller, coupled between an output of the comparator and the variable capacitor for outputting an adjusting signal according to an output signal of the comparator to adjust a capacitance of the variable capacitor.

Abstract: A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

Abstract: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: Some embodiments of the present disclosure relate to a sensor interface module. The sensor interface module includes a comparator having a first comparator input, a second comparator input, and a comparator output. A current- or voltage-control element has a control terminal coupled to the comparator output and also has an output configured to deliver a modulated current or modulated voltage signal to an output of the sensor interface module. A first feedback path couples the output of the current- or voltage-control element to the first comparator input. A summation element has a first summation input, a second summation input, and a summation output, wherein the summation output is coupled to the second comparator input. A supply voltage module provides a supply voltage signal to the first summation input. A second feedback path couples the comparator output to the second summation input.

Abstract: A bulk-driven current-sense amplifier and an amplifier operating method are disclosed. The bulk-driven current-sense amplifier includes a differential amplifier, a first driver, and a second driver. The first driver is coupled to the differential amplifier, and a first node is formed at a connectivity segment of the first driver. The second drive is coupled to the differential amplifier, and a second node is formed at a connectivity segment of the second driver. When a first switch of the first driver and a second switch of the second driver are turned on, the differential amplifier charges the first node and the second node. When the charging is completed, the first node and the second node respectively have a different stabilized potential according to currents separately flowing through a first memory unit of the first driver and a second memory unit of the second drive, and the differential amplifier generates a voltage.

Abstract: An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a VCC into N states SK, and acquires the border voltages VK and VK+1 corresponding to the SK through a resistor divider. The threshold selector acquires a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine and then sends the acquired VK as VH to a first comparator, and acquires a corresponding voltage VK+1 and sends the acquired VK+1 as VL to a second comparator. The state machine determines whether or not the VH and the VL are matched with the current state SK. If matched, the OSC of the state machine will be turned off, otherwise, the next state Sk+1 or Sk?1 of the SK will be outputted.

Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Abstract: According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.

Abstract: A first A/D converter converts an analog observed value, which corresponds to a power supply signal supplied to a power supply terminal of a DUT, into a digital observed value. By means of digital calculation processing, a digital signal processing circuit generates a control value that is adjusted such that the digital observed value matches a predetermined reference value. A first D/A converter supplies, via a power supply line to the power supply terminal of the DUT, an analog power supply signal obtained by performing digital/analog conversion of the control value. A load estimating unit applies a test signal containing a predetermined frequency component via the power supply line to a node via which the power supply terminal is to be connected, and generates a control parameter for the digital signal processing circuit according to the test signal and the observed signal.

Abstract: A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Abstract: A voltage source generates a power supply voltage VOUT stabilized such that it matches the voltage level that corresponds to a reference voltage VREF, and supplies the power supply voltage to a DUT. A current detection circuit generates a detection voltage Vm that corresponds to an output current IOUT that flows through the DUT. In the initial state, the reference voltage VREF generated by a reference voltage generating circuit is set to an initial voltage level that corresponds to an input voltage VIN. After the output current IOUT flows, the reference voltage transits to a first voltage level VL1 obtained by shifting the initial voltage level by a first voltage step that corresponds to the detection voltage Vm. Subsequently, the reference voltage VREF transits to a second voltage level VL2 obtained by shifting the initial voltage level by a second voltage step that corresponds to the detection voltage Vm.

Abstract: The present invention discloses a power stage control circuit including: a driver circuit for controlling a power stage according to an error amplified signal; an error amplifier circuit for comparing a feedback voltage at a feedback terminal with a reference signal to generate the error amplified signal; a current generator circuit coupled to the feedback terminal for generating a fault detection current flowing to the feedback terminal; and a feedback terminal short detection circuit for generating a fault signal to stop the operation of the power stage when the feedback voltage is smaller than a short-circuit threshold voltage or when the fault detection current is larger than a short-circuit threshold current.

Abstract: Embodiments include a comparing device having hysteresis characteristics and a voltage regulator using the same. The voltage regulator includes a comparator which compares a comparison voltage with a reference voltage and outputs a result of the comparison, a switching controller which generates a plurality of switching signals in response to the comparison result, resistors connected in the form of a string to divide the comparison voltage into a plurality of voltages, and a switching box which selects one of the plural voltages as the comparison voltage in response to the switching signals.

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Abstract: In order to transfer data at high speed over a long distance, a current mode logic output circuit (CML) having a large number of taps, high accuracy, and a wide switchable range of the amount of pre-emphasis is needed. However, when the amount of emphasis is set by adding unit source-coupled pair circuits, a problem will arise that the output capacitance of the current mode logic output circuit would increase, thus hampering high-speed transmission. An output circuit of the invention is constructed from unit source-coupled pair circuits 501, which are obtained by dividing a current mode logic output circuit (CML) into m groups, terminal resistors 502, and a data selector 504. The amount of emphasis of each tap is determined by the ratio of the number of unit source-coupled pair circuits, which have been obtained by dividing the CML into m groups, allocated to each tap. Thus, the amount of emphasis can be set to be any arbitrary amount without a change in the output amplitude of 1.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.