Abstract: A method and circuit for automatically centering the control loop bias current by sensing and “memorizing” the total steady state bias current used by the function block (VGA or VCO) through the use of both digital and analog memory elements. The present invention uses an auto-centering, high-impedance current driver to supply the bias current. This current driver cancels out offset currents by exploiting the high output impedance nature of a CMOS current driver using cascoded or resistor source de-generated FET devices.

Abstract: A hysteresis comparator circuit which has: a first differential input circuit that operates according to the difference between input voltage and reference voltage; an adder circuit that is composed of first and second addition input ends and differential output voltage of the first differential input circuit is input to the first and second addition input ends as first addition input; a quantizer that quantizes output voltage of the adder circuit and outputs the quantized value as output signal; an attenuator that attenuates output voltage of the quantizer; and a second differential input circuit that applies differential output obtained by differential-amplifying output voltage of the attenuator to the first and second addition ends as second addition input as well as forming a positive-feedback system.

Abstract: A multiplier circuit multiplies a reference voltage to increase the level of the reference voltage. A feedback circuit of the multiplier circuit stabilize the multiplier circuit such that a feedback voltage of said feedback circuit tends to equalize the reference voltage. The feedback circuit is free from capacitance which would unstabilize the feedback circuit. A voltage divider outside of the feedback circuit reduces the multiplied voltage of the multiplier circuit.

Abstract: A current sensing circuit with high input impedance comprises a first transconductance amplifier connected across the terminals of a resistor, through which a current to be measured flows. A voltage amplifier is cascade-connected to the first transconductance amplifier. A second transconductance amplifier is feedback connected between an output of the voltage amplifier and a virtual ground node of the voltage amplifier. A ratio between the output voltage of the voltage amplifier and the voltage across the resistor are equal, in absolute value, to a ratio of the transconductances of the first and second transconductance amplifiers.

Abstract: A dual-threshold voltage comparator circuit utilizes a single input pin of an integrated circuit and an external resistor network. Appropriate selection of the resistors comprising the resistor network permits independent setting of the dual thresholds of the comparator.

Abstract: A high-speed, differential pair input buffer is constructed from a conventional differential pair having a data input terminal, a reference voltage input terminal, and an output terminal. A voltage source Vsupply and its ground connection are coupled to the differential pair through a first pair of transistors. The first pair of transistors have their enable inputs coupled to the data input terminal so that they are both biased "on" during a transition in a logic signal delivered to the data input terminal. The output terminal of the differential pair is connected through a delay circuit to the enable input terminals of a second pair of transistors, which also interconnect the differential pair to the voltage source V.sub.supply and system ground. Thus, the second pair of transistors provide a feedback path to enable the differential pair to conduct current longer if a load connected to the output of the differential pair slows the transition of the output of the differential pair.

Abstract: The present invention discloses an integrated constant bias voltage generator using only active devise to simulate a high impedance node, as seen from a capacitively coupled input signal. A reference current source an MOS device are coupled in series between Vcc and ground with the drain electrode of the MOS device being the constant bias voltage output. An input signal capacitively coupled to said drain electrode introduces an error current monitored by a current monitoring means. A feedback means responsive to the current monitoring means modulates the control input of the MOS device to select a IDS vs. VDS characteristic curve which will maintain the VDS voltage constant for any given IDS current, including the error current. The feedback means also compensates for voltage fluctuations in Vcc.

Abstract: The current sensing circuit with automatic offset compensation is provided with a current sensing resistor, a difference amplifier which inputs this current sensing resistor voltage at its voltage measuring input terminal and inputs a reference voltage at its reference voltage terminal, and a measuring circuit which determines the current flowing in the current sensing resistor from the difference amplifier output voltage. The current sensing circuit adds a small bias voltage to the current sensing resistor voltage and inputs it to the voltage measuring input terminal to increase difference amplifier output voltage. The measuring circuit measures difference amplifier output voltage and compensates the reference voltage input to the difference amplifier reference voltage terminal to compensate difference amplifier output to 0V when current sensing resistor current is zero.

Abstract: In view of the fact as found in the prior art that a measured device as hardly installed on a chip and a temperature variation in the measured device could not be detected accurately, the present invention provides a system in which a MOS transistor is arranged, there is provided a potential control circuit for sensing a potential in the case of depletion under a gate of a certain specified MOS transistor and controlling a gate voltage of the MOS transistor while comparing the detected output with the reference voltage Vref, and a temperature is detected in reference to a variation in current of the MOS transistor while controlling a gate voltage of the MOS transistor by this potential control circuit.

Abstract: A circuit arrangement is disclosed which detects a signal pauses in an audio signal, The audio signal is amplified, rectified, and then sent to a control unit. The control unit periodically sets the output of the rectifier to a predetermined level below a threshold level. The control unit then waits a predetermined period of time and determines whether the signal at the output of the rectifier has exceeded the threshold. If is does not, a signal pause has occurred.

Abstract: A voltage circuit for a device having an active period and an inactive period comprises a reference voltage generator generating a reference voltage and a voltage stabilizer receiving the reference voltage. The voltage stabilizer includes first circuit componentry for raising a potential of an output terminal during the active period of the device and second circuit componentry for lowering a potential of the output terminal during at least the inactive period of the device.

Abstract: A precision voltage level shift circuit includes an emitter follower input circuit including a lateral PNP transistor having a base receiving an input voltage, and an emitter coupled to both an output terminal and a first current source. JFET is coupled between a collector of the input transistor and a first supply voltage conductor. A second PNP transistor has a base coupled to the collector of the first transistor and an emitter coupled to a second current source. A differential amplifier has a first input coupled to the output terminal, a second input coupled to the emitter of the second transistor, and an output coupled to the load element. The differential amplifier operates to maintain the voltage drop across the JFET at a level such that the emitter of the second PNP transistor is equal to the voltage of the emitter of the lateral PNP transistor to thereby maintain the collector-emitter voltage thereof at a constant value.

Abstract: The present invention relates to a circuit for restoring bits transmitted by an asynchronous signal, including a comparator of the signal level with a reference level; a sampling circuit supplying several samples of the comparator output for each time interval corresponding to a bit; a circuit for determining a succession of windows, each of which corresponds to a bit; an acquisition circuit receiving the samples and supplying, for each window, the number of samples having a first logic value, the number of sample transitions, and the value of a border sample of an adjacent window; and an estimation circuit for correcting the reference level and the alignment of the windows on the bits according to the outputs of the acquisition circuit.

Abstract: A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.

Abstract: An accurate V/I conversion circuit converts an input voltage to an electric current which includes an external resistance in series with an input voltage V1. The external resistance is directly coupled to an input terminal of the V/I conversion circuit. V/I conversion circuit includes an input terminal coupled to the external resistance which is in series with the input voltage V1. V/I conversion circuit also includes (1) a resistance type voltage dividing circuit which generates a standard voltage by dividing a supply voltage, (2) a differential amplifier circuit comprising two transistors which compares a voltage of the input terminal with the standard voltage, (3) a third transistor which receives the collector voltage of one of the transistors in the differential amplifier where the third transistor is also connected between the input terminal and ground with a resistor in series, and (4) a fourth transistor which receives a collector voltage of one of the transistors of the differential amplifier.

Abstract: A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.

Abstract: A motor current detection circuit is formed of a current detector for detecting an overloaded state of a motor by comparing a motor current value, which represents current flowing through the motor, with a predetermined reference value, and a hysteresis generating circuit for generating, in the current detector, a hysteresis characteristic corresponding to an integrated value with respect to time of an increment amount by which the motor current value exceeds the reference value. Chattering in output of the current detector is reduced so that an overloaded state of the motor can be detected quickly.

Abstract: A semiconductor device includes a differential amplifier and a first and a second pull-up transistor for generating a reference voltage. The second pull-up transistor has a gate connected to an output terminal of the differential amplifier. The differential amplifier is such that, when an output voltage thereof previously outputted is at a high level, both the first and second pull-up transistors become conductive so that the reference voltage becomes equilibrium at a high level voltage, and when an output voltage previously outputted is at a low level, the first pull-up transistor becomes conductive and the second pull-up transistor becomes non conductive so that the reference voltage becomes equilibrium at a low level voltage. With this arrangement, a high speed operation of the differential amplifier is realized.

Abstract: A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.

Abstract: A charge mode pulse-width modulation control method and apparatus includes setting up a detector at a primary side of a transformer to detect a current and feeding back the detected current to a current apparatus to provide a current output; an integrator providing charge output with a voltage mode, where the charges are supplied by the integrator which takes the output current of current source to implement mathematical integration, and produce an output voltage and providing the output voltage to a main controller as a reference for deciding whether or not to switch a switch. The control system can prevent the transformer from reaching magnetic saturation and the feedback control current signal from generating noises.

Abstract: A decision circuit compares an input voltage with a reference voltage and judges whether the input voltage is at least equal to the reference voltage. A controller in the decision circuit detects whether the input voltage or reference voltage is at least equal to the setting voltage. When both the input voltage and the reference voltage are lower than a setting voltage, which represents an operating voltage of the decision circuit, a first bias-supply circuit adds a predetermined bias voltage to the input voltage and supplies a level-shifted input voltage to the decision circuit. Similarly, a second bias-supply circuit adds the predetermined bias voltage to the reference voltage and supplies a level-shifted reference voltage to the decision circuit. Therefore, the decision circuit compares the level-shifted input voltage with the level-shifted reference voltage.

Abstract: A bi-mode circuit for driving an output load selectively couples the output load to a supply voltage source or to a low discharge voltage source such as ground using switches which are controlled by an input buffer in response to an input signal. A high input signal closes a first switch to provide a biasing current to first and second current amplifiers to turn on a first output transistor which couples the output load to the low reference voltage to discharge the output load. Conversely, a low input signal closes a second switch to provide the biasing current to a third current amplifier to turn on a second output transistor which couples the output load to the supply voltage source. When the input signal becomes high, rapid pulldown of a capacitive output load is achieved using a high internal pre-drive current provided by the first and second current amplifiers, in a first mode of operation.

Abstract: A comparator circuit (31) for sensing a voltage difference between a battery voltage and a power supply voltage is coupled to a switch (39). The comparator circuit is capable of accurately sensing a voltage near the power supply voltage. The comparator circuit (31) comprises a first amplification stage (32-36), a second amplification stage (37), and a Schmitt trigger (38). The first amplification stage (32-36) includes a first source follower (32) and a second source follower (33) for generating a differential voltage corresponding to a difference voltage between the battery voltage and the power supply voltage. The first amplification stage (32-36) reduces problems in amplifying voltage near the power supply voltage by level shifting the voltage through the use of source followers and insuring transistors operate in a saturation region of operation. The second amplification stage (37) further amplifies the difference voltage between the battery voltage and the power supply voltage.

Abstract: A full wave rectifier includes an amplifier having a minus input, a plus input and an amplifier output; an input resistor connected between a circuit input and the minus input; and a current bridge having an output terminal connected to the circuit output, a first terminal connected to the minus input and a second terminal connected to the amplifier output. The current bridge includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first current source and a second current source, a source end of each current source of the first and second current sources being connected to the first terminal, a drain end of the first current source being connected to the second terminal and a drain end of the second current source being connected to the output terminal.

Abstract: A data slice circuit is provided for slicing the caption data or the likes included in a television signal at an optimum voltage. A product between a clock-run signal sliced by a comparator at a tentative reference voltage and a clock signal which is 16 times the clock-run signal is stored in a shift register as 16 bit information, and out of them, only the 8 bits around its center are taken in a duty-factor check block, thereby judging the suitability of the slice level. Based on the result obtained, the value of the counter is increased or decreased, and it is taken as a renewed reference voltage through a pulse width conversion circuit and an integration circuit. Also with data sliced by a renewed reference voltage, the check is executed similarly, and a slicing action at an optimum level is achieved.

Abstract: A voltage comparator for comparing an input voltage with a comparison voltage having a hysteresis characteristic. The comparison voltage is derived by combining a voltage drop developed across a fixed resistor by supplying a constant current therethrough from a constant current source and a reference voltage from a constant voltage source.

Abstract: The present invention provides a system for controlling current through inductive elements by automatically switching between a pulse width modulation mode and a linear mode, depending upon the current demands of the inductive elements. A time-base circuit provides periodic pulses that allow current to flow through an inductive device. The current through the inductive device increases over time. If the current through the inductive device exceeds a specified value, the current is shut off until the next pulse from the time-base circuit. After the power supply current has been shut off, current through the inductive device continues to flow through flyback diodes, gradually decreasing over time. Another pulse is provided by the time-base circuit before the current is allowed to reach zero. By controlling the duration and rate of increase and decrease of current through the inductive device, a method of current control for inductive elements has been provided.