Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.

Abstract: Some embodiments of the invention relate a circuit having a first and a second electrically connected voltage domains, respectively biased at different supply voltages (e.g., the first voltage domain biased at a low bias voltage and the second voltage domain biased at a second, different supply voltage). The apparatus further comprises a first DC current source coupled to one of the voltage domains (e.g., the first voltage domain having a low DC voltage potential) and a second DC current source coupled to the other voltage domain (e.g., the second voltage domain having a high DC voltage potential). The first and second DC current sources are configured to provide a DC cancellation current having a value that cancels a DC current generated by the potential difference between the first and second voltage domains.

Abstract: A Wide-band Equalization System (“WBES”) based on near- and far-field measurement data. The WBES includes a subwoofer equalizer having an FIR filter together with decimator and interpolator filters for processing low frequency signals. The WBES may also include satellite channels for processing mid- and high-frequency signals, where each satellite channel includes cascaded IIR filters that process mid-frequency and high-frequency signals, respectively. The WBES may also include a DSP that performs the functions required by the IIR and FIR filters.

Abstract: An amplifier with wide gain range includes a signal converting unit, a channel unit, and multiple amplifiers. The signal converting unit receives a gain modulation signal and accordingly outputs multiple modulation signals and multiple selection signals. Based on a level of the gain modulation signal, one of the selection signals is set at a first logic state and the other selection signals are at a second logic state. The channel unit has multiple channels, respectively controlled by the selection signals, so as to conduct the channel with at the first logic state. The amplifiers are connected in series. Output terminals of the amplifiers are also respectively output to the channels of the channel unit. The amplifiers are also controlled by the modulation signals of the signal converting unit.

Abstract: A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies.

Abstract: An amplifier and bypass switch circuit includes a circuit input, a circuit output, an amplifier and a switching circuit. The amplifier has an amplifier control input, and a first amplifier output. The amplifier control input is connected to the circuit input. The amplifier output is connected to the circuit output. The switching circuit includes a control input, a switch input, a switch output and a phase matching network. The switch output is connected to the circuit output. The switch input is connected to the circuit input. The phase matching network preserves phase information when the amplifier and bypass switch circuit switches between an amplifier mode and a bypass mode.

Abstract: In a method and an arrangement for adapting, from a DC point of view, the signal input of a first circuit, lying at a first DC voltage, to the signal output of at least one second circuit, lying at a second DC voltage, the signal input terminal is connected to the respective signal output terminal of the respective second circuit via a respective first resistance, whereby first DC currents will be allowed to flow through the respective first resistance. The signal input is adapted to be virtually short-circuited to a source for the first DC voltage, which is of a predetermined value, separate from zero. The first circuit is adapted to internally generate a DC cancellation current and bring it to flow in the signal input. The signal input is to be connected to ground via a selectable, second resistance, whereby a second DC current will flow through the second resistance.

Abstract: Current mirror circuits and methods, and an amplifier using same, are provided in which the output of the current mirror is reduced to zero when the input current falls below a predetermined threshold. An offset current is subtracted from the input (or reference) current at input currents below the threshold. Otherwise, the offset current source is turned off. Thus, the output current can be reduced to zero, even if there is a small input current, without distorting the input-output relationship over the majority of the range of operation of the current mirror. An amplifier with two current-feedback complementary input stages (or fader circuit) is also provided which includes a gain control circuit that uses the current mirror circuits of the present invention to ensure that each input can be fully attenuated.