Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: The amplifier includes an input circuit configured to convert an input signal into a current; an output circuit comprising at least one switching element for reducing a voltage change of an output end of the input circuit and configured to provide an output signal; and a biasing circuit connected to the at least one switching element to form a feedback loop for reducing the voltage change of the output end of the input circuit.

Abstract: A constant current generation circuit for optocoupler isolation amplifier and a current precision adjustment method are provided. The constant current generation circuit includes a start circuit, a current generation circuit and a precision adjustment and output circuit integrated into a same substrate. The start circuit can generate and output a first start current and a second start current. The current generation circuit includes a negative temperature change rate current generation circuit connected to a first start current output and a positive temperature change rate current generation circuit connected to a second start current output. The precision adjustment and output circuit outputs constant current meeting application requirements of optocoupler isolation amplifier by adjusting proportional precision of two currents output from a current generation circuit.

Abstract: Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

Abstract: A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value.

Abstract: A sensor interface circuit (5) for an amperometric electrochemical sensor (3). The circuit includes: a current-to-voltage converter (9, Rf) connected to a first terminal (WRK) of the sensor (3) for converting an electric current through the sensor (3) to a voltage at an output terminal (10) of the current-to-voltage converter (9, Rf); a first amplifier (7) connected between a second terminal (REF) and a third terminal (CNTR) of the sensor (3) for maintaining a substantially fixed voltage difference between the first and second terminals (WRK, REF) of the sensor (3); a power supply (11) for powering the voltage converter (9, Rf) and for powering a first portion (31) of the first amplifier (7); and a negative voltage converter (17) configured to power a second portion of the first amplifier (7) through its low-side supply terminal (41), while a high-side supply terminal (39) of the second portion of the first amplifier (7) is configured to be connected to the power supply (11).

Abstract: The present invention discloses a circuit for improving linearity and channel compensation of PAM4 receiver analog front end, comprising a first stage and a second stage, the first stage comprising first to twentieth transistors, a first resistor, a pair of second resistors, a pair of first capacitors, and a pair of second capacitors. In the first stage circuit, the ninth and tenth transistors are directly coupled to the ground, eliminating the electrical connection to the bias current source. The Input terminals of the ninth and tenth transistors are coupled to the output signals of the preceding nineteenth and twentieth transistors, so that the ninth and tenth transistors serve as both input pairs and current source transistors. The overall current is limited by the thirteenth and fourteenth transistors, which results in a lower power supply voltage for the first stage consisting of the ninth through fourteenth transistors.

Abstract: A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.

Abstract: A trans-impedance amplifier (TIA) may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, a pair of capacitors electrically connected in series, a differential output node, a third PMOS transistor, and a fourth pair of NMOS transistors cross-coupled between the pair of output circuits of the output driving stage. The structure can lead to a reduced noise level and a reduced peak transient current level of the TIA.

Abstract: A network TAP includes four serial transceivers on a printed circuit board. Each serial transceiver has a medium-dependent interface and a serial differential interface that includes a differential input and a differential output. A passive tap circuit arrangement is configured to be operative at up to 10 Gbps or a higher data rate and configures the differential output signal from the differential output of the first serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the second and third serial transceivers. It also configures the differential output signal from the differential output of the second serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the first and fourth serial transceivers. In one embodiment according to the present invention, the four serial transceivers are pluggable transceiver modules.

Abstract: The present disclosure relates to a magnetic field sensor circuit including at least one coil for measuring a magnetic field, a first stage amplifier circuit coupled to the coil and having a first transfer function with a pole at a first frequency, and a second stage amplifier circuit coupled to an output of the first stage amplifier circuit and having a second transfer function with a zero at the first frequency. In some embodiments, a temperature dependent frequency drift of the pole of the first transfer function corresponds to a temperature dependent frequency drift of the zero of the second transfer function.

Abstract: An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Abstract: A differential operational transconductance amplifier, or DOTA, intended to be used in zero-drift precision operational amplifiers as chopper amplifier stage is disclosed. The DOTA is configured to function with a low-voltage power supply and to have good performance based on circuitry configured to provide a constant gain over a range of common-mode voltages, or VCM. The DOTA further includes bias circuitry configured to respond to the common mode voltage in order to prevent large currents, which can result from the constant gain circuitry, from negatively affecting performance. The DOTA further includes current sources that are configured to prevent temperature variations from negatively affecting performance. The DOTA further includes VCM-driven bias voltages used to optimize the operating point of the differential output stage. The DOTA uses input and input replica transistors having medium threshold voltage, which results in capability to operate at low supply voltages.

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

Abstract: Examples are disclosed herein that relate to automatically limiting an output current of a voltage regulator circuit responsive to detecting that the voltage regulator is in a current overload mode. In one example, a voltage regulator circuit includes an amplifier stage and a current limiter stage electrically connected to an output of the amplifier stage. The amplifier stage is configured to output a DC voltage based on a reference voltage and feedback from an output voltage. The current limiter stage is configured to operate in a quiescent mode and an overload mode. In the quiescent mode, the current limiter stage is configured to operate as a buffer stage that forms a closed feedback loop to an input of the amplifier stage. In the overload mode, the current limiter stage is configured to act as a current source that clamps an output current to a designated current.

Abstract: Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit 1 including a differential amplifier circuit 10, a switch circuit 20, and a hold capacitor C21, the differential amplifier circuit 10 includes a first resistor R11 having one end connected to a collector electrode of a first transistor Q11 constituting a differential pair, a second resistor R12 having one end connected to the collector electrode of a second transistor Q12 constituting the differential pair, and a third resistor R13 to which the other end of the first resistor R11 and the other end of the second resistor R12 are connected and which is connected between the other ends and a power supply VCC.

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

Abstract: A system includes a power supply source and a power control circuit coupled to the power supply source, in which the power control circuit includes a pass field-effect transistor (FET). The system also includes a short-to-ground protection circuit coupled to an output of the pass FET. The short-to-ground protection circuit includes a sense circuit configured to detect when a magnitude and a change rate of a voltage drop at the output of the pass FET is greater than respective thresholds. The short-to-ground protection circuit also includes a control node at the output of the sense circuit. The sense circuit is configured to induce a control current at the control node in response to the magnitude and the change rate of a voltage drop at the output of the pass FET being greater than respective thresholds. The control current is used to turn off the pass FET.

Abstract: A filter can perform two filtering processes. The filter includes a switching circuit, a first filter circuit, and a second filter circuit. The first filter circuit is coupled to the switching circuit. The second filter circuit is coupled to the switching circuit. The first filter circuit performs a first filtering process on an input signal according to a state of the switching circuit. The first filter circuit and the second filter circuit work together to perform a second filtering process on the input signal according to the state of the switching circuit.

Abstract: A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.

Abstract: A data transmission circuit includes: a main driver circuit suitable for driving data to an output line; an amplitude equalization window generator circuit suitable for detecting the data transitioning from a first level to a second level; an auxiliary driver circuit suitable for driving the output line with the second level in response to a detection result of the amplitude equalization window generator circuit; and a phase equalization window generator circuit suitable for detecting whether the data consecutively has the first level, wherein the main driver circuit changes a time point of driving the data in response to a detection result of the phase equalization window generator circuit.

Abstract: An impedance circuit includes a first impedance terminal, a second impedance terminal, a first transistor, a second transistor, a low frequency signal blocking element, and a current-voltage transform circuit. The first transistor is coupled to the first impedance terminal, and controlled by a first voltage. The second transistor is coupled to the first impedance terminal, and controlled by a second voltage. The low frequency signal blocking element is coupled to the first transistor and the second impedance terminal. The current-voltage transform circuit is coupled to the first impedance terminal. The current-voltage transform circuit adjusts a terminal voltage at the first terminal of the current-voltage transform circuit according to a current flowing through the current-voltage transform circuit. The impedance circuit provides impedance between the first and the second impedance terminals according to the terminal voltage and the first voltage.

Abstract: A differential comparator circuit is provided that includes a differential input pair, an active load, a pair of cross voltage generation devices and a pair of switches. The differential input pair has a pair of input terminals and a pair of first connection terminals. The active load has a pair of second connection terminals. The cross voltage generation devices are electrically coupled between the first connection terminals and the second connection terminals, wherein the cross voltage generation devices are configured to be electrically activated to establish a cross voltage therebetween in a reset phase and electrically deactivated to become a short circuit in an operation phase. The switches are configured to electrically couple the pair of input terminals respectively to the pair of first connection terminals in the reset phase and not electrically couple the pair of input terminals respectively from the pair of first connection terminals.

Abstract: In an embodiment, an amplifier includes first, second, and third stages, and a feedback network. The first stage has a first passband and is configured to generate a first output signal in response to first and second input signals, and the second stage has a second passband that is higher in frequency than the first passband and is configured to generate a second output signal in response to third and fourth input signals. The third stage has a first input node coupled to receive the first output signal, a second input node coupled to receive the second output signal, and an output node. And the feedback network is coupled between the second input node and the output node of the third stage. For example, where the first, second, and third stages are respective operational-transconductance-amplifier stages, such an amplifier may be suitable for low-power applications.

Abstract: A radio-frequency module includes a substrate, a low-noise amplifier circuit being a first amplifier circuit arranged in a first area in the substrate, a power amplifier circuit being a second amplifier circuit arranged in a second area in the substrate, and a duplexer being a component arranged between the first area and the second area in the substrate and having a heat generating property lower than that of the power amplifier circuit. The low-noise amplifier circuit includes a bias circuit configured to generate a bias current dependent on temperature characteristics of a first diode, a voltage generating circuit configured to generate a voltage dependent on temperature characteristics of a second diode as an operating voltage for the bias circuit, and an amplifier circuit configured to operate at an operating point determined by the bias current.

Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.

Abstract: An apparatus and method are provided. The apparatus includes a multiplexer, including first, second, and third inputs, and an output; a first transistor, including a gate connected to the multiplexer, and first and second terminals; a first variable capacitor, including a first terminal connected to the first transistor, a second terminal, and an input; a first inductor, including a first terminal connected to the first transistor, and a second terminal connected to the second terminal of the first variable capacitor; a second transistor, including a gate connected to the output of the multiplexer, a first terminal, and a second terminal connected to the second terminal of the first inductor; a second inductor mutually coupled to the first inductor, including a first and second terminals; and a balun-bias switch, including first, second, and third inputs, and an output connected to the second terminal of the second inductor.

Abstract: A differential amplifier includes a pair of cascode amplifiers. A voltage clamp is coupled to the pair of cascode amplifiers.

Abstract: A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.

Abstract: Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

Abstract: A buffer is provided where a part of the buffer is implemented in switched capacitor or other analog discrete time processing circuitry and a dynamic response characteristic, such as an effective gain or charge transfer coefficient between the input stage and an output stage is digitally controllable. This means that the buffer can be driven as if it was a system controlled by, for example a three (3) term controller, giving rise to greater, digital flexibility in tailoring the buffer's transient response.

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

Abstract: A switching amplifier provided, at a minimum, with: a first input transistor into which one of two input signals that operate in a complementary manner is input; a first cascode transistor cascade-connected between the first input transistor and a power supply; a second input transistor into which the other of the two input signals is input; and a second cascode transistor cascade-connected between the second input transistor and the first input transistor; the switching amplifier extracting an output signal, a connection point between the first input transistor and the second cascode transistor being used as an output terminal; wherein a first potential limiting circuit and a second potential limiting circuit for limiting the potential fluctuation range are respectively connected to the input terminal of the first cascode transistor and the input terminal of the second cascode transistor.

Abstract: An electronic circuit including a current conveyor connected to a load is provided. The load delivers at least one first voltage output and one second voltage output. Such a circuit is noteworthy in that the second voltage output has what is called a non-linear behavior relative to the magnitude of the input current of the electronic circuit in a given range.

Abstract: A charge pump comprises a charge pump circuit with bipolar switching devices with a common emitter. A collector line which comprises a first current source connects to the high potential provider. An emitter line connects the common emitter to a low potential provider and comprises a second current source. The output is provided by or connected to the collector of the second bipolar switching device and provides said output voltage. A driving stage circuit applies a charge pump circuit driving signal across the bases of the bipolar switching devices and controls the charge pump circuit driving signal in accordance with a driving stage input signal. The driving stage circuit effects a shift of a DC operating point of the charge pump circuit driving signal as an increasing function of the output voltage function of the output voltage of the charge pump circuit.

Abstract: A current source circuit flowing an output current to at least one detection element including a first terminal to which a first voltage is supplied and a second terminal being connected to the current source circuit includes a reference resistance, a current mirror circuit including at least one first transistor and at least one second transistor, and a control circuit controlling a voltage of a common wire that is connected to a terminal provided at the first transistor and a terminal provided at the second transistor such that a voltage of a terminal provided at the reference resistance comes to be equal to a reference voltage.

Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.

Abstract: A differential amplifier circuit and display drive circuit having the same are disclosed herein. In one example, a differential amplifier circuit includes a differential pair transistor configure to receive a differential input signal. A current source is connected in series to the differential pair transistor and an output transistor that drives an output terminal on the basis of the differential input signal. The output transistor is configured to increase a current value of a current source on the basis of a timing at which a voltage level of the output terminal is caused to transition. The output transistor is configured to drive the output terminal only during a period in which the output terminal is caused to transition, and thus a slew rate is improved by increasing a bias current of the differential pair transistor in the period.

Abstract: Described herein is an electronic device. The electronic device includes a unity gain buffer having an input coupled to an input node to receive an input voltage and an output coupled to an output node. A current sink circuit operates in a sleep mode in an absence of a sink current flowing into the output node, and operates in a sinking mode to sink the sink current from the output node to a reference supply node when the sink current flows into the output node.

Abstract: Provided is a technology capable of preventing arithmetic operation accuracy from deteriorating even when a bipolar transistor used to form a Gilbert multiplier core has poor characteristics. A correction current generating circuit (3) uses a constant current source (301) to feed a constant current I0 to an emitter of a bipolar transistor (Q7) being a first replica transistor having the same current gain ? as bipolar transistors (Q1 to Q4) that form the Gilbert multiplier core (101), to generate a current of ?·I0 on a collector side thereof. The current is output as a correction current ?·I0, and is added to each of one of input signals (±K1·Vy) of the Gilbert multiplier core (101) as a bias current, to thereby eliminate influence of the current gain ? on an output signal being a multiplication result.

Abstract: Disclosed is a compensation circuit for a common voltage according to a gate voltage, which compensates the common voltage in accordance with variation in gate high voltage, to obtain an optimal common voltage. The compensation circuit includes a divider to divide a gate high voltage, an adder to add a fed-back common voltage to a voltage output from the divider, and a differential amplifier to differentially amplify a voltage output from the adder, and to output the amplified voltage as a compensated common voltage.

Abstract: A high slew rate operational amplifier including an input terminal, an output terminal, and at least one slew-rate enhancing circuit is disclosed. Each slew-rate enhancing circuit includes a first stage enhancing unit and a second stage enhancing unit. The first stage enhancing unit is coupled between the input terminal and the output terminal. The first stage enhancing unit and the second stage enhancing unit are coupled. The slew-rate enhancing circuit has a threshold voltage and the threshold voltage is related to the size of the first stage enhancing unit. When the threshold voltage is driven, the slew-rate enhancing circuit will rapidly start the second stage enhancing unit to perform a slew rate compensation on the high slew rate operational amplifier.

Abstract: A pixel compensation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a switch unit and a light emitting diode. The first transistor, the third transistor, the fourth transistor, the fifth transistor, and the switch unit are used to receive a respective switch signal. The pixel compensation circuit can compensate a threshold voltage of transistor automatically; and consequentially a driving current of light emitting diode is prevented from being affected by the change of the threshold voltage or the voltage drop of the light emitting diode.

Abstract: A differential amplifier with cascade transistors connected in series to switching transistors is disclosed. The base bias of the cascade transistors is set higher than the output LOW level of the cascade transistors by a preset amount of 0.1 to 0.2V, or lower than the input HIGH level of the switching transistors by the preset amount adding to a forward voltage of a junction diode, to provide a discharge current of the base-emitter junction Cbe from the bias control, or from the upstream stage to drive the differential circuit.

Abstract: A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.