Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.

Abstract: An operational amplifier including a primary differential input pair, a primary tail current source module, N auxiliary differential input pairs, and N auxiliary tail current source modules is disclosed. A first and a second input terminal of the primary differential input pair respectively receive a first and a second input signal, wherein first input signal and the second input signal are differential to each other. The primary tail current source module supplies a tail current to the primary differential input pair during a first time interval. A first and a second input terminal of each of the auxiliary differential input pairs respectively receive the first and the second input signal. Each of the auxiliary tail current source modules supplies an auxiliary tail current to the corresponding auxiliary differential input pair during a second time interval. The first time interval and the second time interval partially overlap each other.

Abstract: A common-mode feedback circuit includes an amplifying circuit, a biasing circuit connected with the amplifying circuit, and a feedback loop connecting the amplifying circuit with the biasing circuit. The feedback loop includes a first field effect transistor M1, a eighth field effect transistor M1B connected with the first field effect transistor M1, a tenth field effect transistor M2B and an eleventh field effect transistor MFB connecting the eighth field effect transistor M1B and the tenth field effect transistor M2B. The common-mode voltage value of the common-mode feedback circuit is adjusted by the eleventh field effect transistor MFB. The common-mode feedback circuit has the simple structure and is capable of achieving the common-mode feedback without the peripheral feedback circuit and the input reference voltage.

Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Abstract: An ultra-low-power circuit for wireless neural recording and stimulation is provided. The circuit includes a neural amplifier with adaptive power biasing for use in multi-electrode arrays and a decoding and/or learning architecture. An impedance-modulation telemetry system provides low-power data telemetry. Also, the circuit includes a wireless link for efficient power transfer, and at least one circuit for wireless stimulation of neurons.

Abstract: An apparatus including cascaded amplification stages adapted to be biased by a common DC current to generate an amplified output signal from an input signal. A first amplification stage includes a routing network to substantially double an input voltage signal, and a first transconductance gain stage to generate a first current signal from the input voltage signal. A second amplification stage includes a resonator to convert the first current signal into a second voltage signal, and a second transconductance gain stage to generate a second current signal from the first current signal. A third amplification stage includes a current gain stage to generate a third current signal from the second current signal, and a load through which the third current signal flows to generate the output signal.

Abstract: An amplifier with a cascode device contains a common mode feedback circuit to ensure correct operating point in the amplifier. Common mode feedback is provided to the amplifier to maintain the common mode operating point during active operation. Additional common mode feedback is provided to the cascode devices to ensure correct start-up by forcing the node voltages to go to their desired voltage levels.

Abstract: Aspects of a system for improving efficiency over power control for linear and class AB power amplifiers may include a current source circuit that enables determination of a bias current level for a PA circuit within an IC die based on an amplitude of an input modulation signal. The PA circuit may enable generation of an output signal based on a differential input signal and the input modulation signal to the current source circuit. A generated bias voltage may be applied to a transformer external to the IC die, but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels may be applied to the PA circuit wherein the amplifier bias voltage levels may be derived from the generated bias voltage level and/or the determined bias current level.

Abstract: To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.

Abstract: A voltage detection circuit includes operational amplifiers, a battery, and a voltage circuit. The voltage circuit offsets the inverting input terminals and non-inverting input terminals of the operational amplifiers to the positive side with reference to a ground GND.

Abstract: Methods and systems for a single-ended input low noise amplifier (LNA) with differential output are disclosed and may include configuring the LNA and/or a balun on a chip for single-ended or differential mode, which may function as a load for the LNA. A frequency response and gain of the LNA may be configured via switched capacitors and resistors, which may include CMOS transistors. A transition frequency, and thus impedance matching and matching network gain, may be tuned via configurable gate-source capacitors. A received signal may be filtered via a surface acoustical wave (SAW) filter. The LNA may be impedance matched with an input device via the transition frequency tuning and off chip inductors and/or capacitors. The LNA may be configured for single-ended or differential input mode via switches outside of a signal path to the LNA and reverse isolation may be enabled via a cascode device.

Abstract: An amplifier circuit includes: a field-effect transistor including a first gate, a first source and a first drain, the first gate receiving one of differential signals, and the first source being connected to a reference potential node; a field-effect transistor including a second gate, a second source and a second drain, the second gate receiving the other of the differential signals, and the second source being connected to a reference potential node; a first transformer including a first inductor and a first secondary inductor which are magnetically coupled together, the first inductor being connected between the first drain of the first field-effect transistor and the second drain of the second field-effect transistor, and the first secondary inductor being connected between an output terminal and a reference potential node; and a first switch circuit connecting a power-supply potential node or a reference potential node to a midpoint of the first inductor.

Abstract: A circuit for power amplification of an input signal includes an input stage and an output stage, the said input stage including: a drive means incorporating a so-called main drive transistor, and a first so-called main input transistor able to receive the input signal, and mounted as a current mirror with the main drive transistor The first main input transistor is coupled to the output stage via a second so-called main input transistor incorporated into the input stage and controlled by the drive means, the first and second main input transistors being coupled together and with the earth according to a structure of Darlington type by way of a resonant circuit

Abstract: An integrated circuit includes an input unit and a voltage level detecting unit. The input unit is configured to output differential amplification signals corresponding to differential input signals in response to a voltage level detection signal. The voltage level detecting unit is configured to detect a voltage level of the differential amplification signals and output the voltage level detection signal.

Abstract: An embodiment includes a first amplification device receiving a high frequency signal in an upstream stage in an initial stage unit and having a predetermined thermal time constant, a second amplification device in a downstream stage cascade-connected to the first amplification device and having a thermal time constant different from that of the first amplification device, and a final stage amplification device cascade-connected in a final stage downstream of the second amplification device.

Abstract: An amplification circuit may include an input differential pair including a first transistor receiving a positive input voltage and a second transistor receiving a negative input voltage, a first resistor that generates a difference current corresponding to a difference voltage between the positive input voltage and the negative input voltage, an output differential pair including a third transistor supplying a negative output voltage and a fourth transistor supplying a positive output voltage, a second resistor connected to a reference voltage to receive the difference current generated by the first resistor, and a bias circuit that supplies a bias current to the first transistor, the second transistor, the third transistor, and the fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor may have the same polarity.

Abstract: A differential amplifier includes: an output amplifier circuit; a bias circuit; and a pulse applying circuit. The output amplifier circuit receives a positive gradation voltage and a negative gradation voltage alternately by an input stage circuit and supplies a drive voltage generated based on the gradation voltage to a display panel. The bias circuit generates a bias voltage in synchronization with a strobe signal which is a trigger for a polarity inverting operation of the gradation voltage and applies the bias voltage to a constant current source controlling a current of the input stage circuit. The pulse applying circuit generates a pulse voltage having a voltage level higher than a voltage level of the bias voltage and couples the pulse voltage to the bias voltage.

Abstract: An electronic device has a manipulation part which outputs a control signal including a first analog signal and a second analog signal obtained by inverting a phase of the first analog signal; and a display part which includes a semiconductor integrated circuit supplied at an input terminal thereof with the control signal to output a signal depending upon the control signal from an output terminal thereof, and which displays a predetermined image based on the signal output from the semiconductor integrated circuit.

Abstract: An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.

Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer.

Abstract: In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage.

Abstract: A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained.

Abstract: An equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.

Abstract: An amplifier comprising at least one amplifying element (20a, 25a) and a biasing circuit (32a, 32b) for biasing the or each amplifying element with a bias voltage is disclosed. The biasing circuit (32a, 32b) is adapted to vary the bias voltage such that the or each amplifying element switches between non-switching and switching modes of operation in response to a bias control signal (4) passing through a threshold value.

Abstract: A motor driver circuit for driving the gate node of a high-side driver transistor to a boosted voltage from a charge pump draws little or no static current from the charge pump. The gate node is pulled to the boosted voltage by a p-channel pullup-control transistor that is driven by p-channel transistors that are pumped by capacitors that cut off current flow to ground from the charge pump. An n-channel output-shorting transistor shorts the gate node to the output when the high-side driver is turned off. A coupling capacitor initializes the shorting transistor for each output transition. A p-channel output-sensing transistor generates a feedback to a second stage that drives the coupling capacitor. P-channel diode transistors and an n-channel equalizing transistor control the voltage on the coupling capacitor.

Abstract: A front-end equalizer and amplifier circuit includes two pairs of fully differential pair transistors, wherein the tail currents of one pair of transistors are connected with ground and connected with each other through the capacitive component to realize the connection between the pair of transistors and the feedback capacitor, the tail currents of the other pair of transistors are connected with ground and connected with each other through the resistive component to realize the connection between the other pair of transistors and the feedback resistor, the output positive and negative ends of each pair of transistors are connected with each other through the inductive component, thus forming the load for connecting the voltage source. The circuit increases the high frequency gain. Its single-stage gain is equivalent to the multi-stage gain. Compared with the traditional multi-stage structure, the present invention decreases the power consumption and area, and improves the reliability.

Abstract: The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: Embodiments of the present invention provide DC biasing circuits. Embodiments employ an open loop scheme, instead of a closed loop scheme as used in conventional circuits. In addition, embodiments generate a DC bias voltage that is independent of temperature, process, and power supply variations. Further, embodiments require low amounts of power and silicon.

Abstract: A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.

Abstract: A micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays is provided. The micropower neural amplifier includes a low noise gain stage. The low noise gain stage is implemented using an amplifier and pseudoresistor elements.

Abstract: A multi-stage amplification type class-AB operational amplifier disclosed includes an amplification stage having plural amplification sections formed in multiple stages, and a class-AB output stage having a bias section and an output section, in which an input signal input to the amplification stage is sequentially amplified by the plural amplification sections, and further amplified by the bias section and the output section of the class-AB output stage. A positive supply voltage applied to the amplification stage is different from a positive supply voltage applied to the class-AB output stage, and a negative supply voltage applied to the amplification stage is different from a negative supply voltage applied to the class-AB output stage.

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: An electronic circuit comprises at least two transistors coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor is biased with a first gate-source voltage and a first drain-source voltage. The second transistor is biased with a second gate-source voltage and a second drain-source voltage. The first and second gate-source voltages are offset from each other by a gate-source voltage offset. The first and second drain-source voltages are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors operating in different regions so that the second and third-order nonlinearities of the transistors substantially cancel each other out simultaneously.

Abstract: Provided is an output buffer, which may be included in a source driver of a liquid crystal display (LCD) device. The output buffer may include a differential amplification unit and an output unit. The differential amplification unit may generate control currents by amplifying the difference between the voltages of an analog image signal and a signal output from the output buffer. The output unit outputs the amplified analog image signal in response to the control currents. The amount of bias current used to drive the differential amplification unit increases during a charge recycling period, and the amount of quiescent current flowing through the output unit decreases during the charge recycling period. The amount of the bias current used to drive the differential amplification unit decreases during a driving period, and the amount of the quiescent current flowing through the output unit increases during the driving period.

Abstract: An output stage of a class-AB amplifier, including: a first transistor of a first channel type between a first terminal of application of a first voltage and an output terminal of the stage, having its gate connected to a first input terminal of the stage; a first transistor of a second channel type between this output terminal and a second terminal of application of the first voltage, having its gate connected to a second input terminal of the stage; and second and third transistors of the second channel type between the output terminal and the first transistor of the second channel type, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor of the second channel type, and the gate of the third transistor being biased to a fixed voltage.

Abstract: An amplifier circuit having a differential input and an amplifier output is provided. In some examples, the amplifier circuit includes a first input stage having a first complementary transistor pair providing a first input and a first output, the first input being a first half of the differential input; a second input stage having a second complementary transistor pair providing a second input and a second output, the second input being a second half of the differential input; an output stage coupled to the first input stage and the second input stage and providing the amplifier output; and a transistor coupled in parallel to one transistor in one of the first complementary transistor pair or the second complementary transistor pair.

Abstract: A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: A current control circuit for controlling a bias current of a class AB operational amplifier includes: a low current source, for generating a low bias current; a high current source, for generating a high bias current, which is greater than the low bias current; and a comparing and selecting unit, coupled to an output terminal of the class AB operational amplifier, for selecting one of the low bias current and the high bias current to output as the bias current according to an output voltage of the class AB OP.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.

Abstract: A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

Abstract: A selectable gain amplifier includes two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output. The amplifier further includes and two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: A pre-driver includes first to fourth transistors and first and second impedance elements. The first transistor, coupled between the first output terminal and a first node, has a gate coupled to the first differential input terminal. The second transistor, coupled between the second differential output terminal and the first node, has a gate coupled to the second differential input terminal. The third transistor, coupled between the first differential output terminal and a second node, has a gate coupled to the first differential input terminal. The fourth transistor, coupled between the second differential output terminal and the second node, has a gate coupled to the second differential input terminal. The first and second impedance elements are coupled between the first differential output terminal and a third node, and coupled between the second differential output terminal and the third node, respectively, wherein the third node is biased to a preset voltage.

Abstract: Disclosed is an operational amplifier including an overdriving circuit capable of reaching a target voltage within an operation time by outputting a higher voltage than the target voltage when an RC delay time is greater. The operational amplifier may including an overdriving circuit, in which first and second input terminals and an output terminal may be provided, an input voltage may be applied to the first input terminal, a second input terminal may be connected to the output terminal, and the input voltage applied to the first input terminal may be overdriven to have a certain level to be outputted to the output terminal, may include: first and second overdriving units performing an overdriving operation at a rising edge and a falling edge, respectively.

Abstract: A driver circuit for a semiconductor laser diode (LD) is disclosed, in which the driver circuit drives the LD in the differential mode and lowers the power consumption thereof. The driver circuit includes a differential unit to provide the modulation current to the LD, a voltage converter to provide a positive power supply to the differential unit, a detector to detect the common mode voltage of the differential outputs of the unit, and a comparing unit to control the voltage converter dynamically such that the output common mode voltage is set in a preset reference level.

Abstract: The present disclosure describes a variable gain transconductor having gain and/or linearity performance that are selectively controllable in operation. In one embodiment the gain and/or linearity performance are selectively controllable in response to the strength of an input signal, such as an incoming radio frequency (RF) signal to a radio receiver. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a number of operating bias cells. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a number of operating transconductance (gm) cells. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a combination of operating bias cells and gm cells.

Abstract: A multi-mode driver and method therefore includes a plurality of amplifiers, an adjustable load block, and adjustable current supply circuitry that selectively adjusts current magnitudes supplied to at least one of the plurality of amplifiers. The multi-mode driver can operate in a KR mode with a higher voltage supply, an SR4 mode with the higher voltage supply, and an SFI mode with a lower voltage supply. To support these modes, the multi-mode driver selectively operates a plurality of amplifiers, adjusts current magnitudes supplied to the amplifiers, and selectively adjusts an adjustable load. Thus, the multi-mode driver is operable to selectively and efficiently produce high swing and low swing output signals and to efficiently operate with any one of a plurality of supplies. The driver includes selectable loads and parallel-coupled amplifier devices that are selected based on mode.