Abstract: Transceiver for transmission over serial bi-directional links having a bi-directional amplifier including an impedance (R) for adaptation to the line and connected to it, a generator (G1) commanded for transmission and supplying the adaptation impedance (R) and the line in parallel, detection device (G2, r) for furnishing a measurement signal (V) representative of either the current circulating in the adaptation impedance (R) when the generator (G1) is active, or the sum of the current in the adaptation impedance (R) and a compensation value when the first generator (G1) is not active. The compensation value is determined so as to make the measurement signal (V) independent of the transmission state of the transceiver.

Abstract: Integrated circuit structure and processing is provided for a high power limiter including at least a first anti-parallel array of monolithically integrated Schottky diodes. In a further embodiment, integrated circuit structure and processing is provided for an MMIC, microwave and millimeter wave monolithic integrated circuit, including an amplifier and a high power limiter monolithically integrated on the same substrate.

Abstract: A high-frequency power amplifier device is provided in which the number of ground lines on the electronic parts mounting face of a strip line substrate having microstrip lines is reduced or eliminated. Specifically, a metallic cover extending in parallel with the mounting face of the strip line substrate is grounded, and the microstrip lines between this cover and the strip line substrate are electrically connected by connecting means such as capacitors and/or conductors.

Abstract: A low drift integrated circuit resistor structure has a forced high end and a forced low end. A sense high connection is located proximate to the force high connection, and a sense low connection is located proximate to the force low connection. The structure also has at least one internal sense connection. This structure can be used in an instrumentation amplifier that includes an operational amplifier which regulates the current between the force high connection and the force low connection in response, in part, to the current sensed in the internal sensing connection of the resistor structure. The sense high connection and the sense low connection form the outputs of the instrumentation amplifier.

Abstract: in a semiconductor array having a tetrode integrated in a semiconductor element, the tetrode comprises two field-effect transistors having a common semiconductor area forming the drain electrode of the first field-effect transistor and the source electrode of the second field-effect transistor. The semiconductor array has a three-pole array integrated in the semiconductor element and functioning as a feedback element, the input of the array is connected to the common semiconductor area of the tetrode. The output of the three-pole array is connected to the semiconductor area forming the gate electrode of the first field-effect transistor of the tetrode.

Abstract: A quasi-interdigitated transistor (50) for rf power applications has a plurality of channel regions (102-118) that are each offset from each other in a y-direction such that a q.sub.x heating component from adjacent channel regions will affect any one channel region to a lesser extent that the q.sub.x from adjacent channel regions in the conventional interdigitated structure. In a preferred embodiment, the channel regions (102-118) are formed in a single, curved, V-shaped row such that the cumulative transverse width of all of the transistor sections is less than the waveguide cutoff frequency. The V-shaped row of transistor sections also provides the advantage of parallel signal paths having approximately the same propagation time delay such that there is no phase cancellation within the device.

Abstract: As a switch circuit SW1 is incorporated in an integrated circuit, the number of IC terminals is proportionately reducible. On receiving a mute input signal Min, a mute circuit 13 generates a mute control signal M1 and subsequently a mute control signal M2 later than M1. On receiving the mute control signal M1, the switch circuit SW1 grounds the signal line of an audio output signal A, whereas on receiving the mute control signal M2, a switch circuit SW2 cuts the signal line of an audio input signal I later. A muting function can thus be fulfilled stably.

Abstract: A semiconductor device comprises a plurality of gate electrodes, drain electrodes, and source electrodes axi-symmetrically formed on opposite sides of a gate pad and drain pad. Two source pads are arranged at ends of these electrodes, to which the source electrodes are connected, so that a gate width can be shortened. Therefore, an output power, gain, etc., can be increased, and the high-frequency characteristics can be improved. Further, when arranging a plurality of semiconductor devices in parallel, the semiconductor chip can be formed in the shape of a square, i.e., the aspect ratio thereof can be reduced, and therefore, cracks in the semiconductor chip (semiconductor device) can be avoided.

Abstract: A small-sized, high-efficiency semiconductor amplifier exhibits a satisfactory efficiency characteristic over a wide band and a low output level for secondary and tertiary higher harmonics.

Abstract: A low drift integrated circuit resistor structure has a forced high end and a forced low end. A sense high connection is located proximate to the force high connection, and a sense low connection is located proximate to the force low connection. The structure also has at least one internal sense connection. This structure can be used in an instrumentation amplifier that includes an operational amplifier which regulates the current between the force high connection and the force low connection in response, in part, to the current sensed in the internal sensing connection of the resistor structure. The sense high connection and the sense low connection form the outputs of the instrumentation amplifier.

Abstract: Described is a circuit arrangement for amplifying weak sensor currents, in particular the photoelectric current of a photoelectric diode (1), in which the photoelectric diode is connected to the base or gate electrode of a transistor (2). A constant current source (3) is connected into the collector circuit of the transistor (2). Connected between the collector and the base is a negative feedback which includes a current step-down circuit using at least one current mirror (6). The mother or sum current (I.sub.S) is coupled out as the amplified signal current.

Abstract: In a hybrid microwave integrated circuit in which an FET and an LC resonance circuit are integrated, the LC resonance circuit includes an inductor and a capacitor disposed on a substrate having a smooth surface which ensures that the dimensional precision of the inductor will be in a range of.+-.several microns when it is formed on the substrate. Then, the substrate, on which the LC resonance circuit is formed, is mounted on or buried in a high frequency signal transmitting substrate. Therefore, variation in resonant frequency of the LC resonance circuit are reduced, whereby deteriorations in characteristics, such as efficiency, output power and the like, are reduced. In addition, since the LC resonance circuit is reduced in the size and cost of the whole circuit are reduced.

Abstract: A high power field effect transistor (FET) amplifier which can provide a high gain over a wide bandwidth of a microwave range includes, on a first substrate on which a grounded-source field effect transistor is disposed, a series combination of an inductor and a capacitor connected between the gate of the FET and ground. The gate of the FET is coupled to an input impedance matching circuit disposed on a second substrate. The drain of the FET is coupled to an output impedance matching circuit disposed on a third substrate.

Abstract: A multistage amplifier for amplifying an input signal so as to output an amplified signal. The multistage amplifier is comprised of a plurality of transistors that are monolithically formed around a central VIA hole. Predetermined electrodes of the respective transistors are electrically connected to each other in the area immediately surrounding the central VIA hole and are connected to the VIA hole itself. This allows for a reduction of the number of VIA holes used over conventional methods. The distance between the central VIA hole and the predetermined electrodes of each of the transistors is minimal, as is the wiring pattern of each of the electrodes. No scattering is caused by the characteristics of the transistors, as they are monolithically formed in the same manufacturing process.

Abstract: For use in a spacecraft for correcting amplifier distortion, a wideband distortion corrector avoids the need for directional couplers. The corrector includes a FET mounted in a miniature microwave-type housing. Signal flows through the source-to-drain channel. A gate impedance selected to be inductive at the operating frequency is coupled from the FET gate to the platform of the package, and may be simply a loop of bond wire. The channel connects by a strip transmission line to an amplifier, the distortion of which is to be corrected. For enhanced bandwidth, an inductor is coupled between the FET source and drain electrodes within the miniature housing. The platform of the package is coupled to the reference conductor of the transmission line. In one embodiment, direct bias voltage is applied by way of a bias tee across a strip transmission line and ground, and galvanic connections cause the bias to appear between the FET gate electrode and the channel.

Abstract: A CMOS integrated circuit incorporating both logic functions and analog functions. The latter are subjected to noise from the logic transitions by means of supply conductors. To avoid disturbing the rest point of an amplifier by this supply noise, without using compensation circuits which would increase the number of pins of the integrated circuit, it is proposed to supply a pair of complementary transistors forming an amplifier stage by identical incoming and outgoing current generators. These generators are transistors copying a current from a current mirror circuit which includes a pair of complementary transistors connected between the two power supply lines.

Abstract: A transistor in which the emitter terminal is coupled to ground through a filter capacitor. The filter capacitor has a capacitance of from about 0.2 .mu.f to about 22 .mu.f and can be connected either by itself or in parallel with a resistor, depending upon the circuit in which it is used. The incorporation of a filter capacitor of such a capacitance level provides greatly improved gain and less distortion of the input signal, to permit a high output to be achieved in fewer amplifier stages and with less current draw and heating than in conventional transistor amplifier stage circuits. Additionally, the transistor can be provided in a unitary structure by incorporating the filter capacitor directly on the transistor chip, and can also be provided by incorporating the transistor and a resistor within the casing of a filter capacitor.

Abstract: A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

Abstract: A series resonant circuit (17, 16, 22, 21, 19) is employed to minimize the area utilized to form an RF amplifier (10). The series resonant circuit (17, 16, 22, 21, 19) utilizes a capacitor (21) along with inductors (17, 19, 22) that are formed by bonding wires (17, 19, 22) which interconnect the components of the amplifier (10). The series resonant circuit is tuned to the second harmonic of the fundamental frequency applied to the RF amplifier (10). The area consumed by the series resonant circuit (17, 16, 22, 21, 19) is small thereby minimizing the amplifier's size.

Abstract: There is disclosed a microwave device having a substrate made of a dielectric material and a frequency conversion circuit formed on a front surface of the substrate and including a microstrip line for input and output and a radio frequency amplifier. The substrate is partially thinned in a portion of a rear surface thereof which faces the radio frequency amplifier. The microstrip line width is a change in the characteristic impedance of microstrip lines which cross the front surface of the substrate where its thickness changes due to the partially thinned portion, is smaller than 10%.

Abstract: An octave band decade watt power amplifier is disclosed using compact and efficient MMIC fabrication techniques. The power amplifier is a two stage amplifier in which the driver transistor has two cells, and the power transistor has four cells, with each power cell double the size of the driver cells. Both transistors are of an optimized topology facilitating efficient broad band operation at matchable impedance levels. They are interconnected by three four section impedance matching networks of which the input network is coupled to a 50 ohm signal input terminal. The input and the interstage network are both formed on the same substrate as the transistors. The output network is formed on a separate substrate having a high dielectric constant (i.e. 37) which facilitates efficient and compact matching of four power transistor cells to a single output terminal for connection to a load at the conventional (50 ohm) impedance.

Abstract: A high frequency amplifying device comprises a field effect transistor-bipolar transistor darlington pair. Such a device combines the main desirable features of both field effect transistors and bipolar transistors, therefore, having a high input impedance that is typical of FETs and a high transconductance (or high current gain) which is typical of bipolar transistors.

Abstract: A post-assembly trim of a monolithic IC is set forth wherein selected package pins can be employed to address the on-chip trim circuit. Then, after the trim is completed, the circuit is addressed to provide a disconnect of the coupling between the trim pins and the post assembly trim circuit of the IC, while leaving the pins fully usable for other purposes. This means that following the post-assembly trim the trim pins cannot accidentally be employed for further trimming and the packaged IC is user-proof. A circuit that employs zener zapping for both trimming and disconnect is detailed and the invention is clearly usable for plastic encapsulated devices. However, when cavity containing packages are involved it is shown that a combination of zener zapping and fuse blowing can be employed.

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

Abstract: Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.

Abstract: A variable gain wideband bipolar monolithic amplifier has first and second bipolar transistors connected together in a Darlington configuration. A resistive shunt feedback loop connected between the output and the input of the amplifier controls the gain of the amplifier. The feedback loop includes a field effect transistor, formed on the same chip substantially by the same bipolar process as the bipolar transistors, for varying the impedance of the shunt feedback loop thereby varying the gain of the amplifier. The gain of the amplifier is controlled in response to the application of a control voltage to the gate of the FET. Further, the FET is dc biased for inhibiting the FET from drawing dc current.

Abstract: The amplifier employs an FET having a flat characteristic of mutual conductance versus the potential gap between the gate and the source of the FET. By employing this FET, the amplifier achieves a sufficiently flat gain characteristic in which the gain deviation is very small throughout the range of the objective frequencies.

Abstract: An RF power device including a DMOS field effect transistor has increased efficiency and reduced distortion. A capacitor is connected between the gate and source input of the transistor which swamps non-linear variations of the parasitic capacitance (C.sub.GD) between the gate and drain, thereby offsetting the Miller effect of the feedback provided by the MOS transistor parasitic capacitance. The capacitor, the Ciss of the MOS transistor, and the inductance of input leads provide a device input resonant frequency between the input signal fundamental frequency and the first harmonic.

Abstract: A semiconductor integrated circuit includes a differential transistor circuit having first and second FETs which each include a drain, a source and a gate and whose sources are connected to each other.

Abstract: Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor.

Abstract: Disclosed is a switched capacitor filter block having a nonlinear quality coefficient, Q, whereby quality can be enhanced while limiting the size of feedback resistors in the filter block. A pair of capacitors alternately switchably connect an input signal to the input of integrator whereby the sampling frequency is twice the switching frequency. The filter block is readily fabricated in a monolithic integrated circuit with the feedback resistors being thin-film resistors formed on the surface of the monolithic integrated circuit. Such a circuit configuration is more accurate in programming and requires only one mask step in fabrication to program.

Abstract: In a controllable amplifier circuit with an amplifier transistor a further transistor is provided that, when actuated under control conditions, deprives the amplifier transistor of at least a part of the input signal.

Abstract: A power amplifier circuit utilizes vertical power transistors, such as static induction transistors, field effect transistors, or bipolar junction transistors, in a configuration where an ungrounded terminal serves as a common node while a separate reference terminal is connected directly to ground. A transformer of appropriate bandwidth couples an rf input signal to the input terminals of the transistor such that the input terminals are floating relative to ground. The novel amplifier circuit establishes separate electrical paths between the common terminal and the input circuit and between the common terminal and the output circuit. Thus, negative feedback is not present in the common lead, thereby improving gain, power output, and efficiency. Moreover, the circuit, in either a BJT, FET, or SIT configuration, can be fabricated on thinned semiconductor chips to form a transistor package in which the chips are bonded directly to the package heatsink.

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage.

Abstract: A device for minimizing parasitic junction capacitances in an isolated collector vertical PNP transistor, having a terminal N connected to an epitaxial n layer, comprises a bootstrap circuit including an emitter follower vertical PNP transistor having its emitter and base respectively connected to the terminal of the epitaxial n layer and the collector of the isolated collector transistor; further, a bias resistance is connected between the emitter and one pole of a voltage supply to the emitter follower.

Abstract: A technique for reducing phase shift of a signal passing through a large thin film resistor on an insulating layer includes applying a signal to one terminal of the thin film resistor and also to one end of an underlying doped epitaxial region. The opposite terminal of the thin film resistor is connected to a virtual ground or virtual reference voltage produced by an inverting input of an operational amplifier. The corresponding opposite end of the epitaxial layer is connected to ground or other reference voltage. The voltage gradients produced by currents flowing through both the thin film resistor and the epitaxial layer are equal, so that substantially no incremental charging current flows through capacitance between the thin film resistor and the epitaxial layer. Phase shift of the signal flowing through the thin film resistor is thereby avoided.

Abstract: An integrated current-mirror arrangement comprises a first and a second transistor whose bases are interconnected and connected to the collector of the first transistor. The transistors are constructed as vertical transistors each having a collector region (23a, 23b) of the first conductivity type, isolated from the substrate (21) of the first conductivity type by an intermediate layer (22) of the second conductivity type. A connection is provided between said intermediate layer (22) and the interconnected bases (29, 30) of the two transistors which improves the high-frequency transfer function between input and output and effectively eliminates the capacitive path for interference signals from the voltage supply line (+V) to the output.

Abstract: A monolithically integrated audio amplifier which is commutable from a stereo configuration to a bridge configuration and vice versa may have only seven pins, namely: two output pins, two input pins, an supply pin, a ground pin and a SVR pin. It comprises two operational amplifiers which may both have two distinct input differential stages, a first input differential stage being fedback according to a stereo configuration while the other input differential stage being fedback according to a bridge configuration of the two operational amplifiers. A comparator with an internally fixed threshold determines, in function of its output state, the switching on or the switching off of one or the other of said two distinct input differential stages of the two operational amplifiers and, therefore, either a stereo configuration or a bridge configuration of the audio amplifier.

Abstract: An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics.

Abstract: A monolithic integrated wideband power amplifier circuit has a push-pull output stage, a driver stage, a difference stage which receives an input voltage signal and provides a difference signal, and the improvement of an operating point setter which receives the difference signal and controls the operating point of the circuit through a settable resistor. The setting of the operating point is independent of the gain of the output stage, and both are independent of temperature. The bipolar NPN transistors of the push-pull output stage consists of parallel-connected subtransistors which are arranged in the integrated circuit layout according to their characteristics and specific use, so as to minimize parasitic capacitances and resistances and to keep the upper cutoff frequency as high as possible.

Abstract: Circuitry is disclosed for staggering the onset of gain reduction in a series of cascaded gain stages as a function of received signal strength. The staggering is effected by controlling the area ratio between corresponding components in two or more AGC control circuits whose topologies are otherwise identical. The technique is particularly well suited for use in radio receivers fabricated in integrated circuit form.

Abstract: The invention teaches the placement of a plurality of conducting paths in the vicinity of the base of the final stage of a Darlington configured transistor group. When an abrupt change in carrier density occurs, such as during switching intervals, the added conduction paths facilitate the removal of carriers from the base region, thereby facilitating the turn-off process. The extra conductive paths allow a more even current density within the volume of the base during changes in carrier density.

Abstract: A distributed FET amplifier comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal. The gate terminals of the adjacent FET elements are connected by a first inductor, and the drain terminals of the adjacent FET elements are connected by a second inductor. Between the source terminals of each of the FET elements and the ground is connected a parallel circuit comprising a capacitor having a capacitance greater than the gate-source capacitance of the FET element and an impedance element connected in parallel to the capacitor for grounding the direct current. A bias voltage supply circuit for supplying a bias voltage to such as distributed amplifier is also disclosed.

Abstract: A circuit for automatically controlling the gain-bandwidth product of operation amplifiers, where gain-bandwidth product (G*B) of one of the amplifiers placed on the same chip as the amplifiers to be controlled is measured and the resulting signal is used to control through a bias circuit the gain-bandwidth products of all the amplifiers, the value of these products being presettable through the frequency of a control signal sent to the circuit input. The reference amplifier is highly compensated for and placed in the configuration of voltage follower.

Abstract: An integrated circuit in a seven pin package particularly for audio signal amplification comprises at least two integrated amplifiers selectively commutable in a bridge configuration or in a stereo configuration by means of at least three integrated switches driven by an integrated comparator with threshold set by an internally generated reference voltage and whose input is connected to the SVR pin commonly used to implement the function of common mode signals rejections. The internal commutation between the two selectable configurations is obtained by varying the level of the bias voltage applied to said SVR pin by means of an external voltage divider.

Abstract: A semiconductor non-inverting repeater circuit utilizes a pair of current mirrors operating in a balanced source/sink operation during non-input signal periods to provide quiescent biasing current to a pair of complementary bipolar output transistors. The bipolar output transistors are configured in a complementary emitter-follower arrangement to provide minimum delay. Finally, the circuit includes two diodes and two capacitors to supply a non-inverted input signal to the bipolar output transistors such that a non-inverted output signal is produced.

Abstract: An integrated circuit selectively programmable to form an active filter without external circuit components, the integrated circuit having 2.sup.m amplifying modules where m is an integer between 2 and 4, inclusive, p resistive matrices where p is 1 when m is other than 4 and is 2 when m=4, and a bias circuit, r of the amplifying modules being positioned in a first column separated from a second column of r amplifying modules by a respective one of the resistive matrices, where r=4 when m is other than 2 and r=2 when m=2, the second column of amplifying modules being separated from a third column of 4 amplifying modules when m=4 by a second of the resistive matrices.

Abstract: A transistor amplifier has an integral resistance-capacitance negative feedback network in order to stabilize it and allow a broadband impedance match. To minimize transmission line effects and phase shifts, the capacitor is formed using a control electrode pad as one capacitor plate and the control electrode has integral fingers. The resistor can be of the floating gate type for ease of construction. The transistor can be an FET.

Abstract: The invention relates to a low noise amplifier for use at microwave frequencies which may be fabricated using integrated circuit techniques. In accordance with the invention, critical components are made adjustable so as to simplify the design process and manufacturability of the amplifier. A two stage low noise amplifier is disclosed in which TEE networks are used as input and output networks in each stage, and in which one element of each TEE includes an adjustable spiral inductor. The value of each adjustable spiral inductor may be adjusted by removal of one or more air bridges disposed along the inner turn of the inductor. This permits one to "tune" the amplifier and optimize its performance.

Abstract: A simple four-transistor CMOS linear, tunable, high-frequency transconductance element is applied to the design of analog standard cell arrays for semi-custom design of analog circuits. By substituting a pair of composited n-channel/p-channel devices for each transistor in a CMOS inverter circuit, the transconductance circuit achieves its linearity by current differencing without undue matching requirements. The linearity and frequency response is optimized by appropriate choice of device dimensions. The transconductance element is used as an elementary building block which forms the basis of a standard cell library for use in semi-custom analog circuit applications. Various analog circuits are realized by interconnecting a number of the transconductance elements in order to achieve a highly systematic design in chip layout along with high functional density.