Abstract: Systems and apparatus for converting an input current signal into two or more output voltage signals on an integrated circuit. In one aspect, an integrated circuit includes a first trans-impedance amplifier that includes a first cascode amplifier; and a second trans-impedance amplifier that includes a second cascode amplifier, the second cascode amplifier and the first cascode amplifier sharing an input transistive element; where the first cascode amplifier is coupled to one or more first switches that disable the first trans-impedance amplifier, the second cascode amplifier is coupled to one or more second switches that disable the second trans-impedance amplifier, and control logic coupled to the one or more first switches and the one or more second switches disables at least one of the first trans-impedance amplifier or the second trans-impedance amplifier.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: An integrated circuit system comprising: forming a differential amplifier including: forming a first transistor, coupling a second transistor to the first transistor in a high gain configuration, and coupling a third transistor, having a low gain configuration, in parallel with the second transistor; and adjusting a gain of the differential amplifier by adjusting a ratio of the size of the second transistor to the size of the first transistor.

Abstract: An integrated circuit includes a first, diode-connected MOSFET and a second, linearly operated MOSFET serving as resistor. A current source may provide a current such that the second MOSFET shows a transconductance constant over temperature and process variations. In one embodiment the MOSFET devices are included in a variable gain amplifier for adjusting the gain.

Abstract: An electrical component includes an amplifier that includes an output stage, and a power-supply path for powering the output stage. The power supply path includes a line that includes conductor track sections in parallel. The electrical component also includes a carrier substrate containing the amplifier and the line with the conductor tracks.

Abstract: A small, high performance high frequency power amplifier enables easily adjusting and switching the impedance. The high frequency power amplifier module includes a first semiconductor chip including one or a plurality of high frequency amplification devices, and a second semiconductor chip including one or more high frequency matching circuit devices and one or more switching devices. The second semiconductor chip includes the matching circuit for a high frequency amplifier device. The second semiconductor chip also includes a circuit composed of a capacitance and a switching device connected in series or parallel to the capacitance. The switching device switches on or off so that the capacitance is connected or is not connected as a part of the matching circuit.

Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.

Abstract: Active circuits with isolation switches are described. In one design, an apparatus includes first and second amplifiers coupled in parallel. Each amplifier receives an input signal and provides an output signal. Each amplifier has a switch that isolates the amplifier when the amplifier is turned off. The first and second amplifiers may be high and low gain amplifiers or two low noise amplifiers (LNAs). The first and second amplifiers may be for different communication systems, different frequency bands, and/or different gain ranges. In general, any number of amplifiers may be coupled in parallel, and each amplifier may have a switch to isolate that amplifier when turned off. A switch for an amplifier may be a shunt switch coupled between an internal node of the amplifier and ground. The shunt switch may be closed when the amplifier is turned off and may be opened when the amplifier is turned on.

Abstract: A description is provided of a high-frequency, multi-stage, millimeter wave amplifier integrated circuit, and of a method for designing and constructing the circuit. The methods and structures have been created to enable the construction of an amplifier offering substantial gain at a relatively high power and high frequency, but occupying minimal area of an integrated circuit die. Various structures and methodologies are described which each contribute to the practical feasibility of constructing an amplifier with such performance in a relatively compact space.

Abstract: An integrated CMOS power amplifier system to improve amplifier performance, the integrated CMOS power amplifier system including a plurality of differential main amplifier cores, a plurality of ground pads, and a plurality of routes to connect the plurality of differential main amplifier cores to the plurality of ground pads. Each differential main amplifier core includes a pair of collocated main amplifier core transistors. Each ground pad is connected to a subset of the differential main amplifier cores. Embodiments of the integrated CMOS power amplifier system decrease parasitic inductance to ground and increase the transconductance and amplification of the integrated CMOS power amplifier system, thus improving performance.

Abstract: A method for implementing a layout of an integrated circuit containing an OP (operational amplifier) is disclosed. The method includes constructing an output path connecting an output terminal of the OP to an output pad of the OP; and constructing a feedback path connecting an input terminal of the OP to an element of the OP, the element lying in an area covering the output pad, in which a minimum distance between the element and the output pad is less than a tenth of length of the feedback path. The present invention also provides an integrated circuit device produced through the method.

Abstract: A semiconductor integrated circuit includes a capacitor element which defines a prescribed decay time constant with one or more resistors, an MOS transistor connected to the capacitor element via its gate, and a constant current generating element which generates a constant current. The capacitor element is charged with the constant current so as to create a linearly changing voltage. The linearly changing voltage is applied to the gate so that the MOS transistor can accordingly output a smoothly changing current.

Abstract: An apparatus and system are provided to adjust an output voltage of an integrated circuit (IC) die. For instance, the apparatus can include an on-chip source termination and a bias generator. The bias generator can be configured to provide a source current to the on-chip source termination to adjust the output voltage. In particular, when adjusting the output voltage of the IC die, the bias generator can adjust the source current using a first current with a first adjustable current gain and a second current source with a second adjustable current gain.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: The semiconductor integrated circuit includes a constant voltage regulator 3 generating a predetermined constant voltage from an external power supply 16, an inverting charge pump circuit 2 using the output of the constant voltage regulator as its power supply, and an amplifier circuit 4 using the negative voltage outputted by the charge pump circuit as a reference voltage. The output voltage of the constant voltage regulator is set so that a potential difference between the output voltage of the constant voltage regulator and the output voltage of the charge pump circuit is not to exceed a withstand voltage of the amplifier circuit, and power is supplied to the constant voltage regulator and amplifier circuit from a single external power supply. Even if the voltage of the external power supply increases, the negative voltage output of the charge pump circuit does not change, permitting an increase in the maximum value of the external power supply voltage with account taken of the withstand voltage.

Abstract: A millimetric-wave amplifier arrangement comprises a first amplifier whose output is connected to one input of the second amplifier via an adjustable attenuator. Both amplifiers are integrated on a single substrate.

Abstract: A plurality of transistors operate as amplification elements. An input side coupling circuit comprises a plurality of distributed constant lines connected in series, one terminal of which is an input terminal and the other terminal of which is a bias input terminal. Each of the connection nodes between these distributed constant lines is connected to each of the inputs of the transistors. An output side coupling circuit comprises a plurality of distributed constant lines connected in series, one terminal of which is an output terminal and the other terminal of which is a bias input terminal. Each of the connection nodes between these distributed constant lines is connected to each of the outputs of the transistors. A termination circuit is provided at the input side coupling circuit or the output side coupling circuit.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.

Abstract: A method for implementing a layout of an integrated circuit containing an OP (operational amplifier) is disclosed. The method includes constructing an output path connecting an output terminal of the OP to an output pad of the OP; and constructing a feedback path connecting an input terminal of the OP to an element of the OP, the element lying in an area covering the output pad, in which a minimum distance between the element and the output pad is less than a tenth of length of the feedback path. The present invention also provides an integrated circuit device produced through the method.

Abstract: A system for controlling gain in a polar loop is disclosed. Embodiments of the invention provide for a substantially constant gain tolerant of changes in supply voltage, ambient temperature, and/or manufacturing process.

Abstract: A high frequency module comprises a layered substrate. Inside the layered substrate, a reception diplexer for processing reception signals and a transmission diplexer for processing transmission signals are provided. The reception diplexer and the transmission diplexer are located in two different regions inside the layered substrate. A conductor portion that is connected to the ground and that electromagnetically separates the reception diplexer and the transmission diplexer from each other is provided between the two regions inside the layered substrate. The conductor portion is formed by using a plurality of through holes.

Abstract: A semiconductor power device comprises a flange, a die having a gate, a source, and a drain. The source is electrically coupled to the flange. A drain matching circuit is located on the flange having an input, an output and a bias input, the input being coupled with the drain. The drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor. An input terminal is mechanically coupled to the flange and electrically coupled with the gate, an output terminal is mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit, and an input bias terminal is mechanically coupled to the flange and electrically coupled with the drain through the bias input.

Abstract: A solid state power amplifier (SSPA) system may include a radio frequency (RF) input, an RF waveguide split block, multiple monolithic microwave integrated circuit (MMIC) power amplifier modules, and/or a heat spreader. An MMIC power amplifier module may include a backing, a board, at least one MMIC, and/or a cover. A method for dissipating heat within an SSPA may include receiving an RF signal, splitting the RF signal, amplifying multiple RF signals, combining the multiple RF signals, generating heat, and/or dissipating heat.

Abstract: An amplifier circuit includes a first bipolar transistor of which the emitter is connected to the ground, and a bias circuit of the first bipolar transistor. The bias circuit includes a second bipolar transistor constituting a current mirror circuit along with the first bipolar transistor, a first resistor connected to the bases of the first bipolar transistor and the second bipolar transistor, and a third bipolar transistor of which the emitter is connected to the bases of the first bipolar transistor and the second bipolar transistor through the first resistor, and of which the base is connected to the collector of the second bipolar transistor. The first bipolar transistor amplifies a signal input to the base thereof and then outputs the amplified signal from the collector of the first bipolar transistor.

Abstract: A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be implemented on an integrated circuit.

Abstract: A system of compatible modules includes a radio frequency (RF) module with a power amplifier configured to produce an amplified RF signal at an output RF terminal; and a first row of pads and a first column of pads intersecting at a corner pad of the module, and wherein the corner pad is coupled to the output RF terminal.

Abstract: In a power amplifier, a serial bus interface is provided for sending and receiving information to other devices, such as a baseband controller. The power amplifier includes several control pins that can be used as a serial interface, or alternately, with a direct pin control interface. The serial bus interface can be used with digital power control techniques that provide various advantages over conventional power amplifiers.

Abstract: A MMIC amplifier stage and a discrete transistor amplifier stage are housed in a single package. In one aspect, a multi-stage RF amplifier includes a package with an RF input lead and an RF output lead. The signal path from the RF input lead to the RF output lead includes one or more MMIC amplifier stages followed by one or more discrete transistor amplifier stages. Each MMIC amplifier stage includes a MMIC with at least one amplifier, and each discrete transistor amplifier stage includes at least one discrete transistor amplifier. All of the MMIC amplifier stages and discrete transistor amplifier stages are housed in the same package.

Abstract: A variable capacitance circuit includes a MOS capacitor, and an application voltage switching section configured to change an application voltage to the MOS capacitor to change a capacitance of the MOS capacitor. The variable capacitance circuit connects the MOS capacitor to an electronic circuit. Here, the electronic circuit may be a voltage amplification circuit, and the variable capacitance circuit may function as an amplification gain switching circuit configured to switch an amplification gain of the voltage amplification circuit, by changing the capacitance to be connected to the voltage amplification circuit.

Abstract: The present invention is directed to compensate electric properties of an RF power module depending on changes with time, temperature dependency, variations, and the like of grounded emitter current amplification factor of an HBT. A compound semiconductor integrated circuit supplies reference current of a reference HBT depending on hFE of an HBT to an input terminal of a first current mirror of a bias circuit of a silicon semiconductor integrated circuit. The base of an output HBT of the compound semiconductor integrated circuit is biased with bias current which increases in response to decrease in hFE of the HBT from an output of the first current mirror of the silicon semiconductor integrated circuit.

Abstract: Disclosed herein is a differential amplifier using body-source cross coupling. In a common gate differential amplifier in which common gate amplifiers are implemented in a differential structure, since the bodies of the common gate amplifiers are cross coupled to the sources of the opposite common gate amplifiers, it is possible to increase transconductance due to body effect to improve a gain. Since the potential of the body is equal to that of the source in a DC mode, a breakdown voltage reduction problem is alleviated.

Abstract: An integrated power amplifier (PA) module formed on a substrate includes a first cluster of transistor cells positioned in a first portion of the substrate; a second cluster of transistor cells positioned in a second portion of the substrate and spaced apart from the first portion; and a combiner coupled to the first and second clusters to combine the output of the first and second clusters.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: Amplifier circuit for amplifying an input signal, having a vertically integrated cascode that has a collector semiconductor region of a collector, adjacent to the collector semiconductor region, a first base semiconductor region of a first base, a second base semiconductor region of a second base, an intermediate base semiconductor region adjoining both the first base semiconductor region and the second base semiconductor region, and an emitter semiconductor region of an emitter adjacent to the second base semiconductor region, wherein a signal input is connected to the second base, and the first base is electrically coupled both to a voltage source that is independent of the input signal and to the collector.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: A path configuration for a power switch and driver can introduce independent parasitic inductance coupled to the power switch to slow a switching speed of the switch and reduce voltage spikes on the switch during switching events. The path for low side supply of the drive to the negative DC voltage reference is separate from the path of the power switch to the reference. The resulting reduction in voltage spikes due to the slowed switching time maintains performance in an audio amplifier without modifying a switch command signal to compensate for voltage spikes. The path configuration avoids reliance on specifying higher rated components that increase application costs.

Abstract: An inductively degenerated low noise amplifier arrangement is shown having a transistor and a bonding pad connected to the input terminal of the transistor, wherein the bonding pad has parasitic capacitance, and wherein the bonding pad includes a metal layer connected to a second terminal of the transistor. In case of a field-effect transistor the second terminal may be the source and in case of a bipolar transistor the second terminal may be the emitter. The metal layer may be the ground plane of the bonding pad or an additional, intermediate layer.

Abstract: A multi-stage amplifier includes first and second amplification stages and a loading stage, all of which generate flicker noise. A degeneration block is operably disposed between circuit common and the loading stage wherein the degeneration block is operable to reduce flicker noise generated by at least one of the loading stage, the first amplification stage and the second amplification stage. The degeneration block further includes at least one active MOSFET operably biased in a linear region to provide a specified resistive value and coupled to receive and conduct the common mode portion of the intermediate stage output signal based upon a gate terminal bias signal. A degeneration block amplifier is operable to generate a replica device bias signal wherein the replica device is operable to set the gate terminal bias signal for the at least one active MOSFET based upon the replica device bias signal.

Abstract: A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g.

Abstract: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

Abstract: A circuit for improving amplification and noise characteristics of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and a frequency mixer, an amplifier and an oscillator using the circuit are provided. A gate terminal of the MOSFET is connected to a body terminal of the MOSFET through a capacitor and the gate and body terminals of the MOSFET are connected to a current source to simultaneously provide a signal to both the gate terminal and the body terminal, in order to improve amplification and noise characteristics of the MOSFET. As a result, a higher level of amplification and a lower level of noise than the conventional art can be obtained.

Abstract: A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

Abstract: Microwave coupling network comprising a passive resistive pi net and a coupling capacitor is coupled to a branching point. The branching point is coupling to respectively a plurality of common drain FET amplifier stages or respectively to common collector BJT amplifier stages, wherein respectively the source, or respectively the emitter, is coupled to at least one output port.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: In a BTL amplifier of the present invention, between first and third transistor parts which are laterally adjacent, directions of semiconductor regions are parallel. Between the first and second transistor parts and the third and fourth transistor parts, each which are longitudinally adjacent, directions of semiconductor regions are perpendicular. The first and the third transistor parts are connected to a power supply terminal through a first wire. The second and the fourth transistor parts are connected to a ground terminal through a second wire. The first and the second transistor parts are connected to a first output terminal through a third wire. The third and the fourth transistor parts are connected to a second output terminal through a fourth wire.

Abstract: A system for reducing the calibration time of a Power Amplifier (PA) (202) is provided. The system includes a memory module (304) that is integrated in the PA. The memory module is configured to store one or more calibration parameters of the PA.

Abstract: In differential amplifier circuitry formed on a semiconductor substrate, first and second transistors constitute a differential pair of the differential amplifier circuitry. First and second pads are connected with emitters of the first and second transistors, respectively. The first and second pads are connected with first and second external ground terminals via first and second rewiring layers to be grounded, respectively. The first and second rewiring layers are preferably connected with each other. Further, bases of the first and second transistors are connected with first and second bias circuits via first and second resistors, respectively.

Abstract: Satellite set-top boxes (STB) are increasingly being designed with multiple tuners, making them capable of receiving more than one program at a time. In addition, satellite STBs are increasingly being designed with multiple inputs, to permit reception of additional channels that will not fit within the conventional satellite intermediate frequency (IF) band (950-2150 MHz). Often, the STB must route these multiple inputs to the multiple tuners with some form of switching function, to allow each tuner to receive all channel bands. Accordingly, the invention includes an RFIC with two RF inputs and three RF outputs, and a crossbar switch that can route any input to any output. The two inputs are amplified by low-noise amplifier stages.