Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register.

Abstract: An apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.

Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one dock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.

Abstract: To demodulate a quadrature input signal (Si) (for example, frequency shift) a demodulation unit (DEM) is used, comprising a PLL (P) having a complex mixer (M) and a controlled oscillator (V). Normally, a limiter has to be used to keep the loop gain independent of the amplitude of the quadrature input signal. In the PLL, a divider (DEL) is coupled between the mixer (M) and the oscillator (V) to divide the two mixed components (Sm1, Sm2) of the quadrature signal supplied by the mixer.

Abstract: A phase shift keyed carrier recovery and demodulator circuit which includes a phase detector and subsequent feedback control loop circuitry which maintains an initial phase relationship. By comparing an incoming phase modulated carrier with the multiple phase outputs of a local oscillator, the circuit is able to generate a correcting signal which allows coherent phase tracking of the incoming phase modulated carrier. The phase detector produces a correction signal which allows the circuit to phase lock any two sequential phases of the locally generated phase outputs to phase positions on either side of the phase of the incoming phase modulated carrier. Once the circuit has obtained carrier phase lock, the multiple phases produced by the local oscillator will remain fixed (without phase change) relative to the initial detected phase of the incoming phase modulated carrier.

Abstract: The synthesis of high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register.

Abstract: A master and slave arrangement of processors includes a clock signal synchronization apparatus. The clock signals of two (processor) assemblies in micro-synchronous operation are only allowed to exhibit an extremely slight phase difference. A system clock signal is generated by a voltage controlled oscillator, which is fed by phase detectors with a filter at the output of each phase detector. Switches are provided between the filter output and the voltage controlled oscillator input. The phase detectors compare the system clock signal and a reference clock signal. A delay is provided at the input of one phase detector.

Abstract: A phase locked loop (PLL) circuit with time-delayed phase/frequency detector (PFD) input signals and a method for generating high PFD gain in such a circuit is provided. One circuit embodiment includes a first divider, a phase/frequency detector having a plurality of input pairs, a plurality of input signal reference delay elements connected in a series between the first divider and the PFD, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a second divider, and a plurality of feedback signal delay elements connected in a series. The corresponding method embodiment includes steps for receiving digital input signals with reference frequency and period T in the first divider, dividing the reference frequency by a value R, providing a plurality of time-delayed PFD reference input signals in each period T, dividing the VCO frequency by a value M in the second divider, and providing a plurality of time-delayed PFD feedback input signals in each period T.

Abstract: The present invention relates to methods and devices for such control and supervision of an oscillator signal from a controllable oscillator that is done mainly to control the frequency variation of the oscillator signal. According to the invention, the controllable oscillator is controlled by a controlling voltage, which in turn is modified by a correction signal, generated in a control loop. A time discrete representation of a secondary phase is generated in the control loop, the secondary phase corresponding to a frequency being the difference between the frequency of the oscillator signal and a constant frequency. A time discrete approximation signal is generated in dependence of the time discrete representation of the secondary phase. A time discrete error signal is generated in dependence of the time discrete approximation signal, the time discrete error signal indicating the difference between the actual frequency slope of the oscillator signal and a desired frequency slope.

Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.

Abstract: A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.

Abstract: A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.

Abstract: A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output.

Abstract: For a possible simple structure, dispensing with ceramic filters, an FM demodulator for demodulating sound-FM signals comprises a controllable amplifier (1) which receives the sound signals converted to intermediate frequencies, said amplifier having a gain which is adjusted by means of an amplitude control circuit (4) and whose output signal is applied to the amplitude control circuit and to the phase-locked loop which supplies a demodulated sound signal in the locked-in state from its output, said phase-locked loop including a loop filter (7) which comprises a filter (8, 9, 10) of at least the second order with a pole at the frequency f=0, and a limit-detection circuit (13) which feeds back the operating frequency of the phase-locked loop to a predetermined frequency range when said phase-locked loop leaves this frequency range around a predeterminable nominal demodulation frequency, the amplitude control circuit (4) controlling the controllable amplifier (1) in dependence upon its output signal and a signa

Abstract: By using the two square-law circuits for squaring the common mode and orthogonal components of the carrier wave and by using the multiplying circuit for multiplying these squared signals, the Costas loop carrier recovery circuit can be constituted. The carrier recovery circuit is constituted such that a phase synchronous circuit constituted by a PLL is controlled by a signal obtained by removing a sign component from an input carrier wave.

Abstract: An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized.

Abstract: A carrier reproducing circuit for detecting a phase error when an inputted baseband signal is out of phase and bringing the baseband signal into phase even in QAM systems in which normal signal points are located in a non-square pattern in a phase-amplitude signal space. When the baseband signal is out of phase, a first region decision circuit detects a presence of the baseband signal in a first region and outputs a first signal, and a second region decision circuit detects a presence of the baseband signal in a second region and outputs a second signal. If the second signal is not outputted over a predetermined period of time around the time at which the first signal is outputted, then a selective outputting circuit outputs a phase error detected by a phase error decision circuit with respect to the baseband signal at the time the first signal is outputted, to a control signal generator.

Abstract: The invention relates to a transceiver for generating complex I/Q-signals on a transmission frequency (f.sub.TX) and for receiving them on a reception frequency (f.sub.RX). The device comprises a first frequency synthesizer (41) for forming a first mixer signal (f.sub.LI) for the mixer (42) of the first branch that mixes the I-component of the received signal into a lower-frequency I-signal, and a second frequency synthesizer (411, 49, 46) for forming a second mixer signal (f.sub.LQ) for the mixer (421) of the second branch that mixes the Q-component of the received signal into a lower-frequency Q-signal. The device further comprises control means (45) first for directing the phase of the first (f.sub.LI) and the second (f.sub.LQ) mixer signals into the same phase in the mixing effects thereof and, thereafter, into a 90 degree mutual phase shift in the mixing effects thereof when receiving signals for bringing the lower-frequency I- and Q-signals into a 90 degree mutual phase shift.

Abstract: A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.

Abstract: In a method and a device for correcting a frequency offset between a receive signal and a reference signal, the receive signal, being fed to a frequency converter which also receives a conversion signal in order to produce a transposed signal, the conversion signal is produced by a local oscillator in response to a control signal. The device initializes the control signal according to the reference signal. An estimator receives the transposed signal and the control signal and produces repetitively an estimate of the frequency offset comprising the sum of a correction value and an adjustment value respectively greater than and less than a predetermined correction threshold. The control signal is modified in response to the correction value. The transposed signal is connected using at least one of the successive estimates.

Abstract: In a variable frequency divider capable of N+1/2 frequency division, a programmable frequency divider alternately frequency-divides an input signal by a frequency division ratio N (N being an integer) or by a frequency division ratio N+1. A first signal generating circuit generates a first signal in synchronism with an output signal of the programmable frequency division circuit. A second signal generating circuit generates a second signal which is identical to the first signal but delayed by half a period of the input signal. An output circuit alternately selects the first and second signals, and outputs the selected signal as frequency-divided signal. A delay circuit outputs a delayed signal identical to the first signal but delayed by one period of the input signal. A preset signal generating circuit alternately selects the delayed signal and the first signal, and presets the programmable frequency division circuit with the selected signal.

Abstract: A phase locked loop including an in-phase detector (IPD), a quadrature phase detector (QPD), a frequency detector (FD), a squelch, a filter, and a voltage controlled oscillator (VCO). The in-phase detector has an IPD sample input, an IPD input, and an IPD output, where the IPD sample input is coupled to a data input. The quadrature phase detector has a QPD sample input, a QPD input, and a QPD output, where the QPD sample input is coupled to the data input. The frequency detector has a first FD input coupled to the IPD output, a second FD input coupled to the QPD output, and a FD output. The squelch has a squelch input, an enable input, and a squelch output where the squelch input is coupled to the IPD output and the squelch enable is coupled to the FD output. The filter has a filter input coupled to the squelch output and a filter output. The voltage controlled oscillator has a VCO input coupled to the filter output, a VCO in-phase output, and a VCO quadrature output.

Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock circuit also determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming, or alternatively, of the outgoing signal, as determined in order to supply an output signal of predetermined polarity.

Abstract: A carrier regeneration circuit achieves quick frequency synchronization without using a sweeper. An area judging device judges whether a baseband signal, quadrature-demodulated with a regenerated carrier output from a voltage-controlled oscillator, lies inside a designated area in a phase plane. If it is inside the designated area, an output of a phase comparator is selected, and if it has exited the area, the previous value is held. The designated area is set so that the direction of control indicated by the phase comparator, just before the baseband signal rotating in the phase plane exits the area, coincides with a direction that suppresses the rotation.

Abstract: PLL apparatus for generating an oscillatory signal phase locked to a component of a further signal comprises a variable oscillator for generating the oscillatory signal and a source of the further signal. A phase detector responsive to the oscillatory signal and to the component of the further signal, provides a phase error signal which is coupled to the variable oscillator via a limiter. Circuit means are provided for controlling the limiting level of the limiter. The dual limiting substantially improves the loop noise tolerance and reduces the loop sensitivity to occasional phase reversals of the component of the further signal. Additional enhancements to loop stability and noise immunity are provided by an unlock detector which detects and totalizes phase rotations in a selected area of a phase plane and by a phase wrap detector which maintains a lock indication during phase angle wrapping.

Abstract: Based on a phase lock loop structure, having a reference signal generator (1), a first phase detector (2), a low pass filter (3), a VCO (4) and a frequency divider (5), in order to achieve a faster channel switching an maintain the design of the filters to be as simple as possible, a second phase detector (6) is provided that receives the reference signal (9) and a second output signal (11) coming from the frequency divider (5) and shifted 90.degree. with respect to its other output signal (10), and that generates a second phase error signal (13), in quadrature with the first phase error signal (12), that is filtered by a second low pass filter (7) thereby generating a second filtered phase error signal (15). The two filtered phase error signals (14,15) are provided to a quadratic correlator (8) whose output is provided to the VCO (4). Its amplitude is proportional to the difference of frequencies between the reference signal (9) and any of the output signals (10,11) from the frequency divider (5).

Abstract: Accurate phase switching of similar pulse trains having different phase position, in which a respectively selected pulse train determines a pulse train to be distributed by means of a phase locked loop, is achieved. Each pulse train is individually delayed so the phase position is roughly adjusted to zero with respect to the pulse train to be distributed. Each non-selected pulse train is continuously compared with the pulse train to be distributed. A phase error voltage is determined that corresponds to a phase difference still present as it would become effective as a control voltage in the phase locked loop. An oppositely equal correcting voltage is added to the phase error voltage to produce a sum, and the sum is made available as an output voltage. Switching to another pulse train is effected by maintaining the relevant correcting voltage at a momentary value and switching the associated output voltage into the phase locked loop as a control voltage in place of a previously used output voltage.

Abstract: A frequency synthesizer has the configuration of a phase locked loop (PLL) having a voltage controlled oscillator (VCO) generating an output signal, a phase detector for outputting a control signal to the VCO, and circuitry coupled to an output port the VCO for offsetting the frequency of a sample of the output signal. The synthesizer includes a sampling mixer operative with a source of reference signal and interconnecting the offset circuitry with the phase detector. The sampling mixer mixes the offset sample with the reference signal to output a comb frequency spectrum of signals differing in frequency from each other by multiples of the reference frequency. A filter selects a signal outputted by the sampling mixer at one of the comb frequencies for application to the phase detector. The phase detector is operative with a source of input signal having an input signal frequency for phase locking with the signal selected by the filter.

Abstract: A system and method for a computer based system for enabling data phase clock corrections. Basing these corrections primarily on errors that cause consistent phase shift errors while reducing the effect of random data phase errors. An improved phase-locked loop (PLL) is used where multiple data bits are examined simultaneously, allowing us to examine "apparent future" and "apparent late" data. The average phase adjustment to the data window is calculated based upon the examined data bits.

Abstract: A system for processing inphase and quadrature data channels, such as a Costas loop QPSK demodulator, employs an additional feedback loop for adjustment of phase offset between carrier reference signals, this loop being in addition to the Costas error loop for control of frequency and phase of an oscillator which provides the regenerated carrier signal. The additional loop employs cross-channel products of demodulated inphase and quadrature data signals as does the Costas loop. The regenerated carrier is applied via an adjustable phase-offset unit to provide quadrature carrier reference signals to phase detectors of inphase and quadrature data channels. The phase offset unit includes a 90 degree hybrid circuit energized by the carrier signal at a main input port plus an adjustable fraction of the carrier power applied to an auxiliary input port.

Abstract: In a phase locked loop frequency synthesizer having multiple feedback loops, a reference phase signal is developed into two signals having a frequency twice as high as the reference frequency and the phase difference of the two signals is a half wavelength. The output frequency produced by a voltage-controlled oscillator is divided by two frequency dividers in accordance with predetermined frequency division factors. Each of the frequency-divided signals and each of the developed signals are subjected to phase comparison in pairs. A voltage signal corresponding to the phase differences is fed through a low-pass filter and supplied to the voltage-controlled oscillator.

Abstract: A method and apparatus for producing a frequency-controlled loop in a phase-diversity receiver for demodulating received ON-OFF-keyed (OOK) and phase shift keying (PSK) signals, by feeding a reference frequency signal and the received signals to a quadrature mixer (QM) which produces two output signals in phase quadrature at nominally zero intermediate frequency. Quadrature continuous wave signals void of the modulation are produced from the phase quadrature output signals. A voltage proportional to the frequency of the quadrature continuous wave signals is generated and is utilized for controlling the frequency of the generated reference frequency signal.

Abstract: The present invention concerns a method and a system for demodulating mutually interfering signals according to a suitable synchronism bond between said signals. With such a system a complete decoupling of the demodulators of said signals is obtained. The system is characterized in that on each polarization there is at least a pair of demodulators, a first pair operate a baseband conversion of both signal H and V using the carrier recovery circuit driven by data of one of the two signals (e.g. V) and a second pair operate still a baseband conversion of both signals H and V but using said carrier recovery circuit now driven by data of the other signal (e.g. H).

Abstract: A phase-locked loop incorporates a quadrature modulator for generating constant envelope phase or frequency modulation. Locating the quadrature modulator within the feedback loop or feeding the output signal of the quadrature modulator into the feedback loop permits accurate constant envelope phase modulation of the loop reference oscillator and completely suppresses undesired AM and PM components of the modulated signal.

Abstract: A circuit for producing an output signal representative of the phase angle of a single phase input signal includes a phase shift generator for receiving a single phase input signal and for generating a quadrature signal and a direct signal in response to the single phase input signal, and a phase locked loop coupled to the phase shift generator for generating an output signal in response to the quadrature and direct signals such that the output signal is phase locked with the single phase input signal. A method is also provided for producing an output signal representative of the phase angle of a single phase input signal, comprising the steps of: receiving a single phase input signal; generating a quadrature signal and a direct signal in response to the single phase input signal; and generating an output signal in response to the direct and quadrature signals, such that the output signal is phase locked with the single phase input signal.

Abstract: The invention relates to a circuit arrangement for frequency synthesis with a phase control circuit (1) which comprises a first phase discriminator (3) for receiving a reference signal and an output signal supplied by a first frequency divider (6) with a division ratio k, a low-pass filter (4) coupled to the output of the first phase discriminator (3), and an oscillator (5) coupled to the output of the low-pass filter (4) for generating an output signal which can be supplied to the first frequency divider (6). At least one further branch (2) with a further phase discriminator (8) and a further frequency divider (9) which is to be released and which has a division ratio k is present. The further phase discriminator (8) coupled to the input of the low-pass filter (4) is designed for receiving the reference signal delayed by a delay element (10) and the output signal of the further frequency divider (9) provided for receiving the output signal of the oscillator (5).

Abstract: A phase/frequency-locked loop (P/FLL) circuit for generating output signals synchronized with input signals in frequency and phase. The circuit includes a phase comparator which responds to the input signals and to the output signals to develop therefrom phase comparison signals in the form of positive or negative voltages corresponding to the phase differences between the input and output signals. A filtering circuit produces from the phase comparison signals a control signal for a voltage controlled oscillator (VCO) which produces in turn an oscillation signal having a frequency corresponding to the control signal. A phase controller responds to the control signal for the VCO as well as to the output oscillation signal thereof and produces the output signals in a form and wave shape which cause the control signal for the VCO to have a single voltage polarity. The P/FLL circuit of the invention reduces the time required to pull-in the frequency of the VCO and also expands the pull-in range.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: A circuit for the regeneration of the clock signal within a message containing a preamble and random data. No assumption as to the message structure is required for the operation of such a circuit. The circuit operates on an autocorrelation principle which allows a voltage controlled oscillator (VCO) which is used to reconstruct the clock signal to operate free of the data format. The device is essentially formed as a phase correlator connected to a feedback loop which contains in series a filter, an amplifier and a voltage controlled oscillator. The correlator is formed by a delay line feeding a delayed data signal to two multipliers. The data is also fed to a shift register, the output of which is also fed to the multipliers. The multiplier outputs are fed to a differentiating element which outputs an error signal which acts as a clock correction signal feeding the VCO which, when necessary, adjusts the VCO output so as to match the clocking within the circuit with the clock timing of the message received.

Abstract: A Costas loop carrier recovery device with particular application to communications with spacecraft includes a voltage-controlled oscillator. Two filters having different characteristics are connected to the oscillator by a loop filter via two circuits:a direct connection, anda parallel circuit including an amplifier in series with a filter.

Abstract: A receiver for tracking a carrier suppressed phase-shifted input signal comprises a phase-locked loop circuit for receiving the input signal and having a variable frequency oscillator responsive to a control signal for oscillating at a frequency corresponding to an intermediate frequency and a frequency difference detector for producing an output signal indicative of the frequency difference between the frequency of the input signal and the intermediate frequency, a feedback loop network having a narrow-band path and a wide-band path and being responsive to the detector output signal for producing the control signal and applying the control signal to the oscillator through one of the paths whereby to change the intermediate frequency of the oscillator in response to the control signal, a quality detector responsive to the detector output signal for producing a signal corresponding to the bit error rate of the input signal; and selection means responsive to the bit error rate signal for causing the control sig

Abstract: A regenerating device for regenerating a signal from a composite input signal, provided with a phase-locked loop comprising a first phase comparison circuit 1, a first low-pass filter 2 connected to the output thereof and a controlled oscillator 3. The control input of said oscillator 3 is connected to the output of the low-pass filter 2 while its quadrature output 3a is connected to one input of the phase comparison circuit 1. The input of the phase comparison circuit 1 forms the input of the regenerating device and the in-phase output of the oscillator 3 the output. Furthermore a second phase comparison circuit 4 and a second low-pass filter 5 connected thereto are provided, which correspond to the first phase comparison circuit and the first low-pass filter respectively. The input of the phase-locked loop and the in-phase output 3b of the controlled oscillator 3 are connected to the inputs of the phase comparison circuit 4.

Abstract: Broadband, single and multiphase phase lock loop circuits utilize a sliding window averager to remove the second harmonic and other ac components from a phase error signal which is the product of a sinusoidal or square wave source signal and a corresponding reference signal synthesized from a variable frequency signal produced by a voltage controlled oscillator as a function of the integratal of the phase error signal. The sliding window averager maintains a running average of a number of most recent samples of the phase error signal taken over a selected interval which is preferably one-half cycle of the source signal. Also preferably, the sliding window averager is clocked by the variable frequency signal generated by the voltage controlled oscillator.

Abstract: A clock recovery device suitable for implementation in a DSP functions to correct a signal that includes the clock information for carrier frequency offsets, prior to extraction of the clock signal.

Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: There is provided a method of and apparatus for Automatic Frequency Control (AFC) of pure sine waves (PSW). It comprises discriminating to detect frequency differences between a received pure sine wave and a reference frequency, integrating the frequency differences to average the differences, and adjusting the reference frequency to eliminate the frequency difference. It is further characterized by digitizing, in quadrature, the received pure sine wave, mixing the received pure sine wave with a complex sinusoid to translate the pure sine wave to baseband, quadrature filtering the mixed sine wave, cross-product discriminating to detect frequency differences between a received pure sine wave and a reference frequency, integrating the frequency differences to average the differences, selectively calculating the mean variance between the pure sine wave and the reference frequency, and adjusting the reference frequency of a Voltage Controlled Oscillator to eliminate the frequency difference.

Abstract: A PLL circuit having a function of a frequency multiplier comprises a phase detector circuit receiving an input signal, for producing an error signal which includes an alternating current component having a relatively high frequency depending on the frequency of a frequency-multiplied signal, a low pass loop filter, a voltage controlled oscillator, and a comparison signal generating circuit for generating N phase comparison signals. The phase detector circuit comprises a phase splitting circuit for generating from the input signal N phase split signals having respectively different N phases and N phase detectors for comparing the phases of the N phase split signals with different phases of the N phase comparison signal respectively.

Abstract: A frequency control apparatus and method is disclosed in which a frequency offset between a received signal and the local oscillator of a digital receiver is corrected in substantially one step.

Abstract: A FM detection system using a phase locked loop (PPL 20) and including: a wave shaping comparator (7) for accepting a signal V.sub.CO2 from a voltage controlled oscillator (4) which is 90.degree. out of phase with a control signal V.sub.CO1 from the voltage controlled oscillator (4), the comparator reshaping the signal to a square wave; an in-lock detector (8) for accepting the square wave and a frequency modulated input signal (VFM) to provide a sum frequency and a difference frequency; a low-pass filter (9) cutting off the sum frequency component, and filtering out the difference frequency signal when the PLL (20) is unlocked; a comparator (10) for comparing the output of the low-pass filter (9) with a reference voltage (V.sub.

Abstract: A voltage controlled oscillator of a phase lock loop responds to a phase error signal having a value commensurate with the phase difference between input and output signals of the loop, wherein the phase difference extends over more than a one cycle difference of the loop input and output signals. The phase error signal is derived by mixing the loop input and output signals to derive a pair of signals having amplitudes representing orthogonal components of the difference frequency of the loop input and output signals. In response to the signals representing the orthogonal components, signals are derived indicative of the whole number cycle difference of the input and output signals, fractional cycle difference of the input and output signals, and a combination of the amplitudes of the signals representing the whole number cycle difference and the fractional cycle difference of the input and output signals.