Abstract: A synchronized carrier recovery circuit for a PSK modulated signal includes a plurality of phase detectors supplied with the PSK input signal and phase shifted outputs from a voltage controlled oscillator. The detector outputs are rectified and alternately coupled to a pair of adders whose outputs feed a complimentary subtractor. The detector outputs are also converted to digital form and fed to an Exclusive OR circuit, whose output couples the appropriate subtractor outputs to the VCO to achieve phase locked synchronization.

Abstract: A signal detection circuit for determining synchronism and asynchronism in a phase synchronization circuit having a loop consisting of a first phase detector, a loop filter and a voltage controlled oscillator, has a second phase detector for input signals of the phase synchronization circuit and output signals of the voltage controlled oscillator. The output of the second phase detector is supplied to a low pass filter and a level judgment circuit. The level judgment circuit includes a Schmitt trigger circuit with two threshold levels due to hysteresis effect to reduce misjudgments when the input signals are low signal to noise signals.