Abstract: A carrier recovery circuit comprises a voltage-controlled oscillator with a .pi./2 phase shifter coupled to it for generating carriers of quadrature phase relationship. First and second phase comparators respectively detect phase differences between an offset QPSK modulated signal and the carriers of the quadrature phase relationship. Signal from the first phase comparator is delayed by a 1/2 symbol duration and applied to one input of a quadri-phase detector having stable phase angles at .pi./4, (3/4).pi., (5/4).pi. and (7/4).pi. radian and signal from the second phase comparator is applied to the other input of the quadri-phase detector. A bit timing recovery field (1010 . . . 1010) of the second channel is detected from the output of the second phase comparator. Signal from the quadri-phase detector is applied to a loop filter and thence to the voltage-controlled oscillator during the time when a bit timing recovery field (BTR) of the second channel is not still detected.

Abstract: A phase acquisition and tracking apparatus in which a phase difference between a reference signal and a signal to be acquired is rotated within a negative feedback loop so that such phase difference disappears is disclosed. In another embodiment, a baseband signal which is influenced by such a phase difference is rotated within a negative feedback loop so that the phase difference disappears. The phase rotated signal serves as an output signal from the phase acquisition and tracking apparatus, and this output signal faithfully and rapidly reproduces the input signal regardless of any particular value of such phase difference. Since a negative feedback loop is used to control the amount of phase rotation, non-linearities and other errors produced by multipliers, summing devices and combining circuits are automatically compensated for through the feedback.

Abstract: The present invention is a demodulator for demodulating an unsymmetrical QPSK signal (1), i.e., one in which the amplitudes of the I and Q channels are different, and the I and Q channels have been modulated by signals having differnt bit rates. Analog versions of the I and Q modulating baseband signals are first extracted from the carrier. Each baseband signal is then subjected to a bit-rate-matched low pass filter (23, 13). The channel having the higher bit rate is subjected to a delay (32) to time-align the two baseband signals. The time-aligned filtered signals are then amplified by amplifiers (22, 12) having unequal gains that are preselected to substantially equalize the amplifier (22, 12) outputs. The amplified time-aligned filtered signals are then subjected to a phase error (E) generating means (15, 25, 16, 26, 34). The phase error (E) is passed through a loop integrator (38) and a VCO (30) and back to the baseband signal extracting means to complete a phase lock loop.

Abstract: A controlled crystal oscillator of a stereo decoder of a television receiver using CMOS technology includes first, second and third differential emplifiers that produce corresponding first, second and third pairs of anti-phase output signals. The first and second differential amplifiers have variable gains that vary in opposing manners in accordance with a frequency control signal. The oscillatory signal of a crystal is coupled to corresponding input terminals of the three differential amplifiers such that the phase of the signal that is developed at the input terminal of the third differential amplifier is phase-shifted by approximately 90.degree. relative to those developed at the input terminals of the other two amplifiers. The three pairs of output signals are combined to form a single-ended oscillatory signal that is coupled back to the crystal to complete a regulative feedback path. The frequency of oscillation is determined in accordance with the frequency control signal.

Abstract: An FPLL circuit has a first low pass filter and a limiter having a delay that is less than one half the duration of a data bit for developing binary PSK data and a pair of multipliers, a first of which is operated in phase with and the other of which is operated in phase quadrature with an incoming RF signal. The second multiplier is connected to a third multiplier, which is also supplied with the limiter output for stabilizing the loop in the presence of data. The output of the third multiplier is supplied to a low pass filter that has a delay that is greater than the duration of a data bit and this output supplies an oscillator that develops the 90.degree. phase displaced signals for the first two multipliers.

Abstract: Decoder for a frequency keyed signal, particularly an FSK videotext signal. To avoid isochronous distortions, precise matching of the decoder is necessary. Due to the provision of a additional AFC circuit (11) to regulate the natural frequency of the VCO (5) in the PLL loop (3-5) of the decoder, such matching is no longer required.

Abstract: Circuitry is disclosed for processing Doppler-shifted radar signals or ot noisy signals which fluctuate widely in frequency. The circuitry includes a dual channel discriminator including a voltage controlled oscillator as part of a feedback loop for frequency tracking of said signals. The discriminator further includes a frequency pass circuit in one channel thereof and a frequency stop circuit in the other channel thereof, with the outputs of these circuits applied to a multiplier. The multiplier output controls the frequency of the voltage controlled oscillator. The voltage controlled oscillator output is heterodyned with the input signals to obtain the heterodyned signals for application to the aforementioned two channels of the discriminator.

Abstract: A coherent oscillator circuit which samples a signal responsive to phase and frequency of a transmitted pulse of radio frequency energy in an acquisition mode, and regenerates a signal corresponding to the sampled phase and frequency in a save mode is disclosed. A storage element performs the sampling in a relative fast, open loop manner during the acquiring mode. Then, during the save mode a phase locked loop forms which locks when a loop oscillator outputs a signal which corresponds to the sampled signal. The coherent oscillator forms a portion of a demodulator for a coherent-on-receive radar.

Abstract: The acquisition of phase lock to a reference frequency by a signal acquisition system is accomplished using a voltage controlled oscillator, a wideband frequency discriminator, a prepositioning circuit, and a phase lock loop. The voltage controlled oscillator is prepositioned within a loop bandwidth of the reference frequency by the prepositioning circuit and the wide band frequency discriminator which provide coarse tuning. The voltage controlled oscillator achieves phase lock with the reference frequency when it receives the fine tune signal from the phase lock loop. Using both the discriminator and the phase lock loop allows fast acquisition without the need to calibrate the voltage controlled oscillator. Since the discriminator pull-in range is much larger than the phase-lock loop bandwidth, the number of bits can be much smaller than in an acquisition circuit using a digital prepositioning circuit alone.

Abstract: The outputs of respective phase detectors in an orthogonal phase detector circuit are subjected to A/D conversion, and selected bits from each A/D converter are logically combined not only to recover the reference carrier but also to detect any non-orthogonality of the carriers provided to the phase detectors. The phase shifter for providing the orthogonal reference carrier to the second phase detector is a variable phase shifter controlled in accordance with a control signal, with the control signal being adjusted in accordance with the detected non-orthogonality condition.

Abstract: A carrier recovery loop for a burst type QPSK system. A QPSK signal source of frequency f.sub.1 has its output frequency doubled and then doubled again to produce a signal of 4f.sub.1 with the QPSK modulation thereby removed. Also provided are first and second phase locked loops comprising a common voltage controlled oscillator (VCO), and separate ones of first and second phase detectors, respectively, with each detector having a characteristic output which varies sinusoidally with linear variation of the phase difference of the two signals supplied thereto and with the negative-going cross-over transitions of the characteristic output constituting unstable nulls. A third x2 frequency multiplier connects the output of the VCO to the first phase detector, and a fourth x2 frequency multiplier connects the output of the third x2 frequency multiplier to the second phase detector.

Abstract: A frequency synthesizer for controlling the frequency f.sub.0 of a signal e.sub.0 in response to a control signal e.sub.c2 to produce a band of selectable frequencies separated by .DELTA.f between the frequencies f.sub.x and f.sub.y, where (f.sub.x +R.DELTA.f)=f.sub.0 and R is zero or any integer .ltoreq.(f.sub.y -f.sub.x)/.DELTA.f. The invention includes a first generator for generating the signal e.sub.0, a second generator for generating a signal e.sub.1 having a band of selectable frequencies separated by .delta.f, where .delta.f>>.DELTA.f, a frequency subtractor for subtracting f.sub.1 from f.sub.0 to produce a signal e.sub.2 of frequency f.sub.2. Also provided is a third generator for generating a variable preliminary reference signal of frequency f.sub.pr consisting of a band of selectable frequencies separated by M.DELTA.f and lying within the frequency band Mf.sub.x to Mf.sub.y, where (Mf.sub.x +R.multidot.M.DELTA.f)=Mf.sub.r2 ; a divider for dividing Mf.sub.

Abstract: A carrier recovery circuit for use in a demodulator for a 2.sup.n -phase PSK modulated signal which comprises a phase-locked loop including a voltage-controlled oscillator (7) and an automatic frequency control (AFC) loop for avoiding the false lock phenomenon. The AFC loop is comprised of two differentiating circuits (21, 25), two mixer circuits (22, 26), and a difference circuit (27), and forms a symmetrical structure so as to exclude undesired noise, thereby carrying out a stable AFC operation.

Abstract: A phase detector for a phase lock loop can detect more than a 2.pi. radian phase difference. The phase detector is modulized so that modules may be stacked to extend the phase detection range by 2N.pi. radians, where N equals the number of modules that are stacked together. The modules are combined to obtain an output signal which can be applied to a filter for controlling the voltage of the voltage-controlled oscillator.

Abstract: A phase locked loop is disclosed which subtracts an estimated signal from an input signal and operates upon the residual signal. The residual signal is demodulated and applied to a controlled oscillator which produces feedback signals approximately the sine and cosine of the input signal. The cosine feedback signal is multiplied by the residual signal whose resultant signal is a frequency correction signal. The sine feedback signal is multiplied by the residual signal for multiplication again by the sine feedback signal to produce the estimated signal which is amplitude and frequency controlled. This signal is then subtracted from the input signal to reduce the residual signal to near zero.

Abstract: In an FSK demodulator, the output of the phase detector of a phase locked loop (PLL) is capacitively coupled to one input of an FSK voltage comparator, the capacitive coupling blocking d.c. and d.c. being restored at the comparator input by diodes connected between the two comparator inputs. The other input of the comparator is supplied with a reference voltage corresponding to a nominal center frequency of the FSK signals. A buffer amplifier permits rapid charging of the coupling capacitor, which is set to a determined state when there is no phase lock of the PLL. The arrangement facilitates demodulation of narrow-band FSK signals whose center frequency is subject to change.

Abstract: In order to reduce signal loss particularly when transmitting data in a quasi-synchronous area coverage scheme utilizing sideband diversity, it is necessary to effect coherent demodulation by locking the local oscillator signal to the received carrier signal, even when the carrier has been completely suppressed. The demodulator includes first and second mixers (48, 50) having first inputs to which a frequency converted input signal having sideband diversity is applied. Second inputs of the first and second mixers (48, 50) receive a local oscillator signal. Phase shifting is applied to the input or local oscillator signal so that the outputs of the first and second mixers have a relative phase difference of 90.degree.. The outputs of the first and second mixers are applied to respective audio bandpass filters (56, 58) the outputs of which are mixed in a further mixer (60) to provide a sideband error signal (E.sub.s) which is low-pass filtered in a filter (62). A carrier error signal (E.sub.

Abstract: A phase-locked loop having improved off-frequency detection. A variable frequency output signal is to be precisely locked to the frequency and phase of an alternating input signal. This is accomplished by alternately utilizing two feedback loops. A reference signal, having a frequency approximately equal to the frequency of the input signal is input to an initialization feedback loop in which it is mixed with the output signal. The initialization loop produces a feedback signal for controlling a voltage controlled oscillator which generates the output signal. An off-frequency detector detects the frequency difference between the output signal and the reference signal. When this frequency difference decreases below a predetermined level, the off-frequency detector disables the initialization feedback loop and enables a primary feedback loop.

Abstract: In a control circuit for a voltage-controlled oscillator including the combination of: (a) a source of D.C. power, the voltage out of such source being adjustable in discrete steps to provide a coarse frequency control signal; (b) a control loop, responsive to the signal out of the voltage-controlled oscillator, to provide a fine frequency control signal; and (c) a summer to combine the coarse and fine frequency control signals into a single frequency control signal for the voltage-controlled oscillator, an improvement is shown wherein the control loop comprises an interferometer wherein noise extant on the signal out of the voltage-controlled oscillator is degenerated by dividing a portion of such signal into a reference path, a delayed path and a parallel path, the signals in the latter two paths being processed to produce an amplitude corrected signal for combination with the signal, shifted by 90.degree., in the reference path, finally to produce the fine frequency control signal.

Abstract: A phase-locked loop oscillator circuit having a reference signal generator, a voltage-controlled oscillator and a phase comparator comprises a second phase comparator. The first phase comparator is supplied with an output of the reference signal generator whose frequency has been lowered and also an output of the voltage-controlled oscillator whose frequency has been lowered. The second phase comparator is supplied with a signal which has been derived from an intermediate position of a higher-frequency path extending from the reference signal generator to the first phase comparator and also a higher-frequency signal which has been derived from an intermediate position of a path extending from the voltage-controlled oscillator to the first phase comparator. Outputs of the first and second phase comparators are added and applied to the voltage-controlled oscillator to reduce residual FM noise.

Abstract: The double phase lock loop arrangement of the invention comprises a first feedback loop including a first voltage controlled oscillator (16), a second feedback loop including a second voltage controlled oscillator (20) and first (PSD1), second (PSD2) and third (PSD3) phase sensitive detectors. Each of the detectors have first and second inputs and an output, each first input being coupled to receive a signal which is derived from the first voltage controlled oscillator (16). The second voltage controlled oscillator (20) is connected to the second inputs of the first and second phase sensitive detectors (PSD1, PSD2) and via a phase shifter (21) to the second input of the third phase sensitive detector (PSD3) on whose output a lock signal is produced in response to the signals on its first and second inputs being in a desired phase relationship. The output of the second phase sensitive detector (PSD2) is an A.C.

Abstract: A phase synchronizing circuit, wherein two phase detectors are used in quadrature to detect the phase of an input signal and to avoid hang-up when the phase of the input signal changes abruptly by 180.degree.. The two detected phase signals are then multiplied by a locally generated reference signal and re-combined, so that a synchronized output signal having reduced phase jitter results. This circuit is also incorporated in an N-phase PSK system, where it is used as a synchronizer and not as a demodulator. In a receiver for such a PSK system, the frequency of the received signal is multiplied by N, the phase synchronizer circuit of the invention is then used to extract the carrier (at a N times higher frequency), and a divider is then used to convert the synchronized carrier provided by the synchronizer circuit of the invention down to the original frequency.

Abstract: A carrier oscillation in the microwave range is stabilized by a sequence of timing pulses produced by a crystal-controlled reference oscillator whose cadence is an aliquot fraction of the nominal carrier frequency. The pulses are used to obtain two phase-representing amplitude samples of the carrier wave from a pair of mutually phase-shifted pilot oscillations of the same frequency in each of a succession of nonconsecutive cycles thereof; a control voltage derived from these amplitude samples is fed back to the microwave oscillator via a frequency-correcting or phase-locking loop.

Abstract: A feedback circuit for controlling the phase of a local oscillator provided with frequency adjusting means and delivering a local carrier wave for demodulating a data signal transmitted by single side band amplitude modulation, the said feedback circuit comprising at least one sign multiplier (21) producing the product of the sign of the local demodulation carrier shifted by a phase difference of .pi./4 multiplied by the sign of the data signal to be demodulated, followed by a sign coincidence auto-correlator (22) which controls the said frequency adjusting means and correlates two versions of the signal delivered by the sign multiplier (21), one of the two versions being delayed relative to the other by an odd multiple of one fourth of the period of the carrier used for the amplitude modulation on transmission.

Abstract: A frequency and phase lock loop is disclosed in which AFC and phase locking functions are completely separated thus permitting signal acquisition range and closed loop bandwidth parameters to be independently established. Interference between phase lock loop (PLL) and automatic frequency control (AFC) signals resulting in the loss of a beat frequency signal for matching VCO and reference signal frequencies is eliminated thus affording enhanced PLL frequency pull-in range.

Abstract: A phase locked loop (10) has a phase insensitive frequency comparator (18) including an up/down counter (26) incremented one way by loop frequency pulses (on 28) and incremented the other way by reference frequency pulses (on 30) and which yields error correction signals (on 22 and 24) to adjust loop frequency when the counter overflows or underflows given limits. Timing means (32) is provided at the input (28, 30) to the counter (26) and prevents any clock pulse from being lost by ensuring a sufficient time gap between pulses. A sample and hold phase detector circuit (16) is provided at the data acquisition input to the loop (10) and enables successful acquisition and lock-on even with many zeros between the incoming data bits, and does so with a minimum number of components.

Abstract: The voltage controlled oscillator (VCO) in a phase-locked loop carrier recovery circuit is provided with two control signals, one based upon a phase error between the phase modulated carrier and VCO output and the other based upon a frequency error between the phase modulated carrier and VCO output.

Abstract: A phase shift keyed (PSK) demodulator includes a closed loop wherein a phase error signal is generated to control a voltage controlled oscillator (VCO) to track the carrier frequency of an input signal for demodulation. A frequency discriminator is incorporated with the PSK demodulator to provide a frequency error voltage which is also applied to the VCO to improve the tracking of the carrier frequency by substantially eliminating false locks and removing the dependence of the apparatus on the modulation of the received signal.

Abstract: A low phase noise signal source is disclosed which incorporates a voltage controlled oscillator (VCO) and a feedback network that, in effect, demodulates the VCO output signal and supplies negative feedback representative of the VCO signal noise to the VCO frequency control terminal. The feedback network includes a frequency discriminator of the type wherein a time delay network is connected to one input port of a phase detector, with the VCO output signal being supplied to the time delay network and the second input port of the phase detector. A variable phase shifter, responsive to the signal supplied by the phase detector, is included in one of the phase detector input paths to cause a zero crossover of the frequency discriminator transfer characteristic to occur at the frequency to which the VCO is tuned.

Abstract: A system for comparing the frequency of a voltage controlled oscillator to a stable reference oscillator to generate control signals which maintain the voltage controlled oscillator in phase lock with the reference oscillator. The circuit utilizes a digital frequency comparator to determine whether the output frequency of the voltage controlled oscillator is above or below the reference frequency. When the frequency of the oscillator is either above or below the desired value, pulses are generated which are integrated to produce a DC signal which changes the frequency of the oscillator to achieve the desired value. Additionally, a continuous electrical signal is generated when the output of the voltage controlled oscillator is in phase with the reference signal. When phase lock is achieved the output of the frequency determining circuit goes to zero and phase lock is maintained by the continuous electrical signal.

Abstract: A multiple phase shift keyed data coherent carrier recovery system wherein a coherent carrier tracking loop has attached thereto a signal generator for providing a signal with non-stationary zero-crossing times (e.g. a noise generator), which signal generator chops, or alters the phase of, signals within the loop to prevent the loop from locking on harmonics or subharmonics and to allow AC coupling with DC response therein.

Abstract: A carrier recovery apparatus for phase modulated waves including phase-locked loops is operable to prevent false locks. The apparatus includes a clock recovery circuit which generates a signal in response to a modulated carrier, a first phase comparator responsive to the modulated carrier and the output of a VCO, a second phase comparator responsive to the first phase comparator and the clock signal, and a control device for superimposing the low frequency component of the output of the second phase comparator on the output of the first phase comparator or a loop filter which controls the VCO.

Abstract: A digital servo system for a rotating member which detects a difference between phases of a reference signal and a signal representing the rotation phase of the rotating member thereby to control its rotation in accordance with the phase difference. Comparison is made by a digital rotation phase comparator between points of time at which first and second predetermined counts are made by a clock pulse counter which is cleared for each period of the reference signal and a point of time at which the rotation phase information signal of the rotating member is produced. When the rotation phase signal appears during an interval between the first and second counts, a latch signal is generated in synchronization with the rotation phase signal to cause an instantaneous count between the first and second counts of the counter to be loaded into a latch circuit.

Abstract: A DPSK digital signal receiver is disclosed that has a dual bandwidth offset Costas loop that is switchable from an acquire bandwidth to a narrower tracking bandwidth in response to detection of a start code preceding a message signal included in the digital signal. Detection of the start signal may occur before absolute carrier lock on, which then is completed in the narrow-band tracking mode. Thus, carrier acquisition is achieved much faster than that obtained by prior art circuits requiring absolute carrier lock on before switching bandwidths.

Abstract: A phase lock loop (10) includes a frequency and phase preset network for presetting a local oscillator (20) in substantial synchronism with a carrier signal. The preset network utilizes time delayed output signals from split or double correlators (32, 34, 36, 38) to determine a change in the phase angle between the local oscillator signal and the carrier signal for a known time period to determine the frequency of the local oscillator signal relative to the carrier signal frequency. The preset network determines the phase of the local oscillator signal relative to the carrier signal phase utilizing the summed output of one split correlator (32 and 34) and of another split correlator (36 and 38).

Abstract: Disclosed is a phase-locked loop which comprises a voltage controlled variable frequency oscillator (1), a phase comparator (2) having a cosine characteristic and receiving a reference oscillation as well as that supplied by the oscillator (1), and a low-pass filter (3) connected between the output of the phase comparator (2) and a frequency control input of the oscillator (1).The transfer function of the low-pass filter (3) is switchable between two characteristics depending on the instantaneous phase difference between the reference oscillation and that supplied by the oscillator. The first low-pass filter transfer function is adapted to the phase-locked operation of the loop, while the second transfer function is adapted for frequency capture.

Abstract: There is disclosed a circuit for providing a comparison signal representing phase relationship between a clock pulse train and a variable rate input pulse train. The comparison signal can be used to synchronize clock and input pulse trains. The circuit includes a phase difference measuring circuit providing a first signal proportional to phase difference between input pulse train and clock pulse train, the signal having related discontinuities at the points of minimum and maximum phase difference between input and clock pulse trains. A second signal is generated representing a selected value of phase difference, the selected value being greater than the minimum phase difference and less than the maximum phase difference. First and second signals are then compared to provide a signal representing difference between the measured and selected values of phase difference.

Abstract: The acquisition means includes a voltage controlled oscillator, comparison means for comparing an input signal to a signal from the voltage controlled oscillator, filtering means and a summing network connected in a phase-locked loop and providing an output signal at an output thereof at the input of said summing network, a signal multiplying network connected to receive the input signal and a signal from the VCO of the phase-locked loop and providing an output signal approximately 90 degrees out of phase with the output signal of the phase locked loop and two all pass networks connecting the output signals from the multiplying network and the phase locked loop to two inputs of a multiplier which has an output connected to the summing network, the all pass networks being designed to shift the phases of the signals so that they are in phase when applied to the multiplier.

Abstract: An incoming signal including the object signal and plurality of noise signals dispersed about the object signal is fully masked with white noise and applied to a phase synchronization loop wide in loop band width and including a local oscillator repeatedly swept by a sweep generator. During the repeated sweep a control signal generator successively decreases the level of the white noise until the oscillator is locked in the phase of the object signal. At that time the signal control generator is operated to suspend the sweeping operation and prevent the white noise from being added to the incoming signal.

Abstract: The inventive synchronization circuit accepts a reference input signal and produces a signal which is in both phase and frequency lock therewith. The reference signal is quadrature detected via a voltage controlled oscillator signal, a quadrature phase shifter and a pair of mixers. A frequency error signal is generated by processing the mixer outputs through a phase detector and integrator. A phase error signal is produced by extracting and combining the DC components of the signals at the mixer outputs. The frequency and phase error signals are summed to produce a control signal which is fed back to the voltage controlled oscillator, thus causing the oscillator signal to tend to lock in frequency and phase with the input reference signal.

Abstract: Method and apparatus for demodulation of a phase shift keyed carrier in which a plurality of auxiliary signal frequency sources are provided and a substantially constant phase difference is maintained therebetween. Each auxiliary signal frequency is mixed with the modulated carrier and the mixer outputs are combined to form the product thereof to yield a control signal for regulating the auxiliary.The sum and differences of the mixer output may be formed prior to forming the product thereof.Input signals to the product forming circuit are amplitude limited to limit variation of the control signal r between -1 .ltoreq.r .ltoreq.+1.A filter may be employed to smooth the control voltage and may be incorporated with switching means to periodically interrupt the control signal to limit evaluation only during the established keying phase.

Abstract: Apparatus for indicating whether a correlation tracking system such as a phase-locked-loop has locked onto a periodic signal or not, utilizing a quadri-correlation circuit and digitalizers for the in-phase and the quadrature correlation signals, and logic circuitry for detecting the direction of transitions in the output state combinations of the digitalizers, and for adding the detector output signal rates for obtaining lock.

Abstract: A received, suppressed carrier, quadraphase shift key modulated (QPSK) signal is demodulated with a phase locked loop including a variable frequency, coherent reference that drives first and second channels also responsive to the QPSK signal. The channels respectively derive first and second replicas of binary signals that modulated the suppressed carrier. The replicas are combined to derive a variable amplitude error signal for controlling the coherent reference frequency. The frequency of the coherent reference is dithered at a low rate so that there is derived a relatively low level tracking error phase from the locked loop. The frequency of the coherent reference is swept when the phase of the error signal differs from the dithering phase by a predetermined value that is appreciably less than 90.degree..

Abstract: An improved quadraphase shift keyed (QPSK) adaptive demodulator includes a Costas loop modified to independently cross couple the inphase (I) and quadraphase (.phi.) channels so that minimum cross talk takes place between the I and Q channels. Advantageously, the improved QPSK adaptive demodulator separates the feedback control for correcting the phasor errors in the I and Q phasors. Advantageously, the improved demodulator permits independent phase adjustment of the I and Q demodulator outputs.

Abstract: A phase lock loop system that includes a voltage controlled oscillator. The output of an integrator provides the voltage to a tuning port for determining the precise frequency and phase of the oscillator. In response to a change in frequency, the input to the integrator is switched off at the precise time that its output voltage reaches the value for the proper phase relationship at the new frequency. The output of a low pass filter fed by the loop's phase detector determines such precise time. At said precise time, the stabilized condition of the loop is sensed and corrected for minor deviations.

Abstract: An automatic phase and frequency control system includes a pair of multipliers coupled to a source of input signal. A voltage controlled oscillator is also coupled to each of the multipliers. Means are provided to phase shift the oscillator signal at one multiplier such that quadrature beat signals are produced. The output of one of the multipliers is coupled directly to a third multiplier while the output of the other is coupled to a low pass filter. The filtered signal is amplitude limited and applied to the third multiplier. A second low pass filter couples the output of the third multiplier to the frequency control input of the voltage controlled oscillator.

Abstract: A narrow-band tone decoder has a controllable oscillator, connected in a fast-capture phase-locked loop, for generating a signal having a frequency determined by a control signal produced within the loop. A synchronous detector, which responds to an input signal of the tone decoder and to a signal from the controllable oscillator, produces a signal having a magnitude dependent upon the magnitudes of the input signal and of the signal from the controllable oscillator. A window comparator monitors the control signal within the loop for deciding when the generated signal is within a predetermined frequency range.

Abstract: A frequency locked loop that provides an output voltage waveform locked in frequency with an input voltage waveform. The output waveform is provided by a voltage controlled oscillator that is resettable to permit adjustment of the frequency of its output waveform.

Abstract: A phase lock loop configuration having a voltage controlled oscillator utilized, for example, in radar systems wherein false locking is prevented and loop bandwidth is maintained substantially constant. The voltage controlled oscillator includes a cavity resonator within which is located two tuning varactor diodes, one of which is heavily coupled to the resonator and comprises a coarse tuning port and one of which is lightly coupled and comprises the fine tuning port. The configuration is such that when the loop is locked, following a sweep mode of the coarse tuning voltage, the fine tune voltage is held constant at a predetermined DC level thereby making the fine tuning sensitivity essentially constant as the coarse tuning voltage changes the frequency over the band of interest.

Abstract: Phase detectors in quadrature whose outputs are simultaneously coupled to: high pass networks and cross coupled multipliers with the output summed to produce a signal proportional to the frequency difference of the signals applied to the aforesaid phase detectors; and, multipliers arranged to square the output of each phase detector whose outputs are summed to produce a signal proportional to the square of the product of the amplitudes of the signals applied to the aforesaid phase detectors.