Abstract: An oscillator circuit includes: oscillating transistors; a resonance circuit that includes varactor diodes each having a cathode to which a control voltage for controlling an oscillation frequency is applied and that is coupled between a collector and a base of each of the oscillating transistors; and a bias power supply that applies the bias voltages to the anodes of the varactor diodes. The bias voltages are given negative temperature characteristics, and a variation in the oscillation frequency caused by a change in the capacitance values of the varactor diodes due to a temperature variation is corrected by varying the bias voltages corresponding to the temperature variation.

Abstract: The present invention pertains to an oscillator arrangement for carrying out a frequency modulation process, wherein an oscillator (1) with automatic amplitude control (5, 6, 7) is provided. The shift keying is not realized with reconnectable capacitances in the oscillator (1) that determine its oscillator frequency, but rather by suitably influencing (6) the feed current of the oscillator in dependence on the modulation signal (FSK), namely with the aid of the amplitude control (5, 6, 7). Undesirable charge injections do not occur in the proposed oscillator arrangement because reconnectable capacitances are no longer required for achieving the desired frequency deviation.

Abstract: An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.

Abstract: An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.

Abstract: A digitally controlled oscillator circuit is provided that comprises a ring oscillator including multiple inverters; multiple digitally controlled capacitors (DCCs), each coupled to apply a digitally controllable amount of capacitance to an output of a different one of the inverters; and control circuitry operable to change an amount of capacitance applied to each inverter during operation of the ring oscillator and to cause the multiple DCCs to apply substantially the same amounts of capacitance to each of the inverter throughout operation of the ring oscillator.

Abstract: A refresh control circuit includes a reference voltage generating circuit and an oscillator unit. The reference voltage generating circuit generates a reference voltage based on a variation in a drain-to-source voltage of a field effect transistor according to a temperature variation. The oscillator unit generates a pulse signal having a period that varies according to the temperature based on the reference voltage. The refresh period is thereby controlled automatically, in accordance with the operating temperature.

Abstract: A driver device for a voltage-controlled oscillator, having an unstable voltage source, a voltage regulator, a driver for generating a control voltage for the oscillator, and a feedback loop which controls the driver as a function of the output signal of the oscillator; the voltage regulator supplying the feedback loop with operating voltage while the driver is powered by the unregulated voltage of the voltage source, and the feedback loop compensates for voltage fluctuations of the voltage source with the aid of the driver.

Abstract: An apparatus and method for providing a power supply compensated voltage or current is presented. A supply compensated current and voltage source utilizes a differential amplifier connected to a bandgap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator.

Abstract: An oscillation circuit includes a constant current source, a current mirror circuit configured to receive a constant input current from the constant current source and to output a current proportional to the constant input current, a first inverter configured to be driven with a quartz resonator to oscillate, an operational amplifier configured to supply power to the first inverter with a voltage equal to an input voltage of the operational amplifier and a second inverter having a power supply terminal connected to the current mirror circuit and to the operational amplifier and configure to generate the input voltage for the operational amplifier.

Abstract: A circuit arrangement for generating oscillations with a defined frequency includes an oscillator circuit (30, 32) for generating the oscillations and a dedamping circuit (18, 20) connected to the oscillator circuit for compensating any damping of the oscillator circuit. The dedamping or damping compensation by the dedamping circuit is accomplished with the aid of a rectifier circuit (60, 62). The dedamping circuit is a bridge circuit of CMOS field effect transistors (22, 24; 26, 28) which are controlled in their operation in closed loop fashion by respective rectifier circuit branches which are in turn connected to the oscillator circuit to provide a proportional closed loop control of the damping compensation.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: A low phase noise crystal oscillator with supply noise filtering is provided and may comprise receiving an input voltage at a positive potential input of an oscillator circuit, which may comprise an oscillator core and a buffer coupled to an output of the oscillator core. Noise caused by the input voltage that may affect the buffer may be filtered using a resistor coupled between the positive potential input of the oscillator circuit and the input voltage, and a capacitor coupled between the positive potential input of the oscillator circuit and a ground of the oscillator circuit. The noise may be filtered via a low pass filter, which may comprise at least the resistor and the capacitor. A cutoff frequency may be selected for the low pass filter, and a resistance value for the resistor and a capacitance value for the capacitor may be selected appropriately.

Abstract: A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.

Abstract: A real time clock that operates an oscillator within a predetermined range by employing a constant current source. The remaining real time clock logic can be operated at a voltage that is relative to the constant current. Power consumption of the oscillator can be controlled by limiting the current from the constant current source. The outputs of the oscillator can be input into a signal detector. A clocking signal can be produced by the signal detector based on the oscillator signals. The current provided by the first current source is limited to provide low power operation of the oscillator. Optionally, the signal detector can employ a differential amplifier. The differential amplifier receives the oscillator outputs, and provides a clocking signal based on the oscillator outputs.

Abstract: A clock generator capable of providing reduced low-frequency jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.

Abstract: An apparatus for characterizing an operating parameter in an integrated circuit, in accordance with one embodiment of the present invention, includes a voltage potential module, a plurality of distribution systems and a plurality of ring oscillator modules. Each ring oscillator module is coupled to the voltage potential module by a respective distribution system. Each ring oscillator module generates an oscillator signal as a function of the voltage potential and a voltage drop caused by the respective distribution system. The characterization of the operating parameter may be extrapolated from the difference in the operating frequencies of the ring oscillator modules.

Abstract: An oscillation-stop detection circuit includes a switching unit that repeats turning on and off based on a cycle of an oscillation signal from an outside; a capacitor that is charged when the switching unit is turned on, and discharged when the switching unit is turned off; a first MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged; a discharge cutoff unit that cuts off a discharge path for the discharge current to flow, for a predetermined time right after a power is turned on; and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1–INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1–INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Abstract: A system comprising a voltage controlled oscillator is disclosed. The voltage controlled oscillator includes a single input, a power input, and an oscillation input. The oscillation input is coupled to a amplitude detection device, which in turn provides an indication of an amplitude of the output of the VCO to a threshold detect module. Based upon the threshold detected at the threshold detect module, a threshold indicator is provided to a voltage supply module. The voltage supply powering the voltage controlled oscillator is varied, based upon a value of the threshold indicator.

Abstract: An oscillator circuit may be operated in a high power mode or a reduced power mode. The high power mode provides fast start-up of the oscillator circuit.

Abstract: An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.

Abstract: A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.

Abstract: A circuit arrangement for generating a reference current and also an oscillator circuit having the circuit arrangement are disclosed the arrangement includes a capacitance connected to an input of a voltage-controlled current source. Two amplifiers having different drive capabilities, between which a switching can be effected, are provided to drive the capacitance. An LC oscillator can be fed with the reference current in a current-controlled manner and at the same time in a particularly low-noise manner.

Abstract: A logic system with adaptive supply voltage control comprising a logic circuit clocked by a clock signal from a clock generating circuit and a voltage conversion circuit for generating a dynamically regulated supply voltage for powering the logic circuit. A critical path delay of the logic circuit is designed to be equal to or shorter than a period of the clock signal. The voltage conversion circuit dynamically regulates the supply voltage of the logic circuit based on a bias voltage of the clock generating circuit. According to the invention, the power consumption is effectively minimized while ensuring the logic circuit to function correctly throughout all conditions.

Abstract: A digital adaptive power supply interface has two feedback loops, each including a VCO, to automatically compensate for temperature and semiconductor process variations. A first loop compares the system input phase/frequency to a reference voltage that has been converted to a first digital frequency signal by a VCO in the first loop, and generates an analog difference signal. The second loop compares this analog difference with the power supply output voltage, and a VCO in this second loop converts result of this comparison to a second digital frequency signal. The digital frequency signals of the two loops are fed respectively to two registers and the content of the registers are subtracted, one from the other, to generate a digital error signal adjust the power supply output voltage to the input frequency.

Abstract: An amplitude control circuit comprises a first circuit configured to receive differential signals and provide a first signal based on the amplitudes of the differential signals, a second circuit configured to receive a bias signal and provide a second signal based on the bias signal, and a third circuit configured to provide bias to the first circuit and the bias signal to the second circuit. The bias signal is set to provide selected amplitudes of the differential signals.

Abstract: A crystal oscillation circuit has a reduced circuit area and enables to stably oscillate at low consumed current. The crystal oscillation circuit includes an oscillating amplifier and a constant voltage generator. The oscillating amplifier excites a resonator composed of a resistor, a crystal oscillator and a capacitor. The constant voltage generator includes a one-stage differential circuit composed of a transistor and a capacitor for suppressing transient fluctuation of a constant voltage Vreg for generating the constant voltage Vreg served as a supply voltage for the oscillating amplifier. By generating the constant voltage Vreg through the one-stage differential circuit, the phase lag of the constant voltage Vreg reaches 90 degrees at most. This eliminates the necessity of a phase compensation capacitor, resulting in making the circuit area smaller and realizing the stable oscillation at low consumed current.

Abstract: There is disclosed an inverter oscillator circuit delivering an alternating output signal and including a parallel arrangement, between an input terminal and output terminal, of an inverter amplifier means, a resonator, and a resistor, first and second load capacitors being respectively connected between said input and output terminals, on the one hand, and a supply potential, on the other hand. Control means for controlling the inverter amplifier means such that it has a so called start-up transconductance value during a start-up phase and a so-called reduced transconductance value, lower than said start-up transconductance value, in steady state at the end of said start-up phase. Means for smoothing an amplitude decrease in the output signal resulting from the passage of said start-up transconductance value to said reduced transconductance value is included.

Abstract: A temperature-compensated crystal oscillator is provided with an IC (integrated circuit) having a power supply terminal, an output terminal, and an automatic frequency control (AFC) voltage input terminal. In the temperature-compensated crystal oscillator, at least one oscillation circuit is integrated and the frequency-temperature characteristic of a quartz crystal unit is compensated. The temperature-compensated crystal oscillator includes one or more damping resistors for reducing the resonance acuteness of parasitic resonance circuits which result from inductance produced when mounting the IC on a wiring board and stray capacitance existing in the vicinity of each terminal of the IC. The dumping resistors are connected to at least one of the power supply terminal, output terminal, and automatic frequency control voltage input terminal.

Abstract: An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

Abstract: A voltage-controlled oscillator (VCO) for a phase-locked loop (PLL) has improved bandwidth and performance at lower frequency. A variable current source supplies a current to an internal oscillator-power node. The current varies with the VCO input voltage. The internal oscillator-power node drives the sources of p-channel transistors in inverter stages in the ring oscillator. The variable current causes the internal oscillator-power node's voltage to vary, which varies the output frequency. An active resistor is in parallel with the ring oscillator. The active resistor has a resistor and an n-channel transistor in series between the oscillator-power node and ground. The n-channel transistor has a fixed bias voltage on its gate and is non-linear. The non-linear effective resistance of the n-channel transistor improves overall linearity of the ring oscillator. The parallel effective resistance of the active resistor lowers overall effective resistance of the ring oscillator.

Abstract: Oscillator circuit with an LC resonant circuit 1, an activating component 2 connected to the LC resonant circuit 1, which serves to compensate for the losses occurring in the LC resonant circuit 1, where the series-configuration of both the LC resonant circuit 1 and the activating component 2 is connected by way of a current-defining element, which sets the current flowing between a first voltage VDD and a second voltage VSS, which is different from the first voltage VDD.

Abstract: A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a refresh interval. The refresh interval depends on a frequency of an oscillating signal. A refresh timer adjusts the frequency of the oscillating signal based on changes in the temperature to adjust the refresh interval.

Abstract: A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

Abstract: In some embodiments, a ring oscillator includes a plurality of delay cells coupled in series as a ring, and a replica cell coupled to the delay cells to provide at least one bias signal to the delay cells. The replica cell includes a differential transistor pair formed of a first transistor and a second transistor. The first transistor has a drain terminal and a gate terminal coupled to the drain terminal. The second transistor has a drain terminal and a gate terminal coupled to the drain terminal of the second transistor.

Abstract: A variable-frequency oscillator (10) is formed to change an internal delay of the oscillator inversely proportional to changes in the frequency of the oscillator.

Abstract: The voltage controlled oscillator circuit includes a resonant circuit, with two inductive elements (L1, L2) and a variable capacitive element (CV), which is connected to a high potential terminal (VEXT) of a voltage source, and a pair of cross-coupled NMOS transistors (N1, N2), which is connected between two oscillating signal (VA, VB) output terminals of the resonant circuit. Each NMOS transistor of the pair is connected in parallel to a diode mounted NMOS transistor (N3, N4) so as to form a current mirror. An identical current is supplied to each diode mounted transistor in an oscillating signal amplitude regulation loop. Two resistors (R1, R2) series connected between the gates of the transistors of the pair (N1, N2) allow extraction of the common mode voltage to be stored in a filtering capacitor (Cm) in order to bias a reference NMOS transistor (N5) connected to a reference resistor (R3).

Abstract: This oscillation circuit includes a crystal oscillator and a main circuit portion connected by a signal path to the crystal oscillator and driven by the crystal oscillator. The main circuit portion is provided with a DC-cutting capacitor that galvanically separates the signal path between the input side of an inverter that is connected by the signal path to the crystal oscillator and an input terminal Xin of the signal path. A potential stabilization circuit is also provided, connecting the input terminal Xin of the signal path to the output side of the inverter through a resistance element.

Abstract: An oscillator circuit includes a tank circuit, first and second oscillator transistors, and a gain-cell tuning inductor. The tank circuit includes first and second ports, and is configured to resonate at one or more predefined frequencies. The first oscillator transistor includes first port, a second port coupled to the first port of the tank circuit, and a third port. The second oscillator transistor includes a first port, a second port coupled to the second port of the tank circuit, and a third port. The gain-cell tuning inductor is coupled between the third ports of the first and second oscillator transistors and is operable to conduct a biasing signal supplied thereto to the third ports of the first and second oscillator transistors.

Abstract: Periodically, sensed amplitude for the output signal of a voltage-controlled oscillator is compared to a reference and biasing of the voltage-controlled oscillator is correspondingly set, thereby controlling amplitude of the voltage-controlled oscillator output signal. Process and temperature dependencies of the amplitude are eliminated while achieving low phase noise and large signal-to-noise ratio in the output signal, and consequently low phase noise.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A fast start up oscillator. The fast start-up oscillator includes a power-on-reset detect circuit, a bandgap circuit, a voltage detect circuit, a RC-oscillator, and a count two circuit. The fast start-up oscillator is provided with a fast stabilized voltage source to ensure oscillation accurate and quickly such that the system is woken up.

Abstract: An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: A clock oscillator circuit that includes an inverting amplifier and a resonator configured to generate an oscillating signal. The clock oscillator includes a bias circuit having a relatively constant current source configured to create a bias voltage to bias the amplifier in an operating state that can sustain the oscillating signal. The inverting amplifier and the bias circuit are configured to operate in a low power state.

Abstract: A self-biased voltage controlled oscillator (VCO) that includes a VCO core including a plurality of switching transistors, a resonant tank circuit operatively coupled to the VCO core, a current source operatively coupled to the VCO core for supplying a bias current to the VCO core, and a biasing circuit operatively coupled to both the resonant tank circuit and to the current source. The biasing circuit and the switching transistors of the VCO core cooperatively function to bias the current source, whereby the VCO is self-biased.