Abstract: An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: A first and a second resonator are fabricated monolithically adjacent to one another. The first resonator is the reference resonator. The resonant frequency of the second resonator is offset by a difference frequency Fo from the first resonator. Each resonator is included within an oscillator. A mixer receives the output of both oscillators. A low pass filter receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo.

Abstract: This invention makes it possible to reduce a power consumption of an electronic circuit (microcomputer, for example) while preventing malfunctioning of an oscillator by appropriately setting a power supply impedance of a low frequency oscillator corresponding to an operation mode. A high frequency oscillator, a medium frequency oscillator and a low frequency oscillator are provided as sources of system clocks. In addition, there is provided a quartz oscillator to generate a clock for a timepiece. When the high frequency oscillator is in operation, a power supply impedance of the quartz oscillator is reduced to improve a noise tolerance. In a waiting period during which the high frequency oscillator, the medium frequency oscillator and the low frequency oscillator are halted, on the other hand, the power supply impedance of the quartz oscillator is increased to suppress the power consumption.

Abstract: An apparatus including a resonator electrode and a second electrode separated from the resonator electrode by a gap having a size that facilitates electron transfer across the gap, wherein the resonator electrode is a resonator electrode mounted for oscillatory motion relative to the second electrode that results in a size of the gap between the resonator electrode and the second electrode being time variable; a feedback circuit configured to convey an electron transfer signal dependent upon electron transfer across the gap as a feedback signal; and a drive electrode adjacent the resonator electrode configured to receive a feedback signal from a feedback circuit configured to provide a time-varying feedback signal dependent upon electron transfer across a gap.

Abstract: Systems and methods are provided for determining the value of a capacitance. A system for sensing capacitance comprises an oscillator arrangement comprising a plurality of oscillators and a mismatch compensation arrangement coupled between the oscillator arrangement and a first capacitive element having a first capacitance. The mismatch compensation arrangement is configured to selectively couple the first capacitive element to a respective oscillator of the plurality of oscillators, wherein an oscillation frequency of the respective oscillator is influenced by the first capacitance.

Abstract: A VCO comprising a cross-coupled transistors module and a resonant module is provided. The resonant module comprises a first transistor, second transistor, a first inductor and varactor string and a second inductor and varactor string. The first source/drain terminal of the first transistor coupled to the second reference voltage, the second source/drain terminal of the first transistor coupled to the cross-coupled transistors module and the gate terminal coupled to a bias voltage. The first source/drain terminal of the second transistor coupled to the second reference voltage, the second source/drain terminal of the second transistor coupled to the cross-coupled transistors module and the gate terminal of the second transistor coupled to the bias voltage. The first and second inductor and varactor strings coupled between the gate of the first and second transistors and a tuning voltage in serial, separately.

Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.

Abstract: A multi-phase ultra-wideband signal generator uses differential pulse oscillators. The multi-phase ultra-wideband signal generator using differential pulse oscillators includes N pulse oscillators for generating pulse signals based on a supply of power, and further comprises N inverting amplification units for outputting inverted amplified signals of output signals of the N pulse oscillators when a number of pulse oscillators is at least two, wherein, when the number of pulse oscillators is an even or odd number, the pulse oscillators are arrayed such that they have a connection form in which output terminals OUT(+) and OUT(?) of a relevant pulse oscillator are connected to output terminals OUT(+) and OUT(?) of a next pulse oscillator through a relevant inverting amplification unit, and the connection form is consecutively applied to the pulse oscillators.

Abstract: Provided are a harmonic rejection mixer and a harmonic rejection mixing method. A plurality of oscillator signals having a ? duty cycle and uniform phase differences may be generated and a differential or quadrature mixer with harmonic rejection may be realized by using the oscillator signals.

Abstract: Phase locked loop based frequency tuning of an adjustable filter is disclosed. A resonant circuit includes the adjustable filter, and an oscillator signal provides an input to the resonant circuit.

Abstract: A system may include a first circuit configured to generate a first clock having a first period of oscillation, and a second circuit configured to generate a second clock having a second period of oscillation, where the difference (?T) between the first period of oscillation and the second period of oscillation remains within a specified limit even during variations in temperature and/or during variations in the supply voltage. The system may further include a control circuit, which may receive the first clock and the second clock, and adjust, according to ?T, a first target parameter corresponding to a first number of cycles of the first clock, when a current cycle count of the second clock reaches a second target parameter corresponding to a second number of cycles of the second clock.

Abstract: A random number generator comprises a first high frequency (HF) oscillator, a second low frequency (LF) oscillator, a delay buffer, a multiplexer, and a sampling circuit. The HF oscillator generates a high frequency oscillating signal. The LF oscillator generates a low frequency oscillating signal. The multiplexer selects from the LF oscillating signal and one or more delayed version of the LF oscillating signal to generate a third oscillating signal. The third oscillating signal is then used to sample the HF oscillating signal to output a random bit stream. In one preferred embodiment, the random bit stream is feedback to the multiplexer to make randomized selection. As a result, the original jitter distribution of the LF oscillating signal is increased to a larger jitter distribution of the third oscillating signal to increase the random behavior of the output bit stream.

Abstract: System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO.

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract: A multi-phase oscillator includes a plurality of ring oscillators (21) each having a plurality of output ports and each formed by connecting an odd number of inverters (20) in a ring, and a plurality of resistance elements (30) coupling the output ports between the plurality of ring oscillators (21) so that all of the plurality of ring oscillators (21) operate at an identical frequency while keeping a desired phase relationship. The number of the ring oscillators (21) is not limited to an odd number but may be an even number. The multi-phase oscillator changes the state of a succeeding node of a phase coupling to accord with the state of a preceding node of the phase coupling by using the resistance elements (30) as phase coupling devices. If resistors are used as the resistance elements (30), the phase output accuracy greatly improves and high frequency oscillation is possible.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB.

Abstract: Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

Abstract: An electric circuit includes: a reference signal generation circuit that generates a reference signal based on a first oscillation signal that is an oscillation signal of a first oscillation circuit that vibrates a first vibrator; and a counter circuit that counts a second oscillation signal that is an oscillation signal of a second oscillation circuit that vibrates a second vibrator based on the reference signal, and outputs a count signal, wherein the count signal is a change of the count value in the second oscillation signal.

Abstract: In a multi-radar system, configured comprising a plurality of radar units which generate and output signals the frequency of which increases and decreases periodically, each radar unit generates and outputs signals synchronized with a prescribed sync signal, such that the upper limit and lower limit of the periodically increasing and decreasing frequency is different for the signals of each radar unit, and moreover the timing of the upper limit and lower limit of the signals substantially coincide. By this means, the frequency intervals between signals can be reduced, and more channels can be set, without causing radio wave interference.

Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Abstract: Techniques for generating quadrature signals from a local oscillator signal, wherein the generated quadrature signals have a frequency half of the local oscillator frequency. In an exemplary embodiment, two oscillators, e.g., injection locked oscillators, are provided, each oscillator having a load, a cross-coupled transistor pair, an integrating capacitor, and current injection transistors. A differential pair is coupled to the leads of each of the integrating capacitors, and the drains of the differential pair are coupled to the outputs of the other oscillator to help increase the slew rate of the output voltages of the other oscillator. The inputs to the differential pair may be first amplified to improve the gain of the differential pair. In another exemplary embodiment, the power consumption of the differential pair may be reduced by operating them in a discontinuous mode, e.g., by coupling the source voltages of the differential pair to corresponding delayed versions of the drain voltages.

Abstract: One embodiment in accordance with the invention is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Abstract: The demodulator by direct frequency conversion comprises a vector addition device having: a first circuit (1) that furnishes, starting from a first AC signal (LO), a respective AC signal to n outputs that are not all of the same amplitude and of the same frequency, but are out of phase with regard to one another in such a manner that each one is not either in phase nor in opposite phase with any other; a second circuit (2) that splits a second AC signal (RFin) toward n outputs; a number n of summers (3a, 3b, 3c) each receiving, at the input, a respective output of the first circuit (1) and a respective output of the second circuit (2), and; a respective power sensor (4a, 4b, 4c) for each summer, whereby the number n is greater than or equal to 3. The demodulator also comprises digital processing means (5, 6) that furnish the result of the demodulation.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: The disclosure is related to oscillators and more specifically voltage controlled oscillators. Magnetic voltage controlled oscillators are presented that comprise current-biased magnetic thin film structures that can exhibit microwave oscillations and are tunable with current as well as magnetic field. In a particular embodiment, an array of oscillators, which may be activated with a current while in a magnetic field, can be positioned adjacent a spin valve layer to produce a spinwave disturbance in the spin valve layer. An array of detectors that can sense periodic motion of the magnetization of the spin valve layer may also be positioned adjacent the spin valve layer. The detectors may produce an oscillating output signal from the detected periodic motion.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

Abstract: An oscillator device includes an oscillation system having first and second oscillators and first and second resilient supporting members, wherein the oscillation system has at least two frequencies of natural oscillation mode around a torsion axis which include a first resonance frequency f1 and a second resonance frequency f2, wherein there is a relationship that f2 is approximately two-fold of f1, and wherein a drive control member supplies, to a driving member, a driving signal which is comprised of a driving signal based on synthesizing a first driving signal having a first driving frequency and a second driving signal having a second driving frequency, and which is such driving signal that, among the first and second driving frequencies, a lower-frequency side driving frequency Df1 and a higher-frequency side driving frequency Df2 satisfy a relationship Df1×2=Df2 and that Df2 satisfies a relationship f2?|?f/2|<Df2<f2+|?f/2|.

Abstract: A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.

Abstract: Real-time clock calibration is accomplished by generating a fast clock signal and a slow clock signal from an uncompensated clock signal; selectively, momentarily, replacing the uncompensated clock signal with the fast and slow clock signal to generate a compensated clock signal; generating from the compensated clock signal a calibration strobe and window trigger; responding to the window trigger to detect any uncompensated clock signal frequency error and responding to the calibration strobe to selectively, momentarily, replace the uncompensated clock signal with the fast or slow clock signal to reduce the clock signal frequency error.

Abstract: An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Abstract: The present invention relates to a two-frequency switchover type crystal oscillator in which first and second IC chips and first and second crystal resonators are connected to wiring patterns of a circuit substrate to form first and second oscillation circuits, and the first and second oscillation circuits are selectively operated in accordance with a selection mechanism; a two-frequency switchover type crystal oscillator in which surfaces opposite to circuit function surfaces of the first and second IC chips are connected to form a two-stage structure; IC terminals of the circuit function surface of the first IC chip are directly connected both electrically and mechanically to the wiring patterns; and IC terminals of the circuit function surface of the second IC chip are connected electrically by wire bonding to the wiring patterns; wherein those wiring patterns of the wiring patterns that are connected to power source, output, and ground terminals of the first and second IC chips are connected in common wit

Abstract: A multi-band electronic apparatus and method thereof is provided. The method comprises outputting a first output signal in the first band by a first voltage controlled oscillator according to a switch control signal and a control voltage, outputting a second output signal in the second band by a second voltage controlled oscillator according to the switch control signal and the control voltage, the second band being not completely overlapped by the first band, performing frequency division selectively on the first output signal or the second frequency divided signal according to the switch control signal, and outputting a first frequency divided signal, determining a phase difference between the first frequency divided signal and a reference signal to output a phase difference signal, outputting the control voltage according to the phase difference signal, and selectively driving the first or the second voltage controlled oscillators by the control voltage according to the switch control signal.

Abstract: In one embodiment, a multiple band oscillator system is disclosed which comprises a first oscillator having a first input, a resonating element, a first output, and a second output. In addition, the multiple band oscillator system also comprises a second oscillator having a second input, a third output, and a fourth output. The first oscillator has a first oscillator frequency and the second oscillator has a and second oscillator frequency. The multiple band oscillator system also contains a tuning capacitive element coupled to the first and second oscillators for determining the second oscillator frequency, and the first oscillator and the second oscillators are both capable of operating the resonating element.

Abstract: This invention makes it possible to reduce a power consumption of an electronic circuit (microcomputer, for example) while preventing malfunctioning of an oscillator by appropriately setting a power supply impedance of a low frequency oscillator corresponding to an operation mode. A high frequency oscillator, a medium frequency oscillator and a low frequency oscillator are provided as sources of system clocks. In addition, there is provided a quartz oscillator to generate a clock for a timepiece. When the high frequency oscillator is in operation, a power supply impedance of the quartz oscillator is reduced to improve a noise tolerance. In a waiting period during which the high frequency oscillator, the medium frequency oscillator and the low frequency oscillator are halted, on the other hand, the power supply impedance of the quartz oscillator is increased to suppress the power consumption.

Abstract: A clock distribution system that includes a length of two-conductor transmission line driven differentially at one end and terminated at the other end, a plurality of regeneration devices, and a plurality of regeneration device pairs. The two-conductor transmission line is arranged in a serpentine configuration with a number of locations at which portions of the transmission line come physically close to each other. The regeneration devices are located at various spaced-apart positions on the transmission line and operate to provide energy to a wave traveling on the transmission line. Each of the regeneration device pairs is connected between the transmission line portions that are physically close to each other so as to cause a traveling wave on adjacent portions of the line to have opposite phases.

Abstract: A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the two oscillators of intentionally different frequencies are periodically switched at a duty factor, which is dependent on an absolute temperature, to generate a calibrated, precise, and temperature-stable clock.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Abstract: In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.

Abstract: A method and apparatus for selecting an optimum VCO from an array of VCOs is disclosed. Each VCO in the array has an output range and a limit. In one embodiment, a search set of VCOs is designated as all VCOs in a system. The limit is compared to a tuning value which corresponds to a desired calibration frequency. The comparison divides the array of VCOs into a searched set and a non-searched set. The process is repeated until the non-searched set comprises only one VCO. In another embodiment, the VCOs are ordered such that there is a middle VCO. A VCO in the middle of the array is selected. The limit of the middle VCO is compared to a tuning limit. Based on the comparison, another VCO is selected. The process repeats N times, where N is the logarithm, base 2, of the total number of VCOs to be searched. at the end of the search, an optimum VCO will be found.

Abstract: A Trigger-Mode Distributed Wave Oscillator that provides accurate multiple phases of an oscillation and a method of use of the same. An auxiliary oscillator triggers an oscillation on independent conductor loops or rings forming a differential transmission medium for the oscillation wave. Once the oscillation wave is triggered, the auxiliary oscillator can be powered down to turn it off, and the wave can sustain itself indefinitely through active amplifying devices which can compensate for losses in the conductors.

Abstract: Device and method for temperature compensation in a clock oscillator using quartz crystals, which integrates dual crystal oscillators. The minimal power consumption is achieved through an efficient use of a processor in charge of the synchronization of the two oscillators. The invention is particularly adapted for the provision of a precise reference clock in portable radiolocalization devices.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.