Abstract: A target signal analyzer having at least one receiving antenna configured to receive the target signal, and a parallel array of oscillator rings. Each oscillator ring is operatively coupled to receive the target signal from the receiving antenna. Each oscillator ring has an odd number of at least three bistable, nonlinear oscillators circularly coupled to each other such that only one-way signal flow is allowed between the oscillators in each oscillator ring. Each of the oscillator rings is configured to oscillate and thereby produce a response signal only when the target signal frequency is within a designated frequency band. For every designated frequency band in a spectrum of interest, at least one of the oscillator rings is configured to produce a response signal.

Abstract: A ring oscillator comprises a control circuit for receiving a frequency-selection signal operative to select from at least two ring oscillator frequencies, said control circuit using said control signal to generate a first control signal and a second control signal; a primary chain of an odd number of serially connected NOT gates, said primary chain including a primary switching NOT gate responsive to the first control signal and operative to perform a logical NOT or an IGNORE function on a first oscillating input signal to generate a first output signal; and a secondary chain of serially connected NOT gates, said secondary chain logically parallel to at least said primary switching NOT gate, said secondary chain including a secondary switching NOT gate responsive to the second control signal and operative to perform a logical NOT or an IGNORE function on a second oscillating input signal to generate a second output signal.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a random number generator (RNG) based on oscillator noise. In some embodiments, the RNG buffers effects of thermal noise from two independent oscillators impacted by effects of pseudo-stochastic processes and separates thermal noise from other effects. The RNG may then convert the thermal noise to a stochastic binary sequence based, at least in part, on a digital signal processing algorithm.

Abstract: A system for generating a multiple phase clock is provided. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M. Another structure generates multiple phases using a multi-dimensional oscillator including ring oscillators constructed as vertical and horizontal loops with shared elements between the oscillators. A memory system includes a ring oscillator structure with vertical and horizontal loops, the ring oscillator structure receiving an input clock and outputting a multiple phase clock to one or more of a memory controller, memory devices and a memory interface device.

Abstract: Provided is an oscillating apparatus that includes a plurality of variable frequency oscillators, each of which is provided in correspondence with a different oscillating band from one another; and a selection section that selects an oscillating signal that is from a variable frequency oscillator provided in correspondence with a designated oscillating band, from among the plurality of variable frequency oscillators, and outputs the selected oscillating signal, where the selection section includes a plurality of selectors connected in a tree structure, each selector outputting a selected one of inputted two or more oscillating signals, and each of the plurality of variable frequency oscillators is connected to a selector positioned at an end of the tree structure of the plurality of selectors.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures.

Abstract: A radiation hard design for oscillator circuits and circuits having differential outputs is described. The design includes connecting or otherwise coupling outputs of these circuits to a passive polyphase filter. The passive polyphase filter provides four quadrature outputs that are free of glitches that may have occurred at the filter input.

Abstract: A carrier generator for generating a carrier at a frequency of interest in a wireless communications system comprises an oscillator exhibiting a first impedance, the oscillator comprising an energy storage tank configured to generate a periodic signal, the energy storage tank including at least one inductor and at least one capacitor, and an amplifier coupled with the energy storage tank, the amplifier being configured to amplify an amplitude of the periodic signal, an antenna exhibiting a second impedance smaller than the first impedance, and a network coupled between the oscillator and the antenna, the network including at least one inductor or at least one capacitor and being configured to provide a third impedance such that a resultant impedance of the second impedance and the third impedance as viewed from the oscillator toward the antenna is large enough to facilitate the oscillator to generate the carrier at the frequency of interest.

Abstract: A mechanical oscillator has components with dimensions in a sub-micron range to produce resonance mode oscillations in a gigahertz range. A major element is coupled to a minor, sub-micron element to produce large amplitude gigahertz frequency oscillation that is detected with readily available techniques. The mechanical structure can be formed according to a number of geometries including beams and rings and is excited with electrostatic, magnetic and thermal related forces, as well as other excitation techniques. The mechanical structure can be arranged in arrays for applications such as amplification and mixing and is less sensitive to shock and radiative environments than electrical or optical counterparts.

Abstract: An oscillator is provided that includes a first oscillation generating device for generating an oscillation in response to an excitation signal, whereby the first oscillation generating device has a first terminal and a second terminal; a second oscillation generating device for generating an oscillation in response to an excitation signal, whereby the second oscillation generating device has a third terminal and a fourth terminal; an excitation device, which is formed in a first mode to apply an excitation signal between the first and second terminal of the first oscillation generating device, and in the first mode to apply the excitation signal between the third terminal and the fourth terminal of the second oscillation generating device to obtain a first oscillation with a first characteristic value, and in a second mode to apply an excitation signal between the first terminal of the first oscillation generating device and the third terminal of the second oscillation generating device and in the second mod

Abstract: The present invention concerns a phase-locked loop comprising: a variable oscillator connected to a first resonator, said oscillator being able to deliver an output signal at a first output frequency Fout1, a first frequency divider receiving said output signal and able to convert it into a divided frequency signal Fout1/n, a reference oscillator connected to a second so-called reference resonator, delivering a reference signal at a low reference frequency Fref, generating an electrical dissipation lower than a microampere, a phase comparator measuring the phase error between the divided frequency signal Fout1/n and the reference signal and being able to produce a test signal, a low-pass filter or an integrating circuit able to filter the test signal and able to generate a voltage or a control word designed to control the voltage-controlled or digitally controlled oscillator.

Abstract: In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.

Abstract: A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.

Abstract: An ILO circuit has a plurality of oscillator stages which are coupled to one another by means of a “tank lock” coupling. The coupling leads to an improved synchronization of the individual oscillator stages and thus to a reduced phase noise. Any desired LC oscillator topology can be used, not just the topology with PMOS and NMOS transistors. It is also possible to use SOI transistors, that is to say transistors formed on an SOI substrate. The bulk terminals of the transistors may be coupled not only to a supply voltage but, for example, also to a center potential, a reference voltage source, to ground, in floating fashion and/or to the source terminal.

Abstract: A real time clock assembly includes paired crystal oscillators that experience changes in frequency responsive to temperature. The differences in frequency changes between the paired crystal oscillators are utilized to determine a temperature utilized to compensate for those shifts in frequency. The predictability of frequency responsive to temperature variations by the paired crystal oscillators is utilized for the determination of temperature.

Abstract: Systems and methods are provided that compensate for frequency drift due to temperature variation without the need for a temperature sensor. In one embodiment, a navigation receiver with an integrated communication device receives a base station reference signal, which is used to periodically calibrate a local oscillator frequency. In another embodiment, the calibrated local oscillator frequency drives a counter that is used to provide code phase estimation at the start of satellite signal acquisition. To provide temperature compensation in one embodiment, the calibrated local frequency is used to drive one or more counters at different calibration rates (i.e., different time intervals between calibrations). Count values from these counters are used to determine compensation for frequency drift due to temperature variation based on predicted frequency drift variation patterns between calibrations.

Abstract: A method is provided for configuring a microcontroller clock system that includes a main oscillator, a phase locked loop, and a backup oscillator. According to the method, the main oscillator and the backup oscillator are activated in reset mode. A clock signal is generated from the backup oscillator, and the clock signal that is generated is applied to the microcontroller in order to start the microcontroller. Also provided are a clock system for a microcontroller, and a microcontroller including a clock system.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).

Abstract: A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

Abstract: A method for generating a temperature-compensated timing signal that includes counting, within an update interval, a first number of oscillations of a first micro-electromechanical (MEMS) resonator, a second number of oscillations of a second MEMS resonator and a third number of oscillations of a digitally controlled oscillator (DCO), computing a target DCO count based on the first number and second number of oscillations, computing a loop error signal based on the target DCO count and the third number of oscillations, and modifying an output frequency of a temperature-dependent (DCO) timing signal based on the loop error signal. The duration of the update interval may also be modified based on temperature conditions, and the update interval may also be interrupted and the output frequency immediately adjusted, if a significant temperature change is detected. Thus, dynamic and precise temperature compensation is achieved that accommodates constant, slowly changing, and rapidly changing temperature conditions.

Abstract: To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state.

Abstract: An oscillator coupling system includes a plurality of oscillating members and a plurality of delay members connecting at least two of the oscillating members. Between the delay members is a specific phase or time delay relationship such that characteristics of phase or frequency noise suppression correlation of the two oscillating members are coupled to each other by the delay members, thereby reducing noise autocorrelation while the oscillator coupling system is in operation, enhancing phase or frequency noise suppression, using no bulky elements such as solid state circulators, isolators and resonators, reducing signal distortion, and increasing system stability.

Abstract: A random number generator. The random number generator includes a noise source, a circuit controlling random current consumption, and a circuit generating random bits. A noise voltage output from the noise source drives the circuit controlling random current consumption, which also generates a random control signal. The circuit generating random bits also includes a voltage-controlled oscillator, a plurality of frequency dividers, and a plurality of flip-flops. The voltage-controlled oscillator is controlled by both the noise voltage and the random control signal. The output of the voltage-controlled oscillator is input to the frequency dividers and the flip-flops to generate a random number.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: A differential crystal oscillator electronic circuit. Embodiments of the present invention include circuits comprising two substantially similar oscillator circuits. The oscillator circuits may be coupled to a common crystal or ceramic resonator. Embodiments of the present invention are especially well suited to implementation within integrated circuits where their superior common mode and supply rejection function beneficially in opposition to the naturally high coupling characteristics of integrated circuits. Further, by naturally furnishing differential signals, these low noise signals may be used directly by other differential circuits on an integrated circuit, without requiring additional single ended to differential conversion circuitry.

Abstract: The present invention discloses an automatic page detector, to determine which page of a book is open. The automatic page detector uses a sensor plate and an inductor as a sensor. In the invention, there is a sensor plate at each page of the book and the locations of the sensor plates for different pages are different. There is an array of inductors just beneath the sensor plates when the book is closed. The inductors are connected to the feedback loop of a LC oscillator through analog switches. The proximity of a sensor plate to an inductor will change the frequency of the LC oscillator. Scanning the analog switches by a microprocessor and detecting the variation of frequency of the LC oscillator during each scanning time period, the status of each sensor plate will be detected and we can determine which page of a book is opened.

Abstract: Embodiments of the invention may provide for an LC quadrature oscillator that includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals and a phase and amplitude mismatch compensator. The phase and amplitude mismatch detector may include an amplitude mismatch detectors a transconductor, and a capacitor for compensating for both phase and amplitude mismatches between I/Q clock signals generated in the LC quadrature oscillator.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or ?processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.

Abstract: An oscillator for synchronizing and controlling a multi-phase, interleaved power supply system that has a plurality of power sources. The oscillator includes a first oscillator, having a pulse generator and a timing capacitor, and a second oscillator, having a pulse generator and timing capacitor, that are electrically coupled to one or more first power supplies and one or more second power supplies, respectively. The pulse generator of the first oscillator is electrically coupled to the second timing capacitor and the pulse generator of the second oscillator is electrically coupled to the first timing capacitor. Each of the pulse generators is structured and arranged to provide a synchronizing pulse to the other oscillator's timing capacitor when the voltage on its own timing capacitor is midway between a pre-determined maximum voltage threshold and a pre-determined minimum voltage threshold.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.

Abstract: A random number signal generator using pulse oscillators, the generator including: a first pulse oscillator oscillating a first pulse at high speed; a second pulse oscillator oscillating a second pulse; a sampler receiving an output pulse of the first oscillator as data, receiving an output pulse of the second pulse oscillator as a clock signal, and outputting a plurality of output signals; and a digital processor generating a random number signal with a desired size by using the output signals of the sampler.

Abstract: Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90° and ?90° as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a random number generator (RNG) based on oscillator noise. In some embodiments, the RNG buffers effects of thermal noise from two independent oscillators impacted by effects of pseudo-stochastic processes and separates thermal noise from other effects. The RNG may then convert the thermal noise to a stochastic binary sequence based, at least in part, on a digital signal processing algorithm.

Abstract: Signals outputted from oscillators (1-1, 1-2, . . . 1-n) are in phase with signals as reflected by band elimination filters (3-1, 3-2, . . . 3-n) at elimination frequencies of the band elimination filters (3-1, 3-2, . . . 3-n), while they are in opposite phase with signals leaked from the corresponding band elimination filters (3-1, 3-2, . . . 3-n). In this way, a stable oscillation can be performed with the oscillation frequencies of the oscillators (1-1, 1-2, . . . 1-n) balanced as optimum frequencies between the natural frequencies of the oscillators (1-1, 1-2 , . . . 1-n) and the elimination frequencies of the band elimination filters (3-1, 3-2, . . . 3-n), while the oscillators (1-1, 1-2, . . . 1-n) can be synchronized with the elimination frequencies being used as reference frequencies.

Abstract: A source coupled differential complementary Colpitts oscillator is described, which enables a differential oscillation and also can improve phase noise performance by source-coupling a complementary Colpitts oscillator using an inductor. A differential complementary Colpitts oscillator includes: a plurality of complementary Colpitts oscillators and a source coupler which couples a source node of the plurality of complementary Colpitts oscillators, enables the Colpitts oscillators to differentially oscillate.

Abstract: Disclosed is a dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing. The dual-band voltage-controlled oscillator includes a power supply unit for supplying a source voltage; plural voltage-controlled oscillation units for outputting different oscillation frequencies according to controls of a certain tuning voltage; plural bias units for generating driving voltages for driving the voltage-controlled oscillation units and supplying the driving voltages to the voltage-controlled oscillation units; and plural buffers for selectively outputting oscillation frequencies of the plural voltage-controlled oscillation units. The present invention implements the dual-band voltage-controlled oscillator through bias switching and output-buffer multiplexing, which brings an advantage of elimination of interference between output frequencies to enhance phase noise characteristics.

Abstract: Apparatus and method for producing a composite clock signal with optimized stability characteristics from individual clocks which have different stabilities or variances. The composite clock signal includes weighted individual clock signals. In a first (PPN) case, an optimum composite clock is a scale-factor-weighted linear combination of clock signals. In another (non-PPN) case, the optimum stable composite clock is the output of a linear filter of the input clocks signals. Both the phases and frequencies of the individual clocks over time are estimated.

Abstract: Present invention relates to an oscillator circuit comprising: resonator means (102) and, first and second emitter followers (116, 118) being symmetrically coupled to the resonator means and been connected to further emitter followers (120, 122) for providing capacitive loading.

Abstract: A first receiver frequency reference is passively coupled to a second receiver by tapping a signal directly from the resonant element, such as a crystal, of an oscillator in the first receiver to drive the input of the second receiver. The sinusoidal signal from the resonant element is relatively free of harmonics and minimizes interference that could be caused by harmonics of a square wave signal coupling or an amplified signal. The oscillator of each receiver can be selectively enabled or disabled to allow the receiver to either generate or receive the frequency reference. This technique of coupling can be used to couple a frequency reference signal between integrated circuit receivers.

Abstract: A low-power quadrature generator is provided for accurately generating in-phase signals and quadrature signals.

Abstract: Provided is a high-frequency oscillator whose output power increases without a change in physical size of the entire high-frequency oscillator and deterioration of a phase noise characteristic. The high-frequency oscillator for harmonic extraction includes: an active element (5); a fundamental reflection stub (9) provided on a signal line located on an output side of the active element (5); an output terminal (4); and a harmonic impedance converting circuit (3) interposed between the fundamental reflection stub (9) and the output terminal (4), for converting a harmonic output terminal side load impedance into an optimum value for maximizing harmonic output power, the optimum value being obtained in advance.

Abstract: Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

Abstract: When two oscillation signals are output from a common terminal through switching, to reduce attenuation of the oscillation signals, a dual-band oscillator includes a first oscillating transistor for generating an oscillation signal in a first frequency band; a first inductor for supplying power to a collector of the first oscillating transistor; a first switching element for switching the first oscillating transistor; a second oscillating transistor for generating an oscillation signal in a second frequency band; a second inductor for supplying power to a collector of the second oscillating transistor; a second switching element for switching the second oscillating transistor; and an output terminal for outputting the oscillation signal in the first frequency band or in the second frequency band. The first switching element is disposed between the first inductor and the output terminal, and the second switching element is disposed between the second inductor and the output terminal.

Abstract: A quadrature voltage controlled oscillator having low phase noise and excellent output swing characteristics includes a first voltage controlled oscillator for outputting a positive in-phase output signal and a negative in-phase output signal; a second voltage controlled oscillator for outputting a positive quadrature-phase output signal and a negative quadrature-phase output signal, the second voltage controlled oscillator having a symmetrical structure with the first voltage controlled oscillator and constituting a feedback loop together with the first voltage controlled oscillator; a first constant current source for supplying constant current to the first voltage controlled oscillator in response to the output signals; and a second constant current source for supplying constant current to the second voltage controlled oscillator in response to the output signals.

Abstract: A direct conversion RF transceiver (2) and ASIC having an on-chip voltage controlled oscillator operating frequency that is half of the transmitter (4) and/or receiver (6) operating frequency, the VCO (20) being comprised of a plurality of synchronized LC oscillators (92A-D) introducing precise phase shifts that eliminate frequency ambiguity. The transceiver incorporates several low power circuits, including on-chip a power converter switchably coupling a capacitor (42) to a power supply (45) and to an electrical load (40), multiple switchable low dropout regulators (60A, B) each coupled to alternate power supplies (62,64) and having electrical components (67A, B) for setting the bandwidth of the respective low dropout regulator. The transceiver also includes a FSK digital modulator utilizing a circuit-implemented polynomial piecewise approximation (71) of a raised cosine signal.

Abstract: System and method for providing clocks to digital circuitry with a need for multiple clocks. A preferred embodiment comprises an oscillator controller (oscillator clock domain block 305) distributes a system clock generated by an oscillator to a plurality of clock domain blocks (GSM clock domain block 310 and so forth). The clock domain blocks use the system clock to generate specific clocks needed by attached hardware. The clock domain blocks may be programmed after manufacture to permit customized clock generation to meet requirements.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.