Abstract: There is provided a frequency synthesizer including a multi-band voltage controlled oscillator having a plurality of voltage controlled oscillating cores outputting oscillation frequencies having different bands according to an input control voltage. Each of the voltage controlled oscillating cores outputs a frequency band divided into a plurality of bands, and the voltage controlled oscillating core operates by each of the divided bands, and one of the voltage controlled oscillating cores operates in one of the bands according to the control voltage. The frequency synthesizer further includes a comparator unit and an oscillation band-determining unit. The comparator unit compares the control voltage with a pre-set reference voltage range. The oscillation band-determining unit changes the band where the voltage controlled oscillating core operates into another one of the bands when the control voltage is out of the pre-set reference voltage range.

Abstract: A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block.

Abstract: A frequency generation unit (FGU) 100 includes a plurality of selectable voltage controlled oscillators (110) whose output frequencies are chosen in relationship with a predetermined intermediate frequency (IF) and frequency divider value (M) to provide multi-band frequency generation capability in a single communication device. A programmable reference divider (104), phase detector (174) and programmable charge pump (106) take an incoming reference frequency (120) and generate a charge pump output (124) to optimize the in-band phase noise in the FGU 100. A fixed loop filter (108) filters the charge pump output (124) to generate a control voltage (126) for the selectable VCOs (110). The desired frequency band is selected and enabled using control logic (128).

Abstract: The present invention relates to a two-frequency switchover type crystal oscillator in which first and second IC chips and first and second crystal resonators are connected to wiring patterns of a circuit substrate to form first and second oscillation circuits, and the first and second oscillation circuits are selectively operated in accordance with a selection mechanism; a two-frequency switchover type crystal oscillator in which surfaces opposite to circuit function surfaces of the first and second IC chips are connected to form a two-stage structure; IC terminals of the circuit function surface of the first IC chip are directly connected both electrically and mechanically to the wiring patterns; and IC terminals of the circuit function surface of the second IC chip are connected electrically by wire bonding to the wiring patterns; wherein those wiring patterns of the wiring patterns that are connected to power source, output, and ground terminals of the first and second IC chips are connected in common wit

Abstract: A multi-band electronic apparatus and method thereof is provided. The method comprises outputting a first output signal in the first band by a first voltage controlled oscillator according to a switch control signal and a control voltage, outputting a second output signal in the second band by a second voltage controlled oscillator according to the switch control signal and the control voltage, the second band being not completely overlapped by the first band, performing frequency division selectively on the first output signal or the second frequency divided signal according to the switch control signal, and outputting a first frequency divided signal, determining a phase difference between the first frequency divided signal and a reference signal to output a phase difference signal, outputting the control voltage according to the phase difference signal, and selectively driving the first or the second voltage controlled oscillators by the control voltage according to the switch control signal.

Abstract: A clock selection circuit and synthesizer that is capable of selecting an optimum clock signal from among a plurality of clock signals in a short time. A reference-clock counter counts clock pulses in an inputted reference clock signal (REF). A clock counter counts clock pulses in one of the plurality of clock signals which is selected by a selection unit and frequency-divided by a frequency divider. An instruction-signal output unit outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit compares the count of the reference-clock counter and the count of the clock counter. The selection unit selects a clock signal by a binary search according to the result of the comparison.

Abstract: A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.

Abstract: A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is generated during a second period of a known duration. The duration of the first period is calculated based on the first count and the second count. A solid-state, thin-film battery is able to be used by virtue of low-current characteristics of the system, enabling extended shelf life for fuzing systems.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.

Abstract: Provided is an oscillating apparatus that includes a plurality of variable frequency oscillators, each of which is provided in correspondence with a different oscillating band from one another; and a selection section that selects an oscillating signal that is from a variable frequency oscillator provided in correspondence with a designated oscillating band, from among the plurality of variable frequency oscillators, and outputs the selected oscillating signal, where the selection section includes a plurality of selectors connected in a tree structure, each selector outputting a selected one of inputted two or more oscillating signals, and each of the plurality of variable frequency oscillators is connected to a selector positioned at an end of the tree structure of the plurality of selectors.

Abstract: Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

Abstract: A signal generator generates a first internal signal including frequency f1, a second internal signal including frequency f2, and a third internal signal including frequency f3 twice as high as frequency f2, and selects and delivers one from among a first output signal including frequency f1, a second output signal including frequency f1+f2, and a third output signal including frequency f1+f3, using the first, second, and third internal signals.

Abstract: A radiation hard design for oscillator circuits and circuits having differential outputs is described. The design includes connecting or otherwise coupling outputs of these circuits to a passive polyphase filter. The passive polyphase filter provides four quadrature outputs that are free of glitches that may have occurred at the filter input.

Abstract: Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).

Abstract: The present invention relates to a control method for the operation modes of an oscillator and the apparatus thereof, for which the method and the apparatus can be applied to the electronic circuits with multi-operation modes of the oscillator so as to correctly choose the desirable oscillator operation mode. Furthermore, an oscillator checking circuit sets up the oscillation mode automatically and judges if the oscillator operates properly. Hence, there is no need for the user to set up the oscillator operation mode manually.

Abstract: The object of the present invention is to provide a frequency-selective oscillator capable of outputting two frequencies without hindering the downsizing of the device and capable of obtaining good output voltage characteristics. The frequency-selective oscillator includes a first crystal resonator and a second crystal resonator different in oscillation frequency from each other, and a first oscillation circuit and a second oscillation circuit corresponding to respective crystal resonators, in which a frequency-switching voltage is applied to selector terminals of the first and second oscillation circuits, a supply voltage Vcc is applied to a switching control terminal of the first oscillation circuit, a switching control terminal of the second oscillation circuit is grounded, Q outputs and inverted Q outputs of the oscillation circuits and are respectively connected and output from respective common signal lines.

Abstract: An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.

Abstract: A system comprises a primary oscillator that provides a first signal having a first phase and a backup oscillator that provides a second signal having a second phase. The system also comprises trim logic coupled to the backup oscillator logic. Prior to failure of the primary oscillator, the trim logic adjusts the second phase to match the first phase. Upon failure of the primary oscillator, the second signal is used in lieu of the first signal.

Abstract: An oscillator includes: oscillation units (11 through 1n) outputting oscillation signals of different frequencies; a transmission line (15) to which outputs of the oscillation units (11, 12) are connected, the transmission line having a characteristic impedance corresponding to an output impedance of an output terminal (Tout); and a low-pass filter 818) connected between the transmission line (15) and the output terminal.

Abstract: The present invention discloses a dual-band voltage controlled oscillator (VCO), comprising a plurality of resonant circuits; an inductor module; a plurality of switches of current source; a buffer circuit; and a output port. The dual-band voltage controlled oscillator (VCO) according to the invention uses the current source in such two VCOs with different resonant frequencies as the switch device to combine the two VCOs and uses the common inductor module for the two VCOs to save the chip size.

Abstract: A real time clock assembly includes paired crystal oscillators that experience changes in frequency responsive to temperature. The differences in frequency changes between the paired crystal oscillators are utilized to determine a temperature utilized to compensate for those shifts in frequency. The predictability of frequency responsive to temperature variations by the paired crystal oscillators is utilized for the determination of temperature.

Abstract: Various embodiments of the present invention provide systems, circuits and methods that allow for switching between two or more multiphase clocks. As one example, a system for switching between multiphase clocks is disclosed. The system includes a multiphase clock multiplexer. The multiphase clock multiplexer receives a first multiphase clock and a second multiphase clock. The first multiphase clock includes at least a first phase clock and a second phase clock, and the second multiphase clock includes at least a third phase clock and a fourth phase clock.

Abstract: The present invention discloses a frequency synthesizer, including: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, for selecting a specific clock signal from the clock signals as an output clock signal, wherein a specific frequency locking circuit of the frequency locking circuits locks the specific clock signal; and a control circuit, for controlling the frequency locking circuits. The control circuit controls at least one of the frequency locking circuits apart from the specific frequency locking circuit to lock another clock signal according to another reference clock signal at the same time. A related method for frequency synthesizing is also disclosed.

Abstract: A semiconductor integrated circuit device is disclosed that includes a signal processing unit having a nonvolatile memory and a detection unit; plural oscillation sources outputting plural oscillation signals; a selection control unit that selects one of the oscillation signals output by the oscillation sources according to a selection signal, and controls a transfer timing for transferring circuit setting information from the nonvolatile memory to the detection unit and an operations start timing for starting signal processing operations of the signal processing unit according to the selected oscillation signal.

Abstract: A multi-band VOC includes a plurality of oscillators, each oscillators having an oscillatory range respectively; a plurality of capacitor tanks is provided in each oscillators, and each capacitors is composed of a plurality of capacitors in series connection; a voltage detecting device is provided to detect a voltage signal, and to select an oscillator; one end of a logic controller is provided to electrically connect to the voltage detecting device, and another end is provided to electrically connect to the capacitor tank, which is provided a control signal to drive capacitance of the capacitor tank; and a multiple device is provided to output an oscillation frequency.

Abstract: A frequency jittering control circuit wherein by means of the characteristics of a PLL whose input switches between different frequencies, the output frequency of the PLL swings between the different frequencies to achieve the desired frequency jittering.

Abstract: Phase-locked loop (PLL) logic comprises an oscillator that produces a first oscillator signal and phase detect logic that determines a phase difference between the first oscillator signal and a second oscillator signal. After the second oscillator signal is replaced by a third oscillator signal, the phase detect logic determines another phase difference between the first oscillator signal and the third oscillator signal. The PLL removes the phase difference from the another phase difference to produce an intermediate signal. The oscillator adjusts the first oscillator signal using the intermediate signal.

Abstract: A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

Abstract: The present invention is an oscillator including: first transistors outputting oscillation signals of different oscillation frequencies to collectors; a common node to which outputs of emitters of the first transistors are connected and input; a feedback circuit feeding an output of the common node to bases of the first transistors; and isolation circuits that are respectively provided between the emitters of the first transistors and the common node and cut off high frequency components from the common node.

Abstract: A system and a method for operating the same. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached.

Abstract: A system comprises a primary oscillator that provides a first signal having a first phase and a backup oscillator that provides a second signal having a second phase. The system also comprises trim logic coupled to the backup oscillator logic. Prior to failure of the primary oscillator, the trim logic adjusts the second phase to match the first phase. Upon failure of the primary oscillator, the second signal is used in lieu of the first signal.

Abstract: Provided is an oscillating apparatus that includes a plurality of variable frequency oscillators, each of which is provided in correspondence with a different oscillating band from one another; and a selection section that selects an oscillating signal that is from a variable frequency oscillator provided in correspondence with a designated oscillating band, from among the plurality of variable frequency oscillators, and outputs the selected oscillating signal, where the selection section includes a plurality of selectors connected in a tree structure, each selector outputting a selected one of inputted two or more oscillating signals, and each of the plurality of variable frequency oscillators is connected to a selector positioned at an end of the tree structure of the plurality of selectors.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: A semiconductor memory apparatus includes a PLL selector that selectively activates a plurality of PLL enable signals by decoding pluralities of PLL selection signals, and a plurality of PLL circuits that connect to a plurality of PLL enable signals respectively, wherein when the one of a plurality of PLL enable signals is activated, the PLL circuit connected the activated PLL enable signal is operated to execute phase locking operations.

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract: A circuit for providing an A.C. signal including a number N of nanomagnetic oscillators, N being an integer greater than or equal to 2, each nanomagnetic oscillator providing a periodic signal; a unit for providing a control signal that can take N values, each periodic signal being associated with one of the values of the control signal; and a multiplexer receiving the N periodic signals and the control signal and providing the A.C. signal equal to one of the periodic signals according to the value of the control signal.

Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Abstract: In a high-frequency oscillator, a first resonance circuit and a second resonance circuit are respectively connected to a first amplifier circuit and a second amplifier circuit. A selection circuit includes a first switch circuit and a second switch circuit which selectively operate one of the first amplifier circuit and the second amplifier circuit. A grounded capacitor is connected to output sides of the first amplifier circuit and the second amplifier circuit. The grounded capacitor is commonly used by both the first amplifier circuit and the second amplifier circuit. An auxiliary grounded capacitor is connected between the first switch circuit and the first amplifier circuit. Accordingly, the grounded capacitor and the auxiliary grounded capacitor are connected to each other in parallel only when the first amplifier circuit is activated.

Abstract: This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to oscillator systems which employ a plurality of microelectromechanical resonating structures, and methods to control and/or operate same. The oscillator systems are configured to provide and/or generate one or more output signals having a predetermined frequency over temperature, for example, (1) an output signal having a substantially stable frequency over a given/predetermined range of operating temperatures, (2) an output signal having a frequency that is dependent on the operating temperature from which the operating temperature may be determined (for example, an estimated operating temperature based on a empirical data and/or a mathematical relationship), and/or (3) an output signal that is relatively stable over a range of temperatures (for example, a predetermined operating temperature range) and is “shaped” to have a desired turn-over frequency.

Abstract: Disclosed is a dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing. The dual-band voltage-controlled oscillator includes a power supply unit for supplying a source voltage; plural voltage-controlled oscillation units for outputting different oscillation frequencies according to controls of a certain tuning voltage; plural bias units for generating driving voltages for driving the voltage-controlled oscillation units and supplying the driving voltages to the voltage-controlled oscillation units; and plural buffers for selectively outputting oscillation frequencies of the plural voltage-controlled oscillation units. The present invention implements the dual-band voltage-controlled oscillator through bias switching and output-buffer multiplexing, which brings an advantage of elimination of interference between output frequencies to enhance phase noise characteristics.

Abstract: In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: A first receiver frequency reference is passively coupled to a second receiver by tapping a signal directly from the resonant element, such as a crystal, of an oscillator in the first receiver to drive the input of the second receiver. The sinusoidal signal from the resonant element is relatively free of harmonics and minimizes interference that could be caused by harmonics of a square wave signal coupling or an amplified signal. The oscillator of each receiver can be selectively enabled or disabled to allow the receiver to either generate or receive the frequency reference. This technique of coupling can be used to couple a frequency reference signal between integrated circuit receivers.

Abstract: A redundant clock source provides a stable clock source for digital system. The clock source uses two oscillators to generate a clock signal. If one of the oscillators fails, the clock signal is generated from the other oscillator until the failed oscillator is replaced. Special filtering of the waveforms produced by the oscillators makes the clock source is resistant to jitter from the oscillators and transients that occur when an oscillator fails. This allows the clock source to not only use a redundant oscillator in an attempt to eliminate a single point of failure, but to also provide a stable clock signal even if one oscillator fails.

Abstract: When two oscillation signals are output from a common terminal through switching, to reduce attenuation of the oscillation signals, a dual-band oscillator includes a first oscillating transistor for generating an oscillation signal in a first frequency band; a first inductor for supplying power to a collector of the first oscillating transistor; a first switching element for switching the first oscillating transistor; a second oscillating transistor for generating an oscillation signal in a second frequency band; a second inductor for supplying power to a collector of the second oscillating transistor; a second switching element for switching the second oscillating transistor; and an output terminal for outputting the oscillation signal in the first frequency band or in the second frequency band. The first switching element is disposed between the first inductor and the output terminal, and the second switching element is disposed between the second inductor and the output terminal.

Abstract: A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.

Abstract: An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.

Abstract: A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.