Abstract: A voltage controlled oscillation device includes a voltage controlled oscillator, fixed-frequency oscillator, frequency mixer, and frequency selector. The voltage controlled oscillator changes the output signal frequency in the microwave band in accordance with the input voltage of a frequency control signal. The fixed-frequency oscillator has a fixed oscillation frequency higher than that of the voltage controlled oscillator. The frequency mixer mixes the output signal from the fixed-frequency oscillator and the output signal from the voltage controlled oscillator and outputs the sum frequency and difference frequency between the two signals. The frequency selector selects and outputs one of the sum frequency and difference frequency contained in the output signal from the frequency mixer.

Abstract: A voltage-controlled oscillator is constructed to greatly reduce the number of parts required, its overall size, and manufacturing cost. The voltage-controlled oscillator includes first and second resonance circuits, first and second oscillation circuits, a buffer circuit amplifying the oscillation signals output from the first and second oscillation circuits, and an output-matching circuit. In addition, the voltage-controlled oscillator includes a first switching circuit for controlling the oscillation of the first oscillation circuit and a second switching circuit for controlling the oscillation of the second oscillation circuit. The impedance changing of the matching circuit is simultaneously performed while switching between the switching circuits.

Abstract: A multi-octave, wideband voltage controlled oscillator has a plurality of high impedance current output individual voltage controlled oscillators coupled in parallel to form a bank of voltage controlled oscillators covering at least one high frequency octave. The outputs of the VCOs are wire-OR'd together and the VCOs are selected by a select signal that turns on the desired oscillator(s). A main limiter/divider selects a frequency octave at either the fundamental frequency of the selected VCO or a sub-harmonic thereof as the multi-octave, wideband voltage controlled oscillator output. A reference limiter/divider selects a reference frequency from the selected VCO for use in a phase locked loop. Each VCO has a tank circuit coupled across the bases of a pair of transistors, the emitters of which are coupled through respective current sources to ground. The collectors of the transistors are coupled to the wire-OR'd network.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: An input change-over amplifier is capable of effecting a change-over in outputting two signals having different frequencies, without lowering the signal levels thereof. Two signals having different frequencies are fed into two input terminals of an amplifying element. When a signal is input through one input terminal, the other input terminal is grounded. When a signal is input through the other input terminal, the above one input terminal is grounded. In this way, it is possible to effect a change-over in outputting two signals having different frequencies, without lowering the signal levels thereof. Further, since two signals can be fed into an amplifying element through different paths, it is not necessary to provide a matching circuit at a connection point of signal paths. Therefore, the number of required electronic parts can be reduced, an oscillator which is compact in size can be manufactured, and a necessary circuit can be designed within only a short time.

Abstract: The frequency-characteristic switchable buffer circuit includes an amplifying stage, a parallel resonance circuit which serves as an output load of the amplifying stage, a frequency trap circuit electrically connected between the input of the amplifying stage and a reference potential point, and a frequency switching voltage generator for selectively generating a first switching voltage or a second switching voltage. The parallel resonance circuit parallel-resonates at a first frequency when the first switching voltage is supplied thereto. When the second switching voltage is supplied thereto, the parallel resonance circuit parallel-resonates at a second frequency. The frequency trap circuit comprises a series circuit made up of a diode and a capacitor. When the first switching voltage is supplied to the frequency trap circuit, the frequency trap circuit series-resonates at a frequency lower than the first frequency.

Abstract: In a clock control circuit, a multiplication factor setting unit outputs a multiplication factor. A buffer circuit holds a previous multiplication factor and the multiplication factor output by the multiplication factor setting unit and compares the two multiplication factors. When the multiplication factors are different from each other, a clock state control circuit provides a control to, stop the output of clock to the outside, switch the clock to a clock other than those output by the PLL oscillation circuit, change the multiplication factor in the PLL oscillation circuit, switch the clock to clock output by the PLL oscillation circuit after the PLL output clock is stabilized, and restart output of the clock to the outside.

Abstract: A high-speed power-efficient coded M-ary Frequency-Shift Keying (M-ary FSK) modulator. The modulator includes a coding logic, which generates (M/2) Gray code signals in accordance with an (N−1) bits control signal; and (M/2) switching oscillators. Each switching oscillator includes: a composite crystal resonator with a first end and a second end; a first switch, which is controlled by Gray code signals, with one end connected to the first end of the composite crystal resonator, and the other end grounded via an equivalent negative resistance circuit; a second switch, which is controlled by serial data, with one end connected to the second end of the composite crystal resonator, and the other end grounded; and a capacitor, with one end connected to the second end of the composite crystal resonator, and the other end grounded.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator, caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, wireless communication frequency synthesizer for generating multiple band high-frequency signals is disclosed having a first VCO selectable for a first frequency band and a second VCO selectable for a second frequency band.

Abstract: In a three-band switching oscillator, a switching circuit is provided to switch the operating conditions of first and second voltage-controlled oscillator and to switching an oscillation frequency band of said first voltage-controlled oscillator, and is composed of a first switch for supplying a current to place the first voltage-controlled oscillator into operation, a second switch for supplying a current to place the second voltage-controlled oscillator into operation, and first and second switching terminals for receiving switching voltages.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, wireless communication frequency synthesizer for generating multiple band high-frequency signals is disclosed having a first VCO selectable for a first frequency band and a second VCO selectable for a second frequency band.

Abstract: A selectable oscillation circuit includes a first oscillation circuit, a second oscillation circuit, and a selector circuit. The selector circuit selectively switches on and off the first oscillation circuit and the second oscillation circuit, in accordance with the provision of a selector signal, to selectively switch between two communicating modes, with low-power consumption.

Abstract: The present invention is a novel method and apparatus for implementing a high-precision timer utilizing a non-optimal oscillator and a high-speed oscillator wherein only one oscillator is enabled at a given moment in time. The high-precision timer method and apparatus comprises a timer and an error-correction technique. In one embodiment, the timer of the present invention is constructed from a high-speed oscillator and a low-speed non-optimal oscillator. The timer operates from the high-speed oscillator during on-the-air modes of operation and from the low-speed non-optimal oscillator during sleep modes of operation. The present inventive method corrects errors that are introduced by the non-optimal oscillator and a swallow counter. The errors are corrected using an error-correction technique having two steps: an error-determination step and an error-correction step.

Abstract: The two-band oscillating apparatus of the present invention comprises in one aspect a first oscillator for outputting an oscillation signal of a first frequency band, a second oscillator for outputting an oscillation signal of a second frequency band which is higher than the first frequency band, and a grounded-emitter type amplifier including an amplifying transistor to amplify the oscillation signal of the first frequency band or the oscillation signal of the second frequency band. In this structure, an emitter bias resistor is connected between the emitter of the amplifying transistor and the ground. A first series resonance device which resonates in almost the first frequency band, and a second series resonance device which resonates in almost second frequency band, are connected between the emitter and ground. Thereby, the number of parts can be reduced through simplified structure.

Abstract: A switch-type oscillating circuit includes a first oscillating circuit for outputting an oscillation signal having a first frequency, which includes a first oscillation transistor and a first switch circuit for turning on and off the first oscillation transistor; a second oscillating circuit for outputting an oscillation signal having a second frequency, which includes a second oscillation transistor and a second switch circuit for turning on and off the second oscillation transistor; and a coupling circuit disposed between the output end of the first oscillating circuit and the output end of the second oscillating circuit, and the input end of a common circuit.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator. caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: A voltage-controlled oscillator is constructed to greatly reduce the number of parts required, its overall size, and manufacturing cost. The voltage-controlled oscillator includes first and second resonance circuits, first and second oscillation circuits, a buffer circuit amplifying the oscillation signals output from the first and second oscillation circuits, and an output-matching circuit. In addition, the voltage-controlled oscillator includes a first switching circuit for controlling the oscillation of the first oscillation circuit and a second switching circuit for controlling the oscillation of the second oscillation circuit. The impedance changing of the matching circuit is simultaneously performed while switching between the switching circuits.

Abstract: A reference-frequency-signal switching circuit includes an internal reference-frequency-signal oscillator for generating an internal reference-frequency signal, a reference-frequency-signal input terminal to which an external reference-frequency signal is input, a reference-frequency-signal output terminal, and a reference-frequency-signal output switching section.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: Voltage controlled oscillator assembly comprising means for detecting a control voltage input and means for generating an output frequency signal depending on said control voltage input. Said voltage controlled oscillator assembly comprises at least two voltage controlled oscillators, means for reading data from an external source, and means for individually switching the at least two voltage controlled oscillators on and off in accordance with the data read.

Abstract: Apparatus for clock signals distribution with continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU. Switching is transparent to load circuits which utilize these clock signals, by continuously keeping the output clock signals in the CDU and the redundant CDU frequency and phase coherent, by generating each output clock signal from a reference signal, using an adaptive PLL circuitry at each CDU, and pre-adjusting the phase of each output clock signal of the redundant CDU to the corresponding output clock signal of the CDU. In the event of a failure in the CDU, the output is taken from the redundant CDU immediately after failure detection. The phase of the reference frequency output clock signal of the standby CDU module is adjusted to the phase of the active CDU module by adding or subtracting an input signal to the phase error signal, which is generated in a PLL circuitry of the redundant CDU module.

Abstract: A method and apparatus for providing very small changes in the output oscillation of a controlled oscillation circuit, which may be used in a phase locked loop circuit, is accomplished by a phase-shifting controlled oscillator that includes an oscillation circuit and a selection circuit. The oscillation circuit generates a plurality of oscillations that are of approximately the same frequency and are approximately equally phase shifted from one another. The selection circuit is operably coupled to receive the plurality of oscillations and selects one of them to be the output oscillation based on a control signal. The very small change in the output oscillation occurs when the selection circuit, based on the control signal, selects another one of the oscillations to be the output oscillation. When the change happens, a single pulse is stretched by the phase difference between the “old” output oscillation and the “new” output oscillation.

Abstract: A system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. The master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide a control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. The first clock source may be on a first clock board, and the second clock source may be on a second clock board. The clock boards are preferably hot swappable. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system.

Abstract: A VCO has n inverters connected to each other in a ring, wherein the inverters have a depletion-mode FET. A selector control circuit produces a select signal based upon a threshold voltage of a selector depletion-mode FET to select one of an output derived from a (n−i)-th inverter, or another output signal derived from the n-th inverter. Because the selector FET and the inverter FETs are made using the same process steps and thus have the same device parameters, the selector FET has the same threshold voltage variation as the inverter FETs. Based upon the variation in the FET threshold voltage, the selected output is provided to an input of a first inverter. The VCO operates at a constant frequency by changing the total number of inverters in the ring to compensate for the variation in the threshold voltage of the depletion-mode FETs in the inverters, as determined by the depletion-mode FET in the selector circuit.

Abstract: A frequency-providing circuit is disclosed for providing an output signal at a frequency fout. The circuit comprises a frequency-generating unit, a frequency-changing circuit, and a synchronizing circuit. The frequency-generating unit receives a frequency-selecting control signal and provides a frequency output at a frequency fosc, whereby the frequency-generating unit is switchable between different frequencies substantially without a settling time. The frequency-changing circuit receives the frequency output and a frequency-changing control signal and derives the output signal therefrom, whereby the frequency fout of the output signal can be changed, with respect to the frequency fosc, in accordance with the setting of the frequency-changing control signal. The synchronizing circuit synchronizes the frequency-selecting control signal and the frequency-changing control signal.

Abstract: A programmable multi-scheme clocking circuit supports multiple applications. In one implementation, the clocking circuit includes multiple clock sources such as a crystal oscillator, a RC oscillator, an internal oscillator, and an external clock. Each of the clock sources can be enabled by a respective control signal. A multiplexer couples to the clock sources and provides a clock signal from one of the clock sources as the output clock signal. External support circuitry (e.g., external tank circuits) for some of the clock sources (e.g., the crystal oscillator and the RC oscillator) can be coupled to the clocking circuit through one or more device pins. The pins to support the crystal oscillator, the RC oscillator, and the external clock signal are shared so that no additional device pins are required.

Abstract: A clock circuit includes a clock signal generator for generating a first clock signal during a normal mode of operation and an oscillating dual clock generating circuit for producing a second clock signal during a second mode of operation. The oscillating dual clock generating circuit is connected to the output of the clock signal generator. In the first mode of operation, the clock signal from the clock signal generator is passed through the oscillating dual clock generating circuit to a control device. In a second mode of operation, the input of the oscillating research signal is isolated. Isolation of the oscillating dual clock generating circuit causes oscillation in the dual clock generating circuit. Thus, the dual clock generating circuit acts as an oscillator during the second mode of operation to generate a second clock signal.

Abstract: A quenchable VCO that is adapted to be used in switched band synthesizer applications. The VCO may be formed from a heterojunction bipolar transistor (HBT) in a common collector configuration. A quenching circuit which includes a p-i-n diode, is electrically coupled in series with the collector of the HBT. The p-i-n diode is adapted to be monolithically integrated with the HBT. Since the p-i-n diode is electrically connected to the collector of the HBT, as opposed to the base and emitter terminals of the HBT, which forms the main oscillator feedback loop, the Q-factor of the p-i-n diode will have relatively less loading on the phase noise of the HBT oscillator. Moreover, since the p-i-n diode is isolated from the base-emitter junction, the configuration will result in reduced frequency pulling and generation of spurious oscillation and transient effects due to the switching of the p-i-n diode quenched circuit.

Abstract: An oscillator having two oscillation circuits with widely different frequencies with a common passive switched output circuit. Each oscillator circuit includes a transmission line inductive impedance between the oscillator output and ground. The inductive impedances are selected to be open at the operating frequency of the associated oscillator circuit and a short or a low impedance at the frequency of the other oscillator circuit. Each inductive impedance forms a portion of an impedance matching pad for the other oscillator circuit.

Abstract: An integrated, crystalless oscillator includes a voltage controlled oscillator circuit for generating an output signal, and a frequency-locked feedback network to stabilize the frequency of the output signal. The frequency-locked feedback network includes a divide-down circuit and a frequency-controlled variable resistor, the divide-down circuit divides down the frequency of the output signal to produce a feedback frequency which is used to control the frequency-controlled variable resistor. The control voltage for the voltage controlled oscillator circuit is derived from the voltages across a fixed resistor and the frequency-controlled variable resistor. The voltages across these resistors drive an amplifier, with the output of the amplifier being the control voltage for the voltage controlled oscillator circuit.

Abstract: A circuit for synchronizing transmission local oscillating frequency in a co-channel microwave system, with more reliability, synchronizes horizontal and vertical polarization waves phase locked dielectric resonators which generate transmission local oscillating frequencies in a digital co-channel microwave system.

Abstract: A voltage controlled oscillator comprises first oscillating stage for outputting a first frequency signal, second oscillating stage for outputting a second frequency signal different from the first frequency signal, a buffer stage connected with said first and second oscillating stages, the buffer stage receiving said first and second frequency signals to generate an output signal.

Abstract: A monolithic oscillator having dual programmable fixed frequency outputs includes crystal-less oscillator circuitry utilizing frequency-locked feedback to generate ai signal having a select frequency, the frequency being stabilized over temperature and voltage by compensation circuitry associated with the crystal-less oscillator circuitry. A programmable prescaler is coupled to the crystal-less oscillator circuitry for varying the frequency of the signal generated by the crystal-less oscillator circuitry by a select amount. The monolithic oscillator further includes inputs for receiving an external signal, such as an external reference signal, or for connection to a crystal for providing an alternative frequency reference. A multiplexer is used to select either the external signal (or crystal) or the signal from the crystal-less oscillator circuitry to be used for the output signal.

Abstract: A system clock signal switching device capable of switching outputs from a plurality of clock signal generation systems i order to ensure the continuous supply of a stable system clock signal. An oscillation circuit A generates a clock signal CK1 as an ordinary system clock signal while an oscillation circuit B generates a clock signal CK2 as another separate clock signal, such as the time-count clock signal. The output lines of these circuits are connected with the input terminals of a multiplexer. An output clock signal monitor circuit checks the clock signal CK1 from the oscillation circuit A, wherein input terminals of the monitor are connected with the output lines to attain the operational clock signals for its monitoring operation. A monitor flag from the monitor circuit is supplied to a switching signal input terminal of the multiplexer via a line.

Abstract: A pulse-width modulation signal generator having a pre-phase converter which includes N pre-delay circuits connected in cascade, and N main phase converters each of which includes M main delay circuits, where N and M are natural numbers greater than one, and N>M. The output of each of the N pre-phase circuits is supplied to one of the N main phase converters to generate phase converted clock signals used for generating a pulse-width modulation signal.

Abstract: An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

Abstract: A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.

Abstract: Oscillating circuitry built in integrated circuitry (1) comprises a ring oscillator (31) for generating a first clock, an external oscillator (40) capable of generating a second clock in either one of two oscillating modes which is determined according to an external circuit (12 and 13, or 6 through 8) connected to terminals (2 and 3) thereof, and an internal clock selection circuit (41) which delivers the first clock as an internal clock to the integrated circuitry (1) just after the integrated circuitry (1) is activated or reset, stops the delivery of the first clock and simultaneously furnishes a signal held at a logic high level as the internal clock in response to a control signal for instructing a selection of the second clock, and then determines whether or not the external oscillator (40) is generating the second clock properly, and which furnishes the second clock as the internal clock when it determines that the external oscillator (40) is generating the second clock properly.

Abstract: A clock multiplexer including a plurality of clock selection circuits. Each clock selection circuit determines if a clock input is selected and provides the clock input to a clock output based on the determination. Each clock selection circuit further includes deselect inputs, and a select input which is coupled to a deselect output, the deselect output providing a signal indicating if the select input is active. Each deselect input is connected to a respective one of the deselect outputs from the other clock selection circuits. In each clock selection circuit, the clock input is not provided to the clock output when one of the deselect inputs is active.

Abstract: A voltage controlled oscillator (10) operable on two widely separated frequency bands of 800 MHz and 1.9 GHz, for example. The two operable frequency modes are controlled by changing base bias voltages on at least two transistors with commonly connected emitters. A base circuit of each transistor is connected to an independent resonator and tuning element and shares a common feedback reactance. By increasing a base bias voltage of first transistor relative the a second transistor, an associated first base circuit is turned on and allowed to oscillate at a first frequency while a second base circuit is turned off preventing oscillation at a second frequency. Correspondingly, by decreasing the base bias voltage the first base circuit is turned off and the second base circuit is turned on. The transistors share a common collector connection and output providing either one of the two frequencies.

Abstract: A method and apparatus for generating a finely adjustable clock is accomplished by a ring oscillator, a plurality of counting circuits, and a controller. The ring oscillator generates a plurality of oscillations, wherein each of the oscillations have an approximately equal period and are phase shifted by an approximately equal phase shift. Each of the plurality of oscillations is provided to one of the counting circuits which divides the frequency of the respective oscillation by a given count value to produce corresponding periodic representation. The controller selects one of the corresponding periodic representations based on control signal to be the output oscillation, or clock signal. When the clock signal needs to be finely adjusted, the controller, based on the control signal, selects another one of the corresponding periodic representations.

Abstract: A dual band oscillator circuit according to the present invention comprises an oscillator circuit portion that oscillates at a first frequency, an oscillator circuit portion that oscillates at a second frequency, a buffer amplifier circuit portion to which an output of the first oscillator circuit portion is input through a first stage-to-stage coupling element and an output of the second oscillator circuit portion is input through a second stage-to-stage coupling element. Operation is switched between the first and second oscillator circuits by an externally applied control voltage signal.

Abstract: An oscillating device is disclosed including a first ring oscillator having at least three odd inverters connected in series, an input terminal of the first of the inverters being connected with an output terminal of the last of the inverters, and applying an output signal of the last inverter to a first buffer's input terminal, thus producing a signal of the first cycle; the first buffer connected with the output terminal of the first ring oscillator's last inverter, having at least two even inverters connected in series, and buffering an output signal of the last inverter to produce it to outside; a second ring oscillator having at least three odd delay devices connected in series, wherein a power supply of each delay device is connected with the output terminal of each of the first ring oscillator's corresponding inverters, and an output terminal of the last of the delay devices is connected with an input terminal of the first of the delay devices, thus producing a signal of the second cycle, larger than t

Abstract: An integrated oscillation circuit used for frequency conversion circuit in which UHF frequency conversion and VHF frequency conversion are selectively energized to use a common IF amplifier. The integrated oscillation circuit is used for a local oscillation circuit. The integrated oscillation circuit including a connection terminal connected to an external resonance circuit and an input line of a mode switching signal which is set at a different level in response to an operation mode, an oscillation element, a bias terminal of which is connected to the connection terminal, a detection circuit detecting the level of the mode switching signal applied to the bias terminal of the oscillation element, and a switching circuit turning on and off a power source for driving the oscillation element in response to the level detected at the detection circuit.

Abstract: A method and apparatus for recovering the time base of signals which change at periodic intervals is disclosed. The apparatus comprises gated voltage controlled oscillators (GVCO) that are alternated or exchanged, to reduce phase and frequency deviations in the recovered time base signal, such as the deviations induced by inherent GVCO differences. Each GVCO is stabilized by a respective phase locked loop. The respective GVCOs are gated only in response to a chosen polarity transition in the input signal, to make the circuit more tolerant of waveform distortions. More than two GVCOs may be used to provide improved frequency drift resistance. The circuit uses resynchronization control signals, such as the time slot signal in synchronous switching systems, to indicate resynchronization or reassignment of the GVCOs in gaps in the data transmission.

Abstract: A voltage controlled oscillator operable on two widely separated frequency bands, such as 900 MHz and 1.8 GHz for example. The voltage controlled oscillator includes two negative resistance generators (32, 34) which share a common tunable tank circuit (26) and a common impedance matched combiner circuit (28) which provides the RF output (36). The VCO uses only one varactor (30) to tune both frequency bands. Separate negative resistance generators (32, 34) are used to provide optimum frequency selectivity within each frequency band.

Abstract: A circuit for automatically substituting a reference oscillator for synchronizing two transmitter co-channel local oscillators. The circuit includes a first bias switching device for switching a first power supply to a first reference oscillator and a second bias switching device for switching a second power supply to a second reference oscillator. The first and second reference oscillators generate first and second reference signals for synchronizing the oscillator frequencies. A first divider firstly and secondly divides and outputs the power of the first reference signal. A second divider firstly and secondly divides and outputs the power of the second reference signal. A first combining device inputs the power of the firstly-divided first reference signal and the secondly-divided second reference signal and outputs the power to the phase locked dielectric resonator oscillator for the vertical polarization wave.

Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.

Abstract: A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.