Abstract: A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.

Abstract: The present invention provides a semiconductor device wherein the oscillation of a clock signal oscillation circuit is halted by control carried out by a CPU when a clock-signal switching circuit selects either a clock signal generated by a CR oscillation circuit or a clock signal generated by an oscillator-driven oscillation circuit. A frequency divider divides the frequency of a clock signal generated by the clock signal oscillation circuit, supplying a clock signal with a divided frequency to the clock-signal switching circuit.

Abstract: A multiple-frequency local oscillator for providing an LO signal at one of a multiple of predetermined resonant frequencies associated with a number of resonators is disclosed. It includes a number of LO input ports for coupling to a plurality of resonators, respectively, each resonator having a predetermined resonant frequency; the local oscillator is controlled to selectively provide at its LO output port an output LO signal at any one of the resonant frequencies.

Abstract: A clock supply apparatus contains: a clock generating unit for generating a clock signal; a phase comparing unit for inputting a reference clock signal, and obtaining a phase difference between the reference clock signal and the clock signal generated by the clock generating unit; a frequency control unit for generating a control signal for controlling the frequency of the clock signal generated by the clock generating unit, based on the phase difference; a clock preciseness monitoring unit for monitoring preciseness of the clock signal, based on the phase difference; and a clock preciseness output unit for outputting information indicating the preciseness of the clock signal, based on the phase difference.

Abstract: The phase locked loop (PLL) control apparatus includes a selector which selects input signals, for an active system and a standby system having a clock signal and a frame pulse signal synchronized with the clock signal, by means of a line switching signal. The phase difference between the frame pulses before and after the line switching is output by a frame pulse phase comparator. On the other hand, accompanying the line switching, a frequency divided clock output from a frequency divider is branched in a PLL control circuit which carries out the phase matching of the clocks. The branched clock is converted to pseudo clocks with duty factors larger than and smaller than 50% by a duty factor controller. A clock selector which selects one out of the frequency divided clock and the pseudo clock in response to the phase difference of the frame pulses is installed between a clock phase comparator and a low-pass filter of the PLL control circuit.

Abstract: An electronic audio circuit operates a piezoelectric audio transducer to produce a two-tone warbling audio output. The electronic circuit includes an integrated circuit double timer and integrated circuit logic gates. One timer produces a toggling frequency that operates a toggling circuit composed of a logic gate to electrically connect and disconnect an electrical component from a frequency determining network to produce two frequency determining networks. The other timer produces two tones depending upon which frequency determining network is electrically connected to the other timer. The two tone are buffered and then drive a two-element piezoelectric transducer.

Abstract: An oscillator is provided having a plurality of cascade coupled inverters Each one of the inverters is a differential amplifier having a p-input and an n-input. The output of each one of the amplifiers is connected to: the n-input of the next succeeding amplifier to provide a closed loop, or ring oscillator; and, the p-input of an amplifier positioned an even number of amplifier stages forward of such next succeeding amplifier. In a preferred embodiment, each amplifier in the ring includes an n channel transistor (nMOS transistor) connected in a totem pole arrangement, to a p channel transistor (pMOS transistor). The gate of the nMOS transistor provides the n-input and gate of the pMOS transistor provides the p-input. The source and drain paths of the pMOS and nMOS transistors are connected together to provide an output for the amplifier.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.

Abstract: A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked.

Abstract: A fail-safe clock generator which has particular utility in implantable cardiac defibrillators includes a crystal oscillator for generating a crystal clock signal, a back-up circuit, and a one-shot generator. The back-up circuit includes a low frequency oscillator for generating a low frequency clock signal having a frequency less than that of the crystal clock signal, and an overspeed/underspeed detector responsive to the low frequency clock signal for detecting the frequency of the crystal clock signal during each period of the low frequency clock signal, and for generating a back-up mode control signal in response to detection of either an overspeed or underspeed failure mode over a plurality of consecutive periods of the low frequency clock signal.

Abstract: A processor (PR) is connected to the output of a phase comparator (PK) in a phase-locked loop. The processor (PR) calculates the phase shift of an input signal (f.sub.E) within an observation time span (for example, .DELTA.t=0-T) from the phase difference (.DELTA..phi.) at the output of the phase comparator (PK) and the parameters of the phase-locked loop (FT1, PK, FI, VCO, FT2).

Abstract: A first oscillator includes: a ring resonator; an oscillation circuit having a negative resistance active circuit coupled to a first point on the ring resonator for oscillating at an oscillation frequency and resonating the resonator; an output terminal, coupled to a second point on the ring resonator where a voltage is substantially zero with respect to the predetermined frequency when the ring resonator resonates, for outputting a resonant frequency signal, wherein even order harmonic components are outputted with the fundamental component suppressed. A second oscillator includes a ring resonator having points A to D equidistantly dividing the ring resonator, first and second oscillation circuits coupled to the points A and B respectively, first and second grounding capacitors having capacitance equivalent to those of the first and second oscillation circuits. Thus, two independent oscillators which do not affect each other are provided with a single resonator.

Abstract: A phase-looked loop circuit with holdover mode is formed utilizing a primary and secondary phase-locked loop circuits. Each loop circuit comprises a phase detector, loop filter, VCXO and frequency divider. The secondary loop is configured such that its output is very stable. The primary loop is phase-locked on a received reference clock signal and the second loop is phase locked on the output of the primary loop. The scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched to a holdover mode where the input of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-looked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back to the reference clock signal.

Abstract: A duplexed clock switching apparatus of the present invention includes two oscillators constantly working for outputting clock signals, wherein a phase of the stand-by clock signal is kept synchronized to the phase of the clock signal selected from the output signal of the oscillator to be supplied to the apparatus. Each of the duplexed clock switching apparatus of the present invention includes a clock signal generator for generating clock signals of a predetermined frequency independently; a clock selector for receiving clock signals generated by all clock signal generators and selecting one of them; a phase synchronization circuit for synchronizing a phase of a clock signal generated by the clock signal generator to the phase of the selected clock signal; and a clock switching circuit for switching an outputted clock signal to the selected clock signal. With reference to the phase synchronization circuit, it is desirable to include a phase-locked-loop (PLL) circuit.

Abstract: To ensure error-free transmission of digital information, very stringent requirements are placed on the accuracy and stability of the clock generators. It is known to use microprocessor-controlled digital phase-locked loops for this purpose, which contain costly high-stability crystal oscillators. An accurate system clock signal is to be provided even if the reference clock signal fails. Contradictory requirements are placed on the phase-locked loops, namely, on the one hand, a wide bandwidth to achieve a small time interval error, and, on the other hand, a narrow bandwidth to minimize the effect of jitter and wander on clock accuracy if the reference clock signal should fail. The invention provides a circuit arrangement for a low-cost clock generator which generates a highly accurate clock frequency even in the event of a failure of the reference clock signal.

Abstract: An integrated oscillation circuit used for frequency conversion circuit in which UHF frequency conversion and VHF frequency conversion are selectively energized to use a common IF amplifier. The integrated oscillation circuit is used for a local oscillation circuit. The integrated oscillation circuit including a connection terminal connected to an external resonance circuit and an input line of a mode switching signal which is set at a different level in response to an operation mode, an oscillation element, a bias terminal of which is connected to the connection terminal, a detection circuit detecting the level of the mode switching signal applied to the bias terminal of the oscillation element, and a switching circuit turning on and off a power source for driving the oscillation element in response to the level detected at the detection circuit.

Abstract: A local oscillator system carries out a frequency switching method, in which local signals with fewer spurious components can be obtained. The local oscillator system is provided with frequency generators for generating signals with different frequencies and frequency dividers connected to the frequency generators. The dividers divide the frequency of the signals to output the frequency-divided signals while operating in an active mode and output undivided signals while the dividers are operating in inactive mode. The dividers are controlled so that one of the dividers is in the active mode and the remaining dividers are in the inactive mode. The output signals from the dividers are combined with each other to form a single output signal and then the single output signal is sent to a filter. The filter selects a component having a desired local frequency from the single output signal. Spurious components caused by unselected frequencies are removed by the filter because they are not divided.

Abstract: Disclosed herein is an oscillator circuit generating an oscillation signal in response to a resonant element in a first mode and to an external clock signal in a second mode. This oscillator circuit comprises a tri-state inverter circuit and a transfer circuit between the input and output nodes of the tri-state inverter circuit, and the output node of the tri-state inverter circuit is brought into a high impedance condition when an external clock signal is used and into an active state when the resonant element is employed.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window. In one embodiment of the invention, accumulated error is stored in an integrator device while in another embodiment accumulated error is stored in the phase of a bi-frequency oscillator.

Abstract: An FSK modulating apparatus includes a first phase locked loop arrangement having a first voltage controlled oscillator for generating a space frequency signal of a modulation signal and a second phase locked loop arrangement having a second voltage controlled oscillator for generating a mark frequency signal of the modulation signal. The apparatus also includes a third voltage controlled oscillator used to produce an FSK modulated output signal. After input data changes frequency to a space frequency or a mark frequency, a control voltage for the phase locked loop arrangement that is associated with the resulting frequency is routed through a low pass filter having a flat group delay characteristic to the third voltage controlled oscillator. After a set period of time has elapsed, the third voltage controlled oscillator replaces the voltage controlled oscillator of the particular phase locked loop arrangement associated with the current state of the modulator signal.

Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop.

Abstract: A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Abstract: A clock pulse generator has a three-state inverter and a transfer gate forming in combination a feedback loop for oscillating an output clock signal in cooperation with a quartz resonator in an internal oscillation mode, and the three-state inverter enters into high-impedance state in an external oscillation mode so that an external clock signal is transferred to the output node of the three-state inverter without malfunction.

Abstract: A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.

Abstract: An oscillator unit with improved frequency stability, including at least three oscillators having the same nominal frequency. A selector is provided for selecting one of the oscillators (1, 2, 3) for connection to an output (14a) of the oscillator unit. The oscillator frequencies are compared in pairs with each other. The selector is controlled by a controller to replace the oscillator connected to the output of the oscillator unit with another oscillator if the frequency of the oscillator currently connected to the output deviates from the frequencies of the other oscillators by at least as much as a predetermined frequency difference.

Abstract: A digital frequency generating device is comprised of a first digital frequency generator which generates a first output signal at a first frequency and a second digital frequency generator which generates a second output signal at a second frequency independent of the first frequency. Both the first and the second frequency generators run continuously and either can be connected to the generating device output by means of a multiplexer. Apparatus is provided to synchronize the two generators so that a continuous phase transition is maintained when the generating device output switches from the first output signal to the second output signal. This arrangement allows the device output to be shifted from a first frequency to a second frequency and then return to the first frequency output while maintaining the phase position of the first frequency output and is particularly useful in nuclear magnetic resonance applications.

Abstract: The assembly comprises an electrically insulated linear array of a plurality of active plates working in conjunction with common return plate means to provide a line of capacitors. The electrically insulated active plate array and common return plate means extend through a column of multi-phase fluid. A discrete oscillator circuit is positioned adjacent to and is permanently connected to each active plate for charging and discharging it. Means are provided for sequentially enabling the oscillator circuits to produce signals which are each indicative of the dielectric constant of the thin horizontal slice of fluid extending between the active plate and the return plate means. The signals are collected by a microprocessor which analyzes them to provide a dielectric constant profile of the fluid column. Interfaces of phases can be located from the profile and the composition of the fluid phases can be determined.

Abstract: The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.

Abstract: A method and apparatus for controlling the phase of a system clock, in which one of a first clock signal and a second clock signal is selected and output to a system as a system clock signal, the first clock signal being generated by a frequency synthesizer synchronized with an external clock signal supplied from a reference clock signal oscillator provided externally of the system, and the second clock signal being supplied from another reference clock signal oscillator provided internally of the system, and the phases of the first and second clock signals are controlled, prior to switching between the first and second clock signals and supplying the switched clock signal to the system as the system clock signal. The switching is delayed for a period while there is a phase shift between the first and second clock signal , when the system clock signal is switched between the first and second clock signal.

Abstract: A digital computer is provided having a clock generation circuit for generating a clock signal in response to an input signal from a fixed-frequency oscillator, which includes a first fixed-frequency oscillator and a second fixed-frequency oscillator, each providing an output signal. Also included is failure detection circuit for detecting a failure of either of the fixed-frequency oscillators, wherein a failure occurs when the first fixed-frequency oscillator or the second fixed-frequency oscillator ceases generating an output. A circuit synchronizing the output from the oscillators is coupled to both the first fixed-frequency oscillator and to the second fixed-frequency oscillator. This synchronizing circuit modifies the output from the second fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with the output from the first fixed frequency oscillator.

Abstract: A self-configurable clock circuit which automatically detects at power up whether an off-chip crystal oscillator is connected to an integrated circuit including the self-configurable clock circuit, and following such detection generates a system clock signal and a power on reset signal to be used by other circuitry included in the integrated circuit. If the off-chip crystal oscillator is connected to the integrated circuit, then the self-configurable clock circuit provides the system clock signal from a first signal generated from the off-chip crystal oscillator. On the other hand, if the off-chip crystal oscillator is not connected to the integrated circuit, then the self-configurable clock circuit provides the system clock signal from a second signal generated from an on-chip RC oscillator circuit.

Abstract: An electrically controlled oscillator circuit having multi-phase outputs with programmable frequency. The circuit includes a ring oscillator having a plurality of inverting stages. Each stage has an output which is connected to a switch that can be programmed to select one of a plurality of capacitors with different values to change the frequency range of the oscillator. Controlled current is fed to the stages to vary the frequency of the oscillator within a selected frequency range. Using capacitors to change the frequency range of the oscillator reduces variations of the oscillator output frequency.

Abstract: A variable reluctance transducer system incorporating digital control of parallel resonant circuits including two inductive sensors L1 and L2 on each side of a flat diaphram. The dual variable reluctance elements provide dual frequency signals for digital calculation to obtain a quotient of the frequencies, thereby substantially eliminating the resonant frequencies as a variable in the accuracy of the device. Manipulation of the produced quotient by a micro-controller 10 employing digital calibration tables stored in a programmable read only memory 14 allows calibration reponsive to a temperature sensor 16, thereby substantially eliminating temperature induced errors in the system, further increasing accuracy.

Abstract: An apparatus is provided for synchronously selecting different oscillators as the system clock source. The apparatus is comprised of two oscillator selectors. Each of the oscillator selectors has as its inputs the output of each of the oscillators and a three-bit command code which indicates which of the oscillators is to be selected by the oscillator selector and a single clock output. A different oscillator may be selected by each of the oscillator selectors at the same time. The output of the oscillator selectors are inputs to the clock controller. The clock controller also receives command signals for controlling the switching of the clock controller between the outputs of the two oscillator selectors. The output of the clock controller is the clock source for the system and a status signal indicating which oscillator selector is presently being used.

Abstract: A local oscillating frequency synthesizer includes a pair of synthesizers, one being used for synchronizing the frequencies of the communication channels used for the transmission and reception slots, and the other for synchronizing the frequencies when the electric field level of the other station is monitored and information is read out between idle slots other than the transmission and reception slots. Therefore, without using a high speed frequency switching synthesizer such as a direct digital synthesizer or the like, the synchronization of the frequencies by switching can be achieved in a short period of time and a local oscillating portion which is low in power consumption can be obtained.

Abstract: A substrate potential adjusting apparatus of the invention includes: a pump circuit for drawing a current from a semiconductor substrate to adjust a substrate potential; ring oscillators for supplying a periodical signal to the pump circuit and causing the pump circuit to operate; a limiter circuit for detecting a potential of the semiconductor substrate and controlling to switch between operation and non-operation of the ring oscillators in accordance with the detected potential; and a selector circuit for changing the oscillation period of the periodical signal outputted from the ring oscillators in accordance with a signal inputted externally from a chip, the signal determining an operation mode of a circuit formed on the semiconductor substrate.

Abstract: A method and apparatus for recovering the phase of a signal which may change at periodic intervals is disclosed which comprises gated variable frequency oscillators. These results are obtained in an illustrative embodiment of the present invention in which an incoming signal is fed into a gated oscillator and the complement of the incoming signal is fed into a matching gated oscillator. Advantageously, the respective outputs of the two oscillators are fed into a Boolean NOR gate. When the gated oscillators are designed to oscillate at the frequency of the incoming signal, the output waveform will have a bounded phase relationship with respect to the incoming signal.

Abstract: A microwave synthesiser comprising: a plurality of oscillator sources (1, 13, 3, 15, 5, 17, 7), each for generating signals over a range of frequencies, said ranges of frequencies together extending over a total range of frequencies generated; phase locked loops (19, 31, 83, 37, 38, 41, 81) for phase-locking any selected one of said oscillator sources (1, 13, 3, 15, 5, 17, 7) so that it generates signals of a frequency at which it is set; a single low harmonic modulator (21) for modulating the signals generated by the selected one of said oscillator sources (1, 13, 3, 15, 5, 17, 7), the modulated signals passing to an output (27) of said synthesiser; and at said output (27) elements (25, 29) for detecting the power of the signals at said output (27), the modulation by said single low harmonic modulator (21) being controlled in dependence on the detected power thereby to control the power of the signals at said output (27).

Abstract: A signal generator having a switching function includes a first oscillation circuit, a second oscillation circuit, a frequency-division circuit and a combination circuit. The first oscillation circuit outputs a first frequency signal having a first frequency and a reset signal synchronized with the first frequency signal. The second oscillation circuit outputs a second frequency signal having a second frequency which is N times higher than the first frequency. The frequency-division circuit frequency-divides the second frequency signal by N, resets a value for frequency-division based on the reset signal and generates a divided second frequency signal. The combination circuit combines the first frequency signal and the divided second frequency signal and outputs a combined signal.

Abstract: A display control apparatus includes a display control block with plural external connector terminals, and an oscillator block including plural oscillators. The external connector terminals are coupled to a selector for selecting one of the terminals in response to a selection signal applied thereto, with the output of the selector connected to the internal display control circuit via a second gate. A predetermined one of the terminals is coupled via a first gate to the internal display control circuit. The selection signal is coupled to the external connector terminals other than the predetermined terminal via a third gate. When the oscillator block of one type is used, the apparatus operates in a first operating mode, in which the first and third gates are closed and the second gate is opened, and when the oscillator block is of another type, the apparatus operates in a second mode in which the first and third gates are opened and the second gate is closed.

Abstract: YIG oscillator apparatus comprises both an FET-based YIG oscillator circuit and a bipolar transistor-based YIG oscillator circuit inside a single magnetic structure. Both YIG spheres are disposed in the single air gap of the magnetic structure, which is defined by a pole piece which is tapered to an elongated pole surface which is only slightly larger than necessary to cover both YIG spheres. A band reject filter is included inside the housing for rejecting second harmonics of desired oscillation frequencies only.

Abstract: A circuit arrangement for providing a frequency for a computer circuit is suggested in which, in adition to a quartz oscillator, an additional oscillator which quickly begins to oscillate is provided. To ensure a quick operation of the computer circuit when switching on the computer circuit or after voltage dips, the oscillator which quickly begins to oscillate is first connected with the computer circuit when voltage is applied, so that the resetting processes can proceed very quickly. If the quartz oscillator has begun to oscillate and has reached a stable operating state, a switching is effected from the oscillator which quickly begins to oscillate to the quartz oscillator which takes over from the latter to continue providing a frequency for the computer circuit. The circuit arrangement can also contain a comparator whose inputs are connected to the respective oscillators and which compares the oscillator frequencies of the output signals from both oscillators.

Abstract: An RC oscillator for varying an oscillation frequency which has a counter for counting a clock pulse of the oscillation frequency and for outputting a counted value in a form of a plurality of bits to an output terminal. It also includes a standard capacitor, a plurality of capacitors having a capacitance value in proportion to a weight of bits outputted from the counter, and a plurality of switches connected to one end of each capacitor for selectively connecting the capacitors in parallel. A plurality of first gate circuits control the switches connected thereto in response to an output of the counter, each first gate circuit has an input terminal connected to an output terminal of the counter and an output terminal connected to a control terminal of the switches.

Abstract: An integrated circuit device having a CR oscillation circuit and a crystal oscillation circuit and capable of selecting either the CR oscillation circuit or the crystal oscillation circuit, includes a unit for receiving an electrical signal, and a unit for selecting either the CR oscillation circuit or the crystal oscillation circuit in accordance with a state of the electrical signal received by the receiving unit. The integrated circuit device also includes a unit for holding the receiving unit at a predetermined level of the electrical signal. The holding unit is adapted to hold the receiving unit at the predetermined level in accordance with a state of the receiving unit. The receiving unit is a selection terminal and the selecting unit is a selection circuit.

Abstract: A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus.

Abstract: An oscillation circuit having multiple separately addressable oscillator stages for applying RF voltage across selected capacitive loads where each stage includes a power driver, a transformer and a quench/clamp circuit. The oscillation circuit includes one enablement circuit responsive to an externally applied enablement signal and address signal and a common feedback circuit connected between one end of all of the transformers and the enablement circuit. An externally applied address signal and an enable signal selects a particular oscillator stage and initiates action of a power/driver circuit to provide an initial pulse of AC current through the associated transformer for a preset period and the feedback circuit detects negative zero crossovers of the waveform of current through that transformer primary to maintain actuation of the driver circuit for as long as the external enable signal is present.

Abstract: An adjunct chip, usable as a peripheral to a microprocessor, which detects power failure, and puts the microprocessor into a known state upon power down. In order to reliably and stably put the microprocessor into a known state, several clocks are generated after the reset signal. However, since the power supply is failing, it is possible that the crystal-controlled oscillator may already have become unreliable. Therefore, a simple logic circuit (a ring oscillator, in the presently preferred embodiment) is used to generate the needed additional clocks at power-down. In the presently preferred embodiment, the switch from crystal-controlled oscillator to ring oscillator is stabilized by using a nonlinear filter circuit (driven by both the ring oscillator and the crystal oscillator) to detect when the crystal oscillator actually begins to fail. A transmission gate is then disabled, and the state frozen for long enough to allow any changes to propagate through.

Abstract: A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount.

Abstract: A semiconductor integrated circuit device comprises a first oscillator circuit driven by a first voltage for generating a first clock signal employed as the internal system clock signal for an internal circuit in the integrated circuit device and a second oscillator circuit driven by a second voltage lower than said first voltage for generating a second clock signal. A voltage boost circuit generates a stepped up voltage based on the second clock signal, which stepped up voltage is higher than the first voltage and is supplied to the first oscillator circuit and the internal circuit as their circuit source voltage.

Abstract: A clock switching apparatus includes a first phase synchronizing part for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to the n input clock signals. Each of the n first clock signals has a frequency higher than that of a corresponding one of the n input clock signals. A selector selects one of the n first clock signals. A frequency divider generates a second clock signal obtained by frequency-dividing the one of the n first clock signals selected by the selector. A second phase synchronizing part generates an output clock signal synchronized with the second clock signal.