Abstract: A waveform having an amplitude that varies to thereby represent corresponding data values is dithered to further shape the waveform so that use of the dithered waveform to create a corresponding FSK signal will result in a signal having a smoothed frequency domain profile. In various embodiments, the waveform amplitude is varied with respect to periodicity of variation, extent of variation, and duration of variation.

Abstract: A polar modulator creates an amplitude signal and a frequency signal and digitally adjusts the signals so that the frequency and amplitude signals arrive at the power amplifier at the appropriate times. A digital predistortion filter is applied to the frequency signal. The frequency signal is then provided to a single port of a fractional N divider in a phase locked loop. The output of the phase locked loop drives an input of the power amplifier while the amplitude signal is converted to an analog signal and controls the power supply input of the power amplifier.

Abstract: A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter.

Abstract: A phase modulator for direct wideband linear phase modulation of a microwave continuous wave carrier signal which is suitable for many analog and digital phase or frequency modulation techniques. Linear phase modulation range in excess of 360 degrees is provided as a result of linear variation in the modulating signal. A conditioned baseband modulating signal is injected into a highly linear fractional range phase shifter, operating at a subharmonic of the desired output frequency. A nonlinear circuit is used to perform frequency and instantaneous phase multiplication, thus expanding the linear phase modulation range to greater than 360 degrees at the desired output frequency. With special conditioning of the baseband modulating signal, the phase modulator can be made frequency agile in ultra-small frequency steps, without requiring a stable, frequency agile reference signal or frequency synthesizer.

Abstract: A direct modulating frequency shift keying transmitter for multi channel access is constructed so that a transmission signal from a voltage controlled oscillator (VCO) in a phase lock loop frequency synthesizer is output through a buffer amplifier and a transmitting power amplifier, and a modulation signal is applied to the VCO. In the transmitter, in order to cancel instantaneous deviation of a transmission frequency due to ON of the transmitting power amplifier, an ON/OFF control signal is applied to the transmitting power amplifier.

Abstract: An angular difference detector detects an angular variation according to respective signs of current xy coordinate values supplied from an FFT calculation unit and respective signs of preceding xy coordinate values. An angle calculation unit calculates an angle value of a frequency component according to respective absolute values of xy coordinate values supplied from the FFT calculation unit. Another angular difference detector classifies a difference between a current angle value and a preceding angle value supplied from a subtractor as one of a plurality of angle regions to detect an angular difference. A demapper performs demapping according to a sum of the angular variation supplied from the angular difference detector and the angular difference supplied from that another angular difference detector.

Abstract: A FSK demodulation system of the present invention has a means for comparing two preset values across 0, a positive side level shift amount and a negative side level shift amount, with an inputted amplitude level; and a demodulation means for performing demodulation based on the comparison result.

Abstract: A multi-protocol modulator capable of supporting two or more different modes of operation, each mode of operation corresponding to a different type of modulation, comprises an m-level phase shift keying (m-PSK) modulator which receives a serial input data stream and maps data contained therein into a constellation including m equidistant phases in accordance with a predetermined mapping scheme. The m-PSK modulator is shared by at least two different modulation protocols by allowing the mapping scheme to be selectively changed depending upon the modulation protocol used. The multi-protocol modulator further includes a phase rotator operatively coupled to the output of the m-PSK modulator. The phase rotator selectively rotates the phase of the m-PSK signal by a predetermined phase rotation value. The phase rotator is shared by the two or more modulation protocols by allowing the phase rotation value to be selectively modified depending upon the modulation protocol used.

Abstract: A GFSK (Gaussian Frequency Shift Keying) radio transceiver is provided for ISM (Industrial Scientific and Medical) wideband communication. The GFSK radio transceiver includes a transmitter for modulating transmitted signal into RF signal, and a receiver for demodulating received signal into digital form. The transmitter includes a VCO for generating an oscillating signal serving as a carrier signal in the transmitter and a first local oscillating signal in the transmitter; and a variable-gain power amplifier, capable of being adjustable between two gain values, for amplifying the RF signal. The receiver includes a mixer for downconverting the received signal into a first IF signal by using the first local oscillating signal from the transmitter; and an IF demodulator for downconverting the first IF signal into a second IF signal by using a locally generated second local oscillating signal.

Abstract: A method and system for tuning a bulk acoustic wave device at wafer level, wherein the thickness of topmost layer of the device is non-umiform. The thickness non-unifornity causes the resonant frequency of the device to vary from one location to another location of the topmost layer. A laser beam, operatively connected to a beam moving mechanism, is used to locally trim the topmost layer, one location at a time.

Abstract: A method for photonic wavelength shifting and stabilization is described. The method receives a photonic signal, comprised of one or more channels, and provides a wavelength shifted, stabilized, and channelized photonic signal. Data encoding is also supported. A modulation synthesizer provides a modulation waveform embedded with the shifting, stabilization and data encoding mechanisms. A variety of modulation techniques are supported. The modulation waveform is optimized for the particular modulation technique. A wavelength error detector provides feedback to the modulation synthesizer. The error signal is used to stabilize the photonic signal and correct channel wavelength errors. Fixed wavelength channels and spread spectrum channels are supported.

Abstract: A high-speed power-efficient coded M-ary Frequency-Shift Keying (M-ary FSK) modulator. The modulator includes a coding logic, which generates (M/2) Gray code signals in accordance with an (N−1) bits control signal; and (M/2) switching oscillators. Each switching oscillator includes: a composite crystal resonator with a first end and a second end; a first switch, which is controlled by Gray code signals, with one end connected to the first end of the composite crystal resonator, and the other end grounded via an equivalent negative resistance circuit; a second switch, which is controlled by serial data, with one end connected to the second end of the composite crystal resonator, and the other end grounded; and a capacitor, with one end connected to the second end of the composite crystal resonator, and the other end grounded.

Abstract: A method and apparatus for generating digitally modulated signals in which a serial data stream of digital signals to be modulated (70) is provided, the serial data stream being converted into real and imaginary components (74) which are then converted into a complex polar signal (80) representing the serial data stream. A carrier of appropriate frequency is generated by an infinite impulse response filter (84,86) and the polar signal is mixed with the output of the infinite impulse response filter to provide a representation of the complex polar signal modulated at the frequency generated by the infinite impulse response filter (88). Subsequently the imaginary component of the resulting representation is stripped from the signal (90) and the real component of the resulting representation is applied to a digital to analog converter (92) to produce an analog version of the serial data stream.

Abstract: A GFSK modulator suitable for use in an RF communication system comprising a modular subsystem and a baseband processor subsystem which is implemented digitally. The baseband processor subsystem comprises a Gaussian filter, phase accumulator and cosine and sine look up tables. The baseband processor functions to convert an input data sequence into I and Q output signals. The I and Q signals are subsequently modulated by a quadrature modulator to yield a GFSK modulated signal which can then be amplified and placed into the channel. The response of the Gaussian filter is pre-calculated for all possible combinations of the input data and the results are quantized and stored in a look up table. The quantized phase results (either magnitude or differences), generated in response to the input data, are accumulated digitally and converted to I and Q signals.

Abstract: The present invention provides a method and apparatus for implementing a continuous phase modulation with an approximate phase constellation. The method reduces complexity by using fewer than all phase points of the nominal phase constellation. The method includes the steps of storing (502) an approximate phase constellation of phase points (100) selected from a nominal phase constellation of phase points, identifying (504) a next phase in the approximate phase constellation of phase points using an N-bit input word, and outputting (506) the next phase. In reducing the number of phase points used in the modulation, the method may store only unique phase points in said phase constellation, and may further reduce the number of phase points by storing only those phase points differing by at least a phase threshold.

Abstract: A method and apparatus for generating digitally modulated signals in which a serial data stream of digital signals to be modulated (70) is provided, the serial data stream being converted into real and imaginary components (74) which are then converted into a complex polar signal (80) representing the serial data stream. A carrier of appropriate frequency is generated by an infinite impulse response filter (84,86) and the polar signal is mixed with the output of the infinite impulse response filter to provide a representation of the complex polar signal modulated at the frequency generated by the infinite impulse response filter (88). Subsequently the imaginary component of the resulting representation is stripped from the signal (90) and the real component of the resulting representation is applied to a digital to analog converter (92) to produce an analog version of the serial data stream.

Abstract: A signal generator includes an oscillator, a phase locked loop and a fractional divider. The oscillator is configured to provide an output signal. The phase locked loop is configured to receive the output signal and to provide a tuning signal to the oscillator. The phase locked loop has a phase detector configured to receive the output signal, to compare the output signal to a reference signal, and to provide the tuning signal to the oscillator based on the comparison. The fractional divider is outside of the phase locked loop and is configured to generate the reference signal.

Abstract: A frequency shift modulation circuit has a direct digital synthesizer DDS and a phase-locked loop PLL. DDS stores output signal frequency data in a plurality of registers. DDS selects the register storing the frequency data in accordance with a frequency shift keying FSK data signal whose voltage was controlled by a comparator. A signal output from DDS is input to PLL. PLL generates a signal whose phase is synchronized with the signal supplied from DDS, and outputs a frequency shift signal having a shift amount corresponding to the digital value of the FSK data signal. The FSK data signal is input via a balance adjustor to PLL so that a large frequency shift is possible. Since the frequency data is set to DDS, a stable modulation even for a low frequency is possible. In this manner, the frequency of an output signal can be stably shifted.

Abstract: The circuit for combined operation of a mobile radio with GMSK and 8-PSK modulation includes a transmission PLL for GMSK operation, and a direct modulator for 8-PSK operation. A transmission oscillator in the transmission PLL is also used as a synthesizer oscillator for the direct modulator. The modulation in the transmission PLL is suppressed for this purpose. The circuit allows cost-effective implementation while retaining the advantages of a transmission PLL.

Abstract: A high-speed power-efficient coded M-ary Frequency-Shift Keying (M-ary FSK) modulator. The modulator includes a coding logic, which generates (M/2) Gray code signals in accordance with an (N−1) bits control signal; and (M/2) switching oscillators. Each switching oscillator includes: a composite crystal resonator with a first end and a second end; a first switch, which is controlled by Gray code signals, with one end connected to the first end of the composite crystal resonator, and the other end grounded via an equivalent negative resistance circuit; a second switch, which is controlled by serial data, with one end connected to the second end of the composite crystal resonator, and the other end grounded; and a capacitor, with one end connected to the second end of the composite crystal resonator, and the other end grounded.

Abstract: To provide a new data transmission system between a game device and related peripheral devices, and a device using same. Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, the clock .component of the second pulse sequence signal is located in the data section of the first pulse sequence signal.

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances are fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: A shape modulation transmit loop with digital frequency control permits spectral shaping of a digital pulse stream (12) by controlling the slew rate of the transition signal (16) between successive pulses. The loop is formed when the digital data stream is fed into an up/down counter (152) whose output is coupled to a programmable memory means (154), such as RAM, EEPROM, flash memory or similar electronic storage means. The output (108) of the programmable memory (154) forms a first input to an adder (112) which drives an accumulator (52) with specified steps. Values corresponding to the desired waveform (70) are stored in a lookup table (60) which is coupled to a digital-to-analog conversion circuit (64) which uses the values in the lookup table (60) to construct a sine wave output signal (70) corresponding to the frequency set by the current specified step of the up/down counter (152).

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances are fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: A radio frequency transmitter circuit including a user input switch for producing an input signal, an oscillator for producing a frequency signal having a first frequency, an antenna connected to the oscillator for broadcasting the frequency signal, a coupling circuit disposed a predetermined distance from the antenna, and a microprocessor for enabling the oscillator and activating the coupling circuit in response to the input signal. When the coupling circuit is activated, a reflected impedance, derived from a change in inductance, is reflected from the coupling circuit upon the antenna thereby shifting the frequency signal to a second frequency. Sequentially activating and deactivating the coupling circuit modulates the frequency signal.

Abstract: A frequency shift keying device includes a reference oscillator which provides a reference signal, and a controlled oscillator having a control input and an output signal. A phase detector compares the output phase of the output signal with a reference phase of the reference signal to form an error signal on a detector output of the phase detector. The error signal provides phase locking of the output signal. A compensation circuit having a compensation input is connected to a modulation output of a modulation source which outputs a modulation signal. The compensation circuit also has a compensation output connected to the detector output. The compensation circuit provides a compensation signal which counteracts the error signal to form a modified error signal for attenuating the phase locking so that it becomes possible to modulate the controlled oscillator at a low rate without disturbing the sound spectrum which is also transmitted using a carrier generated by the controlled oscillator.

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances is fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: An MSK modulator which performs an accurate MSK modiation with high speed digital data is provided. When a to-be-modulated digital signal is provided from a code generator 1, a bidirectional shift register 2 allows a bit-row with sixteen bits to shift in circulation in a direction determined in accordance with a logic value of the supplied digital signal. Weighting adders 3I and 3Q weight and add logic values of the fifth to twelfth least significant bits in the bit row and logic values of the first to eighth least significant bits in the bit row. Two analog signals each of which is generated by the weighting adders 3I and 3Q are out of phase to each other by (&pgr;/2) radians. The analog signal generated by the weighting adder 3I is multiplied by a signal generated by a first local oscillator 7, whereas the analog signal generated by the weighting adder 3Q is multiplied by a signal generated by a phase shifter 8. An adder 9 adds these multiplication results to generate an MSK modulation wave.

Abstract: A transmitter encodes a number 2N data bits by using N data bits to select one of 2N levels of a cosine wave and the other N data bits to select one of 2N levels of a sine wave. The modulation attains the cosine wave levels at instants offset by half an N-bit symbol interval with respect to the sine wave levels, and is called Offset QAM (OQAM). A received OQAM signal is amplified, filtered and digitized at a sampling rate of preferably only one sample per N-bit half-symbol interval. Successive N-bit half-symbols comprise information modulated alternately on a cosine and a sine carrier wave. The receiver may remove this successive rotation by applying successive derotations of successive digitized samples by like amounts. The derotated samples are then correlated with known sync half-symbols. The sync correlations determine a set of channel coefficients describing the dependence of each digitized sample on one or more unknown half-symbols.

Abstract: The present invention relates to a voltage-controlled quartz crystal oscillator, including an oscillation transistor, the base of which is connected to a first terminal of a quartz crystal and the emitter of which is connected, via a first capacitor, to a second terminal of the quartz crystal connected to a first supply terminal, and including an active circuit introducing a variable capacitance between the base and the emitter of the oscillation transistor, the active circuit being voltage-controlled.

Abstract: A variable rate modulator for selectively encoding a variable rate data stream according to one of a plurality of modulation formats. A timing and control circuit locks the variable rate data to a master clock, an encoder selectively encodes the data according to one of a plurality of modulation formats, and a polyphase filter performs pulse shaping and interpolation functions using only shift and add functions to produce a DAC-ready output signal.

Abstract: A frequency generating circuit scales a warp range of a frequency signal. The frequency generating circuit includes a first frequency signal (10) having a first offset signal with a first frequency relationship to the first frequency signal, and a second frequency signal (14). A frequency scaling element (16) receives the first frequency signal (10) and second frequency signal and provides a third frequency signal, such that the third frequency signal includes the first offset signal having a second frequency relationship to the third signal. A switch (54), has a control input (74), a first input for receiving the first frequency signal, a second input operably coupled to the frequency scaling element (16, 42) for receiving the third frequency signal and an output (76) operably coupled to the first input or the second input dependent upon a control signal applied to the control input (74).

Abstract: A direct modulation phase lock loop (PLL) a voltage controlled oscillator (VCO) (114). A divider (118) has a first divider input coupled to the VCO and a second divider input to receive a modulation inducing divisor sequence. A phase detector (102) has a first detector input coupled to the divider to receive the output thereof, and a second detector input to receive a reference input. A tuning circuit (306, 406) is coupled to the phase detector and the VCO, the tuning circuit responsive to a variable DC reference potential such that the tuning circuit has a frequency response that is constant over the modulation bandwidth whereby the PLL is a type 1 PLL with low modulation distortion.

Abstract: A signal modulator includes a digital signal processor, an address buffer, a counter, and a first memory device. The digital signal processor is adapted to receive digital data at a receive sampling rate and define a code word based on a subset of the digital data. The address buffer is coupled to the digital signal processor and adapted to receive the code word and store a base address. The counter is adapted to increment an address offset at a transmit sampling rate. The transmit sampling rate is a multiple of the receive sampling rate. The first memory device has a plurality of memory locations and is adapted to receive the base address and the address offset and provide a first waveform data sample from the memory location addressed by the base address and the address offset. A method for modulating a signal includes receiving digital data at a receive sampling rate. The time interval between digital data samples defines a bit interval. A code word is determined based on a subset of the digital data.

Abstract: A transmitter in which a complex low IF digitised signal is applied in quadrature to a complex phase comparator together with a digitised frequency down-converted version of an analogue signal produced by a transmitter VCO. The low IF digitised signal serves as a reference against which the digitised frequency down-converted version of the transmitter VCO is compared. The output of the complex phase comparator is converted to an analogue signal which is applied as a control signal to the transmitter VCO. An analogue embodiment of the transmitter which uses zero-IF signals is also disclosed.

Abstract: A method, system, and computer program product for spread spectrum communication is provided using circular waveform shift-keying (CWSK). Circular waveform shift-keying is a modulation technique for conveying data over a spread spectrum channel. Data symbols are encoded in a circular time shift and/or circular frequency shift of a spread spectrum waveform. In a receiver, a CWSK synchronization stage and demodulator stage can be combined on a single fast convolution ASIC chip. Using CWSK modulation and demodulation, a secure, low-cost terminal is realized that can process calls on multiple spread spectrum channels in a hubless wireless network linking large numbers of low data rate users.

Abstract: Disclosed is a modulation method in which the frequency band of a transmission signal, consisting of signal points generated at a given modulation rate in accordance with transmission data, is shifted by a desired frequency shift amount, and which is capable of lowering carrier frequency without increasing the amount of computation.

Abstract: A digital radio transmission and reception system capable of preventing shift of carrier by fading through receiving a modulated signal radio-transmitted, and then directly demodulating the signal.

Abstract: The present invention includes a method for generating a GMSK modulating signal from a serial digital data bit stream whereby the GMSK modulating signal modulates a carrier frequency signal associated with a GMSK transmitter of a digital communications system. Specifically, the method includes converting each set of m consecutive data bits of the bit stream into a parallel symbol, whereby there are 2.sup.m possible symbols. Each symbol is generally defined as (B.sub.-(m-1). . . B.sub.0), where B.sub.0 is the current data bit and B.sub.-(m-1) is the mth previous data bit with respect to B.sub.0. Next, a corresponding phase advance is assigned to each of the 2.sup.m symbols, each phase advance being substantially equivalent to a percent phase advance contributed by the m consecutive data bits of each symbol. Also, four corresponding accumulated phases are assigned to each of the 2.sup.m symbols, each accumulated phase being derived from a multiple of 90 degrees.

Abstract: A transmitter and a phase locked loop (30) for a transmitter are disclosed. The phase locked loop (30) upconverts the frequency of a baseband signal to a frequency for radio transmission. As well as the usual components, the phase locked loop (30) comprises a modulator (39) for modulating a baseband signal (f.sub.bb) onto a carrier (f.sub.ref /R) and forwarding the resultant modulated signal (f.sub.c) to one of the inputs of the phase detector (33). It also comprises a low pass filter (38) in its forward path between the phase detector (33) and the voltage controlled oscillator (34) for passing signals having baseband signal frequencies. A mixer (35) and main frequency divider (36) are provided in the feedback path to downconvert the transmit signal (f.sub.tx). This low division eliminates large amounts of multiplicative noise within the loop bandwidth, and therefore enables a large loop bandwidth to be used. Consequently, the settling time of the phase locked loop is improved.

Abstract: A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency.

Abstract: A modulation system is provided with a data analyzer detecting input of a modulated data and a modulation clock signal and latching and detecting an edge of the modulated data, in response to the modulated data and the modulation clock signal, a signal controller, responsive to an output of the data analyzer, carrying out an operation process with respect to the frequency deviation data and carrying out one of a frequency deviation amplitude control operation and a frequency deviation time control operation, a digital-to-analog converter converting an output of the signal controller into an analog signal, and a transmitting unit transmitting an output of the digital-to-analog converter.

Abstract: A .SIGMA..DELTA. modulator-controlled, phase-locked-loop circuit, and an associated method, generates a frequency-regulated signal which does not exhibit undesired tones. Dithering signals are generated and are provided to a .SIGMA..DELTA. modulator. The .SIGMA..DELTA. modulator forms a division-factor control signal used to control the division factor of a frequency divider forming a portion of the PLL circuit. The dithering signals applied to the .SIGMA..DELTA. modulator reduce the likelihood that the .SIGMA..DELTA. modulator shall enter a limit cycle and generate repetitive output signals.

Abstract: Apparatus for generating the family of PSK (phase shift keyed) modulations, which include BPSK (binary PSK), QPSK (quaternary PSK), MSK (minimum shift keying) and the like. The carrier is generated with the desired digital information already phase-modulated onto it by directly introducing a phase shift or delay onto the error path of a phase-locked loop. causing the phase-locked loop to create the phase modulation. The [proposed scheme differs from common practice approaches, which are usually implemented by linear synthesis (an AM technique); rather, it] invention employs direct nonlinear synthesis (an FM technique). The invention [yields good phase precision with arbitrary spectral shaping under the constraint of constant envelope signaling. It] permits the connection of the output of a simple, inexpensive VCO (voltage controlled oscillator) directly to a system's antenna without the need for intervening circuit elements such as phase splitters, mixers, and the like which is applicable to [.

Abstract: A digital baseband modulator having a flexible architecture that is readily adaptible to a variety of digital modulation types is provided. A symbol builder maps the input data to a series of modulation states corresponding to data symbols that are represented as state indexes. A pair of digital filters accepts the state indexes being generated by the symbol builder to provide both up-sampling and filtering functions. The digital filters are implemented using random access memory (RAM) to implement blocks of interpolating look-up multipliers which may be readily configured between fast, normal, and long modes. The filtered output data from the digital filters is provided to a resampler that converts the filtered output data to an output sample rate that corresponds to the sample rate of output DACs and corresponding analog low pass filters.

Abstract: In order to provide a digital GMSK modulator operating sufficiently stably without aliasing distortion even with a sampling rate of twice of that of input signal, a quasi-GMSK modulator of the invention comprises: integration means (105) for integrating an input signal; filtering means (106, 107) for performing a digital Gaussian filter manipulation of output of the integration means with a low sampling rate of twice or more of a data rate of the output of the integration means; a phase modulator (107, 108 and 111) for obtaining a continuous wave phase-modulated with output of the filtering means; and a limiter (112) for limiting amplitude of the continuous wave within a fixed value.

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal at a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage. An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A digital modulator capable of obtaining a high FM modulation index and reducing the quantization noise without increasing the sampling frequency of an A/D converter of input voice. A phase variation .phi.(Ts) of the digital data (Ts is the sampling period) produced on the basis of the output from the A/D converter is divided by a predetermined integer N (N>1) by a divider, and is fed to an integrator. The integrator integrates the divided phase variation .phi.(Ts)/N for every time interval Ts/N, thereby producing a phase component .phi.(t) of the complex envelope of the modulation signal. The phase component .phi.(t) is resolved into cosine and sine components at the time interval Ts/N. The cosine and sine signals are D/A converted into analog signals which are quadrature modulated by a quadrature modulator.

Abstract: A modulated clock MSK modulator that separately modulates a sinusoidal clock signal by square wave I and Q digital data signals prior to the I and Q data signals being modulated onto a carrier wave signal. Mixers or applicable biphase switches are utilized to impress the I and Q digital data signal information onto the clock signal by inverting or non-inverting the clock signal on separate I and Q data rails to create I and Q modulated clock signals separated in phase. The I channel data modulated clock signal and the Q channel data modulated clock signal are then separately applied to a conventional quadraphase modulator to be separately modulated onto a carrier wave signal, and the summed together to be transmitted.

Abstract: A frequency synthesizing circuit has an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied. The circuit moreover comprises a crystal oscillator supplying a reference clock signal, a phase-locked loop (PLL) having a VCO and a phase detector. The phase detector compares the data-modulated output signal with the reference clock signal and, in response to this, supplies an error signal by means of which the VCO output frequency is controlled. A compensation circuit, which receives a measure of the bit flow received, compensates the data-modulated output signal in the phase-locked loop in response to this before it is supplied to the phase detector.