Abstract: A power system includes a pulse width modulation device. The pulse width modulation device outputs first, second, third and fourth driving signals. The pulse width modulation device receives a control signal. The control signal is divided into a positive periodic signal and a negative periodic signal. A portion of the positive periodic signal higher than or equal to a maximum threshold voltage is clamped as the maximum threshold voltage to generate a first comparison waveform. The positive periodic signal is clamped as the reference voltage level to generate a second comparison waveform. According to the first comparison waveform, a first ramp signal is generated. According to the second comparison waveform, a first pulse width modulation signal is generated. The first, second, third and fourth driving signals are adjusted according to the first ramp signal and the first pulse width modulation signal.

Abstract: A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.

Abstract: A dead band compensation system is provided that provides dead time compensation for a three-phase inverter in connection with counting the time difference between a pulse width without a dead time interval and a pulse width available at the output of the inverter (100). An error measurement is determined, a portion of which is fed back subsequently. Harmonic components, among other things, are reduced, to an extent, in the load current through an inverter load (120). Further, compensation for inverter voltage output errors may be provided.

Abstract: A three input voltage comparator provides termination of a pulse width modulation (PWM) output in a switched mode power supply. Shutdown of the PWM signal occurs when a sense current from the switching transistors exceeds either or both of the limit and error current references. The three input voltage comparator replaces the generally used two input voltage comparator and also eliminates the necessity of having to provide a voltage clamping circuit on the output of the voltage error amplifier in the switched mode power supply. The three input voltage comparator may also comprise selectable polarity control for more versatile integration of it into a switched mode power supply design.

Abstract: An integrated circuit includes a receiver portion, a transmitter portion, and a modulated phase locked loop. The receiver portion is for receiving a radio frequency (RF) signal at a receiver input of the receiver portion. The transmitter portion is for transmitting an RF signal at a transmitter output of the transmitter portion. The modulated phase locked loop (PLL) is shared between the receiver portion and the transmitter portion. The transmitter output and receiver input are coupled together in a loopback configuration during a test mode. The transmitter portion and the receiver portion are enabled concurrently while a modulated PLL signal is provided to the receiver portion from the transmitter portion via the loopback configuration.

Abstract: A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]).

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract: A modulation apparatus for a class D switching amplifier is capable of reducing power consumption of an Electro-Migration Interface (EMI) of an output and a gate driver in a zero input signal. The modulation apparatus for a class D switching amplifier includes a control unit for detecting and outputting a control signal which is a common signal component of a first modulation signal modulated by using a first input signal and a second modulation signal modulated by using a second input signal; and is characterized by feedback of a first output signal, a second output signal and a common output signal outputted by using the first modulation signal, the second modulation signal and the control signal through an input of the modulation apparatus.

Abstract: Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.

Abstract: A novel design scheme for the compensation circuitry of solid-state Marx modulators has been described for enhancing the compensation ability of the compensation cells of solid-state Marx modulators and simplifying the entire circuitry of the modulator. High-speed solid-state switches are adopted in the new compensation cell for the control of the compensation actions. Inductive components and diodes are adopted in the design scheme to smooth the flattop of the voltage pulse output by the Marx modulator.

Abstract: An apparatus and method for amplifying a Transmit (Tx) signal according to an Envelope Tacking (ET) scheme in a wireless communication system are provided. A transmitting end apparatus includes an envelope gain controller for controlling a gain of a digital baseband Tx signal in accordance with power control, a detector for detecting an envelope signal from the digital baseband Tx signal whose gain is controlled, and for shaping on the envelope signal, a first Digital to Analog Converter (DAC) for converting the shaped envelope signal into an analog signal, and an envelope modulator for generating a drain bias of a power amplifier that amplifies a Radio Frequency (RF) Tx signal by using the analog envelope signal. Accordingly, a digital-based ET scheme is implemented, and by using a plurality of shaping tables, efficiency of the ET scheme can be maximized in a transmitting end that uses power control.

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract: An illumination apparatus includes a power supply, a pulse width modulation (PWM) circuit, a switching unit, and an illuminating unit. The power supply supplies a supply voltage to the PWM circuit and the illuminating unit. The PWM circuit outputs a first level voltage by being fully charged by the voltage of the power supply and outputs a second level voltage by being fully discharged. The switching unit is turned off according to the first level voltage and controls the illuminating unit to stop emitting light. The switching unit is turned on according to the second level voltage and controls the illuminating unit to emit light.

Abstract: A pulse width modulation method for controlling the output power of a pulsed gas discharge laser powered by a pulsed RF power supply comprises delivering a train of digital pulses to the RF power supply. Each pulse in the train has an incrementally variable duration. The power supply is arranged to deliver a train of RF pulses corresponding in number and duration to the train of digital pulses received. The average power in the RF-pulse train can be varied by incrementally varying the duration of one or more of the digital pulses in the digital pulse train. The train of RF pulses is used to power a gas discharge laser. The gas discharge laser outputs a pulse train corresponding to the RF pulse train.

Abstract: A modulation arrangement comprises an input (E) for supplying a data signal (DS), a pre-modulator (VMod) that is coupled to the input (E) and features a clock pulse input (TEV) for supplying a pre-clock pulse (VT), a main modulator (HMod) that is coupled to the pre-modulator (VMod) on the input side and comprises a clock pulse input (TEH) for supplying a main clock pulse (HT), as well as an output for providing a modulated control signal (ST), and a switchable current source (Q, S) for providing a current (IS) that is controlled by the modulated control signal (ST) at an output (A) of the modulation arrangement. Furthermore, a method for providing a modulated control signal is disclosed.

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract: An example two-way integrator includes a first current source, a second current source, a first offset current source, a second offset current source, a capacitor, a switching reference and a comparator. The capacitor integrates a sum of a first input current and a first offset current by charging with both the first current source and the first offset current source. The capacitor subsequently integrates a sum of the second input current and the second offset current by discharging with both the second current source and the second offset current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to pulses of a pulse signal. The comparator is coupled to compare the switching reference with a voltage on the capacitor.

Abstract: A fixed-frequency control circuit and method detect the difference between the frequency of a pulse width modulation signal and a target frequency to adjust a current used to determine the on-time or off-time of the pulse width modulation signal, such that the frequency of the pulse width modulation signal is stable at the target frequency.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: A slope compensation circuit includes an oscillator for generating a first clock signal having a reference frequency, a ramp signal generator for generating a ramp signal having a duty ratio of about 50% or higher based on the first clock signal, and a slope compensation signal generator for outputting a slope compensation current based on the ramp signal.

Abstract: A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.

Abstract: The present disclosure relates to I/Q modulation circuits, devices, and methods.

Abstract: A fixed-frequency control circuit and method detect the difference between the frequency of a pulse width modulation signal and a target frequency to adjust a current used to determine the on-time or off-time of the pulse width modulation signal, such that the frequency of the pulse width modulation signal is stable at the target frequency.

Abstract: A digital control switching power supply unit converts an input voltage into a desired output voltage using a digitally controlled pulse width modulation (PWM) signal according to a switching cycle. The power supply unit includes an analog-to-digital converter (ADC). The ADC converts a result of a comparison between an output voltage and a reference voltage to a digital signal during a conversion cycle. The ADC includes a circuit for outputting a phase difference between a switching cycle and the conversion cycle, and a delay circuit. The delay circuit generates a delay output current based on a result of the comparison and the phase difference and determines the conversion time delay according to the delay output current. The delay circuit also generates a delay reference current based on the reference voltage and the phase difference and determining the duration of the conversion cycle according to the delay reference current.

Abstract: The invention provides a multi-phase digital pulse width modulator (MP-DPWM) to implement a distribution scheme which applies the duty cycle in the fastest possible manner with restriction on the number of switching actions per phase and cycle, and additionally takes the number of available phases into account. It modulates switching signals according to a duty cycle input command, their previous switching states, and the current switching cycle. The controller is adapted to additionally take the residue of the previous subcycle into account. In the control scheme: each phase is allowed switch up to twice per cycle; only the next phase in the cycle is additionally turned on, at the start of a subcycle, and if a phase is still on at the end of a subcycle it can be kept on for longer, if required.

Abstract: A dual mode modulator is proposed for driving a power output stage having a serial connection of high-side power FET and low-side power FET. The dual mode modulator includes a PWM modulator operating under a PWM-frequency and a PFM modulator for controlling the power output stage. To improve the dynamic load regulation of the dual mode modulator, a dynamic frequency booster can be added to the dual mode modulator to boost up the PWM-frequency from its normal operating frequency during a PFM-to-PWM mode transition period. Secondly, a dynamic slew rate booster can be added to boost up an error amplifier slew rate of the PWM modulator from its normal operating slew rate during the mode transition period. Thirdly, a dynamic turn-off logic circuit can be added to turn off the low-side power FET during the mode transition period.

Abstract: A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

Abstract: A PWM control method increases/decreases a duty ratio of a PWM signal with a predetermined resolution so to control the duty ratio of the PWM signal in the case of a PWM control. The resolution of the duty ratio of the PWM signal is increased to make a high period in the duty ratio of the PWM signal longer than a rise time of the PWM signal if the high period is shorter than the rise time. The resolution of the duty ratio of the PWM signal is increased to make a low period in the duty ratio of the PWM signal longer than a fall time of the PWM signal if the low period is shorter than the fall time.

Abstract: Dead time compensated complementary pulse width modulation (PWM) signals are derived from a PWM generator by first applying time period compensation to the PWM generator signal based upon the direction of current flow in an inductive load being controlled by the PWM generator. Dead time is then applied to the compensated PWM generator signal for producing complementary dead time compensated PWM signals for controlling power switching circuits driving the inductive load.

Abstract: A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.

Abstract: A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.

Abstract: A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.

Abstract: A pulse step modulator employs a plurality of series connected unit step power amplifier modules. Each module is turned on by a turn-on signal to provide a unit step voltage of a given value. An output circuit is connected to the modules for providing an output voltage to a load and wherein the output voltage is a multiple of the unit step voltages in dependence upon the number of modules that are turned on. The modules are sequentially turned on in a given order and are turned off in the reverse order. An encoder provides turn-on signals with each turn-on signal being applied to a selected one of the modules. The number of turn-on signals provided varies as a function of the magnitude of a time varying input signal. A controller alternately turns enables or disables (in a swapping manner) one of a pair of associated modules as the magnitude of the input signal increases and decreases.

Abstract: Synchronously stackable double-edge modulated pulse width modulation generators are disclosed. An example pulse width modulation generator includes a ramp generator to generate first and second ramp signals that interact to form a virtual ramp signal; and a comparator module coupled to the ramp generator configured to produce a pulse width modulated signal based on a comparison between the virtual ramp signal and an input signal.

Abstract: Systems and methods are provided for operating a pulse width modulation (PWM) circuit in a direct current (DC) to alternating current (AC) power inverter to reduce the magnitude of harmonics. The PWM circuit operates using a reference signal having an irregular period. In one implementation the irregular periodicity includes a sequence of periods uniformly distributed about a target period.

Abstract: A class-D amplifier (10) includes a logic circuit (40) for controlling the operation of a switching bridge (11). The logic circuit (40) transmits the differential mode of a differential pulse width modulation input signal and deletes a central portion of the common mode of input signal, while preserving pulses of a minimum pulse width following a rising edge and preceding a falling edge in common mode of the input signal. Deleting the central portion of the common mode signal improves the efficiency and reduces the electromagnetic interference radiation of the class-D amplifier (10). Preserving the pulses of the minimum pulse width ensures the proper operation of the switching elements (12, 14, 16, 18) in the switching bridge (11), thereby reducing the distortion in the signal amplification.

Abstract: A duty cycle correction circuit with wide-frequency working range utilizes a pulse generator having adjustable pulse width function to adjust the width of the pulse and outputs a clock signal with the duty cycle of 50%. The pulse generator includes a NAND gate, a modulation device, and an inverter. The inverter is coupled between the second input end of the NAND gate and the modulation device. The modulation device modulates the low-level status of the input clock signal and accordingly outputs to the inverter. The first input end of the NAND gate receives the input clock signal. The NAND gate operates NAND calculation to the signals received on the input ends of the NAND gate and accordingly outputs a periodic low-level pulse signal.

Abstract: Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and dithering signals employed by the digital pulse width modulator. Adders add the phase select signals from the digital pulse width modulator and the dithering signal to the leading and trailing edge control signals, with the output employed by multiplexers as select controls in selecting a phase of from the phase-shifted versions of the system clock with which to clock latches controlling the leading and trailing edges.

Abstract: The present invention relates to a pulse width modulation switching direct voltage circuit. The PWM circuit comprises a first passive device, a second passive device and a third passive device which they are connected orderly in series, and a fourth passive device which is connected in parallel between the first passive device and the second passive device, wherein the rated value of the fourth passive device is at least three times more than the rated value of the first passive device. Herewith, the voltage-cycle relationship of the PWM circuit becomes linear. Under such a state, the PWM circuit is enabled with good work efficiency.

Abstract: For controlling a multi-stage load with pulsewidth modulation (PWM), the individual stages have normally separately applied thereto load currents which are clocked in a phase-shifted mode so as to avoid load peaks. An output stage for PWM control of a load stage with a delay circuit which, in addition to the load current modulated by a PWM input signal, supplies a PWM output signal that is delayed by a predetermined fraction of the period duration relative to the PWM input signal. The output stage can especially be realized by integrating the delay circuit together with the actual power semiconductor switch and an associated monitoring and control circuit in a single component. By cascading such output stages, a controller for phase-shifted PWM control of multi-stage loads, which is independent of a precise time base, can be realized in a simple manner.

Abstract: When both step-up PWM control and step-down PWM controls are executed, the offset of the ON/OFF switching timing for step-up PWM control and/or the offset of ON/OFF switching timing for step-down PWM control are changed to become identical. By synchronizing ON/OFF switching timing for step-up PWM control and ON/OFF switching timing for step-down PWM control, the loss on switching can be reduced.

Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.

Abstract: In one embodiment, a PWM power supply controller asserts a PWM control signal synchronously to a clock signal of the PWM controller and also asserts the PWM control signal asynchronously to the clock signal.

Abstract: A quasi average current mode control scheme is provided. The control scheme allows only detecting one part of the inductor current of the switching converter to control the inductor current and make the average current of the inductor follow the reference current. The control scheme is noise insensitive and makes the whole controlled system cost effective.

Abstract: Pulse-width modulation signal generating device and method for the same that can generate multiple pulse-width modulation signals with different overall lengths wherein only a small amount of data is stored in storage means and duty cycles are varied between individual unit pulse signals. Multiple settings are stored in storing means for three types of variables: initial duty cycle; duty change range; and number of unit pulse signals that form a single phase. Out of these, a selected initial duty cycle, a selected duty change range, and a selected number of unit pulse signals that form a single phase are retrieved. These selected values are used to represent the duty cycles for all unit pulse signals forming one phase. The unit pulse signals for which duty cycles have been determined are output to generate a pulse-width modulation signal.

Abstract: A pulse width modulator is presented herein and it includes a pulse width driver circuit that receives a time varying ramp signal that is modulated by a time varying analog input signal to produce a pulse width modulated drive signal comprised of turn-on pulses having widths that vary with variations in the magnitude of said input signal. A switch is turned on by each drive pulse for a time duration dependent upon the duration of each drive pulse and provides an output signal therefrom. A negative bias amplifier provides a negative bias signal that has pulsations that are synchronized with said drive pulses but of opposite phase. A combiner combines output signal with the negative bias signal to provide a combined output signal.

Abstract: A pulse width modulation circuit of the present invention includes: pulse generation means being provided with a first power supply and charged with a first current and a second current between which a constant current is distributed to turn ON/OFF a switching element, thereby generating a pulse from a first output section; pulse modulation means for controlling the charging while controlling a distribution ratio between the first current and the second current based on an input signal, thereby changing a pulse width of the output pulse; and first short circuit means for shorting the first output section with the first power supply when the pulse being output from the first output section transitions to a voltage of the first power supply.

Abstract: The present invention relates to a modulation device MD, which is designed to produce an output signal Vout comprising a succession of pulses. According to the invention, a device of this type includes: two transistors T1 and T2, which are arranged as a differential pair; a capacitive element C, which is connected between the two transistors T1 and T2; adjusting means LC1, LC2, UC1, UC2, in order to adjust the potential of at least one of the terminals of the capacitive element C; and comparing means CMP, which supply the output signal Vout, which is representative of the sign of the voltage Vc, which is present at the terminals of the capacitive element C. By means of a simple and substantially analog structure, the invention permits rapid, flexible control of the width of the pulses of the output signal Vout.

Abstract: A pulse width modulator (PWM) circuit is provided. The PWM circuit includes a selective synchronization circuit configured to receive vector signals, and selectively synchronize the vector signals. The synchronized vector signals are provided to a tap selection circuit configured to output tap selection signals that are logically combined by a transition generating circuit to produce a pulse width modulated signal based on logically detected transitions in the tap selection signals.

Abstract: A pulse width modulator includes a clock operative to count successive discrete time intervals having a period equal to a desired full pulse width, and configured to generate a clock signal. The pulse width modulator also includes an adjustable delay line comprising a plurality of delay line elements, each delay line element operative to generate a clock signal at a specific location, which when combined with a transitional instruction, will produce a modulated output that has a plurality of transitions within the clock period. The pulse width modulator further includes processing circuitry configured to receive the clock signal and a pulse code input and operative to select one of the delay line elements to generate a clock signal at a specific location to produce a single modulated output that transitions at a desired modulated frequency. A method is also provided.