Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Abstract: A cryptographical apparatus for converting input bit sequences, whose overflow-free arithmetic addition results in a secret, into output bit sequences whose logic XORing results in the secret. The apparatus comprises a data interface for providing a first input bit sequence and a second input bit sequence and a processing circuit configured to a) gate the first input bit sequence and the second input bit sequence to obtain a logic result indicating overflow bit positions at which both the first input bit sequence and the second input bit sequence have a value of one; and to b) change the first and/or second input bit sequence at at least one overflow bit position. The processing circuit is configured to repeatedly perform steps a) and b) by using the respectively changed input bit sequences, until the logic result indicates no further overflow bit position and the output bit sequences are obtained.

Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.

Abstract: Systems, transmitters, and methods employing waveform bandwidth compression to transmit information are provided. Transmitters may include an encoder to generate a time-domain amplitude sequence from information in a constant amplitude sinusoidal modulation format; fit a polynomial to the time-domain amplitude sequence, the fitted polynomial spanning at least one transmission time interval; and convert the polynomial to a transmission signal, the transmission signal comprising a sum of sinusoids of differing frequencies, each sinusoid having a continuously time-varying amplitude. A carrier source providing a carrier that is modulated with the transmission signal and transmitted through the system to a receiver, which receives the signal in the constant amplitude sinusoidal modulation format. The sum of sinusoids of differing frequencies having a continuously time-varying amplitude may be generated using instantaneous spectral analysis, to reduce the spectral occupancy of the transmission signal.

Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.

Abstract: A voltage error signal is provided to a PWM controller of a voltage regular and used to produce a PWM signal that drives a power stage of the regulator. When operating in an adapter current limit regulation mode, an adapter current sense voltage, indicative of an adapter current, is compared to an adapter current reference voltage to produce an adapter current error signal. A compensator receives the adapter current error signal and outputs a compensated adapter current error signal. The adapter current sense voltage, or a high pass filtered version thereof, is subtracted from the compensated adapter current error signal to produce the voltage error signal provided to the PWM controller. Alternatively, an input voltage, or a high pass filtered version thereof, is added to the compensated adapter current error signal to produce the voltage error signal.

Abstract: A method includes providing a power supply package (PSP) that includes a power supply, an RFID tag, and a power switch, where a control terminal of the power switch is coupled to an output terminal of the RFID tag, and load path terminals of the power switch are coupled between an output terminal of the PSP and a first terminal of the power supply, where a control register of the RFID tag is pre-programmed with a first value such that the RFID tag is configured to generate a first control signal that turns off the power switch; receiving, by the RFID tag, a second value for the control register of the RFID tag; and writing, by the RFID tag, the second value to the control register of the RFID tag such that the RFID tag is configured to generate a second control signal that turns on the power switch.

Abstract: A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*?t, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.

Abstract: Embodiments provide a pre-distortion circuit and apparatus, a method and computer program for pre-distorting, a transmitter, a radio transceiver, a communication device, a mobile transceiver, a base station transceiver and a storage. The pre-distortion circuit (10) is configured for a digital quadrature signal. The pre-distortion circuit (10) comprises a first input (12) for an inphase component of the quadrature signal and a second input (14) for a quadrature component of the quadrature signal. The pre-distortion circuit 10 comprises a signal processing circuit (16) configured to determine whether polarities of the inphase component and quadrature component are equal, and to determine pre-distortion coefficients based on the amplitude of the inphase component, the amplitude of the quadrature component, and based on whether the polarities are equal.

Abstract: A method for use in a mobile communications network that includes a plurality of infrastructure equipment each providing wireless connectivity within at least one cell, and a communications device configured to communicate wirelessly with at least a first infrastructure equipment including use of a radio bearer. The first infrastructure equipment performs the method including determining that there is a requirement to alter data handling resources allocated for handling the radio bearer in one or both of the first infrastructure equipment and the communications device, re-establishing, in response to the determination, its radio link control protocol layer, transmitting a reconfiguration message to the communications device to effect re-establishment of its radio link control protocol layer, and adding a new bit in the header of data packets transmitted to the communications device for a predetermined time after re-establishment of the radio link control protocol layer of the first infrastructure equipment.

Abstract: A calibration control component within a transmit (TX) or receive (RX) device executes a calibration sequence to ensure reliable data transmission and reception within the device. The calibration sequence comprises a set of calibration functions that are sequentially executed. The calibration control component detects a pause function being enabled based on a pause function configuration register. Based on detecting the pause function being enabled, the calibration control component pauses execution of the calibration sequence.

Abstract: This invention provide a PWM outputting circuit that, from pattern data represented by a plurality of bits representing a pulse width, generates a pulse width modulation signal, wherein the circuit comprises a multi-phase-clock generating circuit which generates a multi-phase clock which is a plurality of clocks of mutually different phases; an edge-pulse generating circuit which, from the pattern data that is inputted, detects a bit position of a rising-edge and a bit position of a falling-edge in the pulse width modulation signal, and generates a rising-edge-pulse and a falling-edge-pulse based on the detection; and an SR latch circuit which, by the rising-edge-pulse being inputted to a set terminal and the falling-edge-pulse being inputted to a reset terminal, generates and outputs the pulse width modulation signal.

Abstract: A cycle setting unit of a signal generating circuit varies a set cycle value. A first determining unit determines a first ON time on the basis of: a first duty ratio obtained by correcting, with a correction value, a ratio between a target ON time and a reference cycle; and a set cycle value. A second determining unit determines, as a second ON time, a setting candidate value that is close to the first ON time. A generating unit generates a PWM signal reflecting the set cycle value and the second ON time. A third determining unit determines the correction value that is to be used next time by the first determining unit, on the basis of the target ON time, the reference cycle, the correction value of the previous time, the set cycle value, and the second ON time.

Abstract: This application relates to methods and apparatus for digital microphones. Disclosed is a digital microphone apparatus (300) for outputting a digital output signal (DATA) at a sample rate defined by a received clock signal (CLK). The apparatus includes a band splitter (302) configured to receive a microphone signal (SMD) indicative of an output of a microphone transducer and split said microphone signal into first signal path (SP1) for frequencies in a first band and a second signal path (SP2) for frequencies in a second band, the frequencies of the second band being higher than the frequencies in the first band. A modulation block (304) is configured to operate on the second signal path to down-convert signals in the second signal path from the second frequency band to a lower frequency band.

Abstract: An ODT circuit is connected to a memory module and includes a first transmission line, a first ODT, a second ODT, a first switch circuit, a third ODT, a fourth ODT, a second switch circuit, and an ODT control logic. The first and second ODTs are coupled to a first node on the first transmission line. The first switch circuit includes a first switch and a second switch, and is driven according to the first control signal. The third and the fourth ODTs are coupled to a second node on the first transmission line. The second switch circuit includes a third switch and a fourth switch, and is driven according to the second control signal. The ODT control logic outputs the first control signal and the second control signal to control the first switch circuit and the second switch circuit to be turned on at different timings.

Abstract: A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

Abstract: Various embodiments of the present technology comprise a method and apparatus for a class-D amplifier. In various embodiments, the class-D amplifier operates to control an output signal during a start-up state to suppress a pop noise (start-up noise) without the need for a mute switch. The class-D amplifier may utilize a transition signal during the start-up state to prime or otherwise stabilize the output signal to suppress the pop noise.

Abstract: Provided is a pulse density modulation value converter, comprising: a pulse density modulation reference point storage for storing a plurality of pulse density modulation reference points, each pulse density modulation reference point comprising a linear pulse density modulation value, an actual pulse density modulation value and/or an integral non-linear error value, wherein the integral non-linear error value is the difference between the actual pulse density modulation value and the linear pulse density modulation value; and a pulse density modulation value calculator for receiving a linear pulse density modulation value, searching the pulse density modulation reference point storage for a pair of pulse density modulation reference points closest to the linear pulse density modulation value, obtaining an actual pulse density modulation value corresponding to the linear pulse density modulation value through linear interpolation on the basis of the pair of pulse density modulation reference points, and outp

Abstract: This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronize any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (SOUT) from the modulator are thus synchronized to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronized to the first clock signal.

Abstract: This application relates to methods and apparatus for digital microphones. Disclosed is a digital microphone apparatus (300) for outputting a digital output signal (DATA) at a sample rate defined by a received clock signal (CLK). The apparatus includes a band splitter (302) configured to receive a microphone signal (SMD) indicative of an output of a microphone transducer and split said microphone signal into first signal path (SP1) for frequencies in a first band and a second signal path (SP2) for frequencies in a second band, the frequencies of the second band being higher than the frequencies in the first band. A modulation block (304) is configured to operate on the second signal path to apply a selective gain modulation to signals in the second signal path.

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device can serve as a current output DA converter. The semiconductor device converts a current corresponding to a digital signal into a voltage and then holds the voltage, which allows output of the analog voltage even after stopping supply of the current. A plurality of circuits that converts a current into a voltage is provided, whereby a settling time for changing the analog output voltage is reduced.

Abstract: This application relates to methods and apparatus for digital microphones. Disclosed is a digital microphone apparatus (300) for outputting a digital output signal (DATA) at a sample rate defined by a received clock signal (CLK). The apparatus includes a band splitter (302) configured to receive a microphone signal (SMD) indicative of an output of a microphone transducer and split said microphone signal into first signal path (SP1) for frequencies in a first band and a second signal path (SP2) for frequencies in a second band, the frequencies of the second band being higher than the frequencies in the first band. A modulation block (304) is configured to operate on the second signal path to down-convert signals in the second signal path from the second frequency band to a lower frequency band.

Abstract: An outphasing power amplifying device includes a switching signal generating circuit configured to generate a switching pulse signal for switching a class-D power amplifier from two types of sinusoidal wave generated based on amplitude and phase of a modulated wave to be transmitted. The switching signal generating circuit includes: a sin calculation unit and a cos calculation unit for converting phase information of the two types of sinusoidal wave into a quadrature format; a DA converter for converting the quadrature-format phase information; a first filter for removing an aliasing component from the analogue signal; an analogue quadrature modulator for generating a sinusoidal wave from the analogue signals by using a local signal; a second filter for allowing a radio frequency and a component in the vicinity thereof to pass therethrough; and a comparator for converting the sinusoidal wave into a switching pulse signal by comparison with a reference voltage.

Abstract: A method for operating an illumination system that includes at least one illumination device, a server configured to perform wireless communication with the illumination device, and a terminal configured to perform optical communication with the illumination device.

Abstract: A ternary pulse width modulation (“PWM”) method and apparatus. In one embodiment, the start of the pulse sequence in the “current” frame is referenced to the end of the pulse sequence in a previous, “reference” frame, rather than to the frame boundary at the start of the current frame, thereby allowing the compensation portion of the pulse sequence to overlap into the preceding or following frame, thus achieving a higher modulation index without dropping the compensation pulses. Although in most instantiations, the reference frame will be the frame immediately preceding in time the current frame, in other instances, the reference frame may be any frame preceding the current frame that falls within the constraints of the timing facility.

Abstract: The present application relates to a wireless signal decoding method, which is used to decode an electric signal converted from a wireless signal, where the decoding method includes the following steps: recording a duration of each level of the electric signal; calculating an average value of m maximum durations and an average value of n minimum durations, where m and n are positive integers and are determined by referring to a distribution percentage value of first binary bit values and a distribution percentage value of second binary bit values in data respectively; calculating a decision duration according to the first average value and the second average value; comparing the duration of each level with the decision duration, and according to a comparison result, determining a binary bit value represented by the level; and integrating all binary bit values to restore the data represented by the electric signal.

Abstract: A system and method for efficiently storing data in a storage system. A data storage subsystem includes multiple data storage locations on multiple storage devices in addition to at least one mapping table. A data storage controller determines whether data to store in the storage subsystem has one or more patterns of data intermingled with non-pattern data within an allocated block. Rather than store the one or more pattern on the storage devices, the controller stores information in a header on the storage devices. The information includes at least an offset for the first instance of a pattern, a pattern length, and an identification of the pattern. The data may be reconstructed for a corresponding read request from the information stored in the header.

Abstract: A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.

Abstract: A wireless transmitter is described herein that provides power wirelessly to an apparatus with high efficiency. For example, the wireless power transmitter may include a class E amplifier that is used as a gate driver for a main power amplifier. This advantageously enables power to be transmitted wirelessly with a 100% theoretical power efficiency and with minimal power loss. Furthermore, electromagnetic interference (EMI) issues are reduced because only low orders of harmonics are applied to the gate of the main power amplifier. A system that incorporates such a wireless transmitter and methods of operating the same are also described herein.

Abstract: A device includes a combining circuitry that receives an incoming signal, and one or more delayed signals from a delay circuitry. The combining circuitry combines the incoming signal and the one or more delayed signals to generate a combined signal. The device includes a comparing circuitry that receives the combined signal from the combining circuitry, and compares a pulse width of the combined signal to a threshold pulse width. When the pulse width of the combined signal is greater than or equal to the threshold pulse width, the comparing circuitry provides the combined signal to an amplifier circuit and provides a null signal to the delay circuitry. The amplifier circuit generates a pulse width modulated (PWM) signal based on the combined signal.

Abstract: A visible light communication (VLC) device and method for discovery and association with a VLC infrastructure node are disclosed. The VLC device is configured to receive a beacon frame from a VLC infrastructure node. The VLC device is further configured to transmit an association request to the VLC infrastructure node. The association request includes an indication of physical layer (PHY) capabilities and an indication of medium access control (MAC) capabilities of the VLC device. The VLC device is further configured to receive an association response from the VLC infrastructure node. The association response includes information for use in communicating with the VLC infrastructure node.

Abstract: The system and method for multi-wavelength optical signal detection enables the detection of optical signal levels significantly below those processed at the discrete circuit level by the use of mixed-signal processing methods implemented with integrated circuit technologies. The present invention is configured to detect and process small signals, which enables the reduction of the optical power required to stimulate detection networks, and lowers the required laser power to make specific measurements. The present invention provides an adaptation of active pixel networks combined with mixed-signal processing methods to provide an integer representation of the received signal as an output. The present invention also provides multi-wavelength laser detection circuits for use in various systems, such as a differential absorption light detection and ranging system.

Abstract: A PWM modulation device includes: a PWM modulator which receives upper N bits of an (N+1)-bit output from a noise shaper; a rising/falling edge detector which receives a PWM output signal of the PWM modulator and detects a rising/falling edge; a delay circuit which receives the PWM output signal, delays the PWM output signal by a predetermined delay time and outputs a PWM output delay signal; an AND gate which receives the lower one bit output from the noise shaper and an output control signal of the rising/falling edge detector; and a selector which receives a signal obtained as a result of an AND operation by the AND gate for the output control signal and the lower one bit and selects one of the PWM output signal and the PWM output delay signal.

Abstract: A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.

Abstract: A driving circuit for driving half bridge connected electrically controlled power switches with a near zero interlock delay time between on-states of the power switches, wherein the driving circuit is configured to receive an input signal and to generate: —a first drive signal being adapted to switch a first power switch between the on and off state, —a second drive signal being adapted to switch a second power switch between the on and off state, wherein the signal curve of the first drive signal generated in response to a rising and falling edge of said input signal is mirrored with respect to the signal curve of the second drive signal along a time axis of a mirroring voltage value within a transition time, wherein the mirroring voltage value is adjusted such to be within the cutoff region of the power switches.

Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system.

Abstract: In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: A power supply device includes a transformer including primary winding and secondary winding, a sensor configured to sense at least one of output voltage and output current in the power supply device, a pulse width modulation (PWM) controller configured to perform PWM switching so that voltage is selectively provided to the primary winding based on one of the sensed output voltage and output current, and a regulator configured to stop PWM switching of the PWM controller and keep the PWM switching in stopped state when at least one of the sensed output voltage and output current exceeds a preset value.

Abstract: Systems and methods are provided for performing noise filtering of a received signal. A first signal is received via a first receiver. A second signal is received via a second receiver. A combined signal based on the first and second signals is generated. The combined signal is processed to generate an adjusted combined signal. A phase adjustment is performed on the adjusted combined signal based on amplitude values of the adjusted combined signal during a period of time and an amplitude value of the first signal during the period of time. The phase-adjusted signal is subtracted from the first signal to generate a noise reference signal. The noise reference signal is subtracted from the combined signal to generate a filtered output signal.

Abstract: A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.

Abstract: Specifically provided is a light emitting device for image display, wherein each of light emitting elements, a PWM control unit which PWM-controls a current to be supplied to the light emitting element, a control condition setting unit which, according to the APL of image data, determines and updatably sets the PWM limiting condition for limiting the PWM value that is the duty ratio of the PWM control, and the reference current value that is the value of the current flowing to the light emitting element in response to turn-on of the PWM control, and a PWM value calculation unit which on the basis of the image data, the PWM limit condition, and the reference current value, calculates the PWM value of each area, and the PWM control unit performs the PWM control on the basis of the reference current value and the calculated PWM value.

Abstract: An embodiment of pulse width modulated (PWM) signal generator includes a module or modules to calculate an amount of change in a period length and duty ratio of an output signal during a transition period between a first signal waveform and a second signal waveform using a first period parameter, a second period parameter, and a parameter indicating a predetermined number of steps in the transition period. The period parameter and duty parameter of the output signal during the steps of the transition period are based on the calculated amounts of change.

Abstract: A method for controlling at least one switch in a power converter, wherein the switching speed of the switch dynamically varies according to a measurement of a quantity representative of the efficiency of the converter.

Abstract: A PCM signal is converted to a PWM signal using predistortion to alleviate harmonics. A PCM predistorted signal is converted to the PWM and amplified. A third harmonic nonlinear function receives the PCM signal and produces a third harmonic of the PCM signal. A third harmonic difference function takes one sixth of the third harmonic and produces a third harmonic PCM compensation signal. The PCM signal and the third harmonic PCM compensation signal are summed to produce a PCM predistorted signal for a full-bridge amplifier. A second harmonic nonlinear function produces a second harmonic of the PCM signal. A second harmonic function takes one fourth of the second harmonic to produce a second harmonic PCM compensation signal. The PCM signal, the third harmonic PCM compensation signal, and the second harmonic PCM compensation signal are summed to produce the PCM predistorted signal for a half-bridge amplifier.

Abstract: A method for providing cross point information includes: providing an input signal having amplitude and phase information; interpolating between a first point of the input signal and a second point of the input signal to provide cross point information between the first point and the second point; and providing a pulse-width modulated signal based on the input signal and the cross point information.

Abstract: A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

Abstract: A method for providing cross point information includes: providing an input signal having amplitude and phase information; interpolating between a first point of the input signal and a second point of the input signal to provide cross point information between the first point and the second point; and providing a pulse-width modulated signal based on the input signal and the cross point information.

Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.