Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.

Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

Abstract: A device for transmit (TX) training a remote link partner (LP) includes a TX retimer module adjacent to a TX port of the device, and a receive (RX) retimer module adjacent to the TX retimer module. The RX retimer module copies first control and status data to the TX retimer module, and the TX retimer module provides second control and status data for TX training of the remote LP.

Abstract: A signal equalizer for compensating impairments of an optical signal received through a link of a high speed optical communications network. At least one set of compensation vectors are computed for compensating at least two distinct types of impairments. A frequency domain processor is coupled to receive respective raw multi-bit in-phase (I) and quadrature (Q) sample streams of each received polarization of the optical signal. The frequency domain processor operates to digitally process the multi-bit sample streams, using the compensation vectors, to generate multi-bit estimates of symbols modulated onto each transmitted polarization of the optical signal. The frequency domain processor exhibits respective different responses to each one of the at least two distinct types of impairments.

Abstract: A processor, comprising a first data input configured to receive a stream of samples of a first signal having a spectral space, the stream having a data rate of at least 4 GHz; a second data input configured to receive a stream of samples of a second signal; a multitap correlator, configured to receive the first stream of samples and the second stream of samples, and producing at least one correlation output for each respective sequential sample of the first signal received; and a programmable control configured to alter a relationship of the stream of samples of the first signal and the stream of samples of the second signal, to thereby select, under program control, an alterable correlation output.

Abstract: A transmitting circuit is connected to a communication line and configured to transmit a primary signal, being a current signal, to the communication line by changing a current flowing from a transmission unit via the communication line. A receiving circuit is configured to receive a secondary signal which is generated by converting the primary signal transmitted from the transmitting circuit to a voltage signal by a current/voltage converter provided between the transmission unit and the communication line. Specifically, the primary signal, being a current signal transmitted from a communication terminal, is converted to the secondary signal being a voltage signal by the current/voltage converter. As a result, communication can be performed even when the impedance of the communication line is reduced, facilitating introduction of a communication system.

Abstract: A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.

Abstract: The various embodiments include methods and apparatuses for canceling nonlinear interference during concurrent communication of multi-technology wireless communication devices. Nonlinear interference may be estimated using a multilayer perceptron neural network with Hammerstein structure by dividing an aggressor signal into real and imaginary components, augmenting the components by weight factors, executing a linear combination of the augmented components, and executing a nonlinear sigmoid function for the combined components at a hidden layer of multilayer perceptron neural network to produce a hidden layer output signal. At an output layer, hidden layer output signals may be augmented by weight factors, and the augmented hidden layer output signals may be linearly combined to produce real and imaginary components of an estimated jammer signal.

Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.

Abstract: A method, an apparatus, and a transceiver for cancelling multi-carrier transmission interference are provided. The method includes: collecting a high order intermodulation signal in radio frequency signals output by a transmitter; processing the high order intermodulation signal so as to generate a first digital signal; establishing a high order intermodulation model by using the first digital signal and a first baseband signal output by the transmitter; generating a second digital signal by using a coefficient of the high order intermodulation model and a second baseband signal output by the transmitter; and counteracting interference in a digital signal output by a receiver with the second digital signal. By using the present invention, high order intermodulation interference of a multi-carrier transmitter on a receiver can be effectively canceled, and therefore, difficulty in duplexer design and requirements on a suppression degree are reduced.

Abstract: The invention relates to a method for communication between nodes in a wireless network further comprising a router node (2), comprising : a first (1) and second (3) transmitting nodes sending a first (a(t)) and second (b(t))data signals to be respectively transmitted to a first (4) and second (5) receiving nodes, the router node (2) receiving a mixed signal (MDATA[a,b](t)) resulting from interference of the first (a(t)) and second (b(t)) data signals, and sending respectively to the first (4) and second (5) receiving nodes a first and second router analog acknowledgment signals comprising information representative of the hearing duration during which the mixed signal has been received by the router node, the router node (2) sending the mixed signal(MDATA[a,b](t)) to the first (4) and the second (5) receiving nodes, the first (4) and second (5) receiving nodes decoding the mixed signal, based on the respective router analog acknowledgment signals.

Abstract: A receiving apparatus estimates a transmission channel of a signal through a training signal that is inserted into a data area of a received multipath signal, i.e., a mobile signal and a terrestrial signal that is coupled to the mobile signal, and estimates a transmission channel by detecting a received mobile signal using a previously equalized signal of a mobile signal and a transmitting signal corresponding to a terrestrial signal that is coupled to the mobile signal through determined data. Mobile signal data corresponding to training signal distortion existing in terrestrial signal data are compensated based on a channel estimation value.

Abstract: A method of characterizing a channel between a transmitter and a receiver (e.g., in a high-speed link) is presented. The method comprises: determining an overall intersymbol interference (ISI) probability density function (PDF) from eye monitor data obtained for a current equalizer setting, extracting a channel ISI PDF for the current equalizer setting from the overall ISI PDF, and generating an overall ISI PDF for a different equalizer setting by using the channel ISI PDF for the current equalizer setting and an impulse response at the different equalizer setting. Based on this characterization, an optimal equalizer setting may be selected among a plurality of equalizer settings on the basis of the channel ISI PDF and the equalizer response functions.

Abstract: Apparatus for generating an RF signal for use in RF signal detection is described. The apparatus comprises at least one processor configured to generate a set of IQ data based on at least one set of weighted IQ data, each set of weighted IQ data having a respective weight and a circuit configured to generate an RF signal using the set of IQ data.

Abstract: The present invention relates to the field of telephony and specifically to a method for correcting the degradation of telephone signal quality caused by analogue lines. The invention describes managing, via the receiver, a specific correction of telephone signal degradation caused by the length of the analogue line between the parties. Said line length between the receiver and the telephone switchboard to which said receiver is connected is stored in the receiver. Advantageously, the line lengths between the receiver of the called party and the corresponding switchboard are stored, for example in the director of the apparatus. During the call, said line length is taken into account by a specific correction means for said correction inside the receiver.

Abstract: A waveform equalization apparatus includes an A/D converter, a waveform equalizer, a training sequence generator, a clock recovery circuit, multiple matched filters, and a clock optimization logic. The A/D converter oversamples a reception signal in synchronization with a base clock signal and generates an A/D converted data sequence. The waveform equalizer performs an arithmetic operation to equalize a waveform. The training sequence generator generates a data sequence for training. The data sequence for training is used instead of an output data of the detector so as to converge a coefficient used in the arithmetic operation in advance. The clock recovery circuit supplies the base clock signal without executing a clock recovery operation during a training period, and executes the clock recovery operation according to the output data of the detector. The matched filters receive the A/D converted data sequence, and execute a filter arithmetic operation.

Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

Abstract: A multipath channel emulation system and method are disclosed. In some aspects, the system and method allow for analog emulation of a multipath MIMO wireless channel. Such multipath channel emulation system is used for testing the ability of wireless communication devices to operate in an airlink channel characterized by multipath. In a particular aspect, an impedance mismatch or discontinuity is provided in an open-ended coaxial cable so as to cause multiple back and forth reflections between an impedance discontinuity and an open coaxial cable stub and, optionally, including a delay element to emulate a multi-cluster multipath environment. A plurality of such stub subsystems may be combined as sub-paths in a multipath channel emulator.

Abstract: In some implementations, a circuit includes an operational amplifier having a positive input, a negative input, and an output, the output being connected to the negative input; a first capacitor to receive the input signal; a second capacitor connected in series with the first capacitor, the second capacitor to provide a first signal to a positive input of the operational amplifier; a first resistor connected in series with the first capacitor, the first resistor to provide a second signal to the negative input of the operational amplifier; a second resistor to receive the input signal; a third resistor connected in series with the second resistor, the third resistor to provide a third signal to the positive input of the operational amplifier; and a third capacitor connected in series with the second resistor, the third capacitor to provide a fourth signal to the negative input of the operational amplifier.

Abstract: A communication unit comprises a controller and a radio frequency signal path having a plurality of delay elements operably coupled to a series of respective amplifier stages, wherein the controller is arranged to individually enable the respective amplifier stages. In response thereto a number of the plurality of delay elements are selectively inserted into or by-passed from the radio frequency signal path thereby adjusting a phase shift applied to signals provided through the radio frequency signal path.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch.

Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

Abstract: A method and apparatus for automatic compensation of insertion loss in signals transmitted over conductors is presented. The present invention is particularly applicable to the transmission of signals over long lengths of CAT-5 or similar twisted-pair cables. A reference signal having a known form and strength (e.g. a pulse signal) is provided to each pair of conductors carrying a component of a signal from a transmitter to a receiver. The receiver includes adjustable gain amplifiers for each conductor pair over which a component of the signal is transmitted. The gains of the amplifiers are initially set at an initial level (e.g., their maximum gain) to allow detection of the reference signal. Once the reference signal is detected in a conductor pair, the amplifier gains are adjusted such that the level of the reference signal is restored approximately to its original form and strength.

Abstract: A skew adjusting apparatus includes: latching circuits that latch other signals in synchronism with transition timing of the signal level of a reference signal among signals transmitted with a plurality of communication cables; delay elements that are provided on the plurality of communication cables, and delay the signals transmitted with the plurality of communication cables, respectively; and a controller that controls the delay elements based on the outputs of the latching circuits to adjust skews between the signals.

Abstract: Multiple transmission inductors are formed over a substrate. A signal input channel is coupled to the multiple transmission inductors and a same transmission signal is inputted to the multiple transmission inductors. A phase difference control section is provided in the signal input channel and controls a phase difference of the signal between the transmission inductors by a unit smaller than 180°.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: Precision delay line instruments according to this disclosure may include a plurality of controller activatable delay loops of different delay length design values, and a controller configured to apply a selected delay setting by activating delay loops corresponding to the selected delay setting. The delay length design values may comprise a first set of delay lengths according to a first set of binary step values, and a second set of delay lengths according to a second set of binary step values that is offset from the first set of binary step values. Delay loops corresponding to selected delay settings may be identified in an operating data structure comprising best-fit matched combinations of delay loops that produce more accurate signal delays than one or more other combinations of delay loops.

Abstract: A sampling filter device wherein the filter characteristic is variable without using a control signal of a complicated waveform is provided. A sampling filter device 105 has integration capacitors 130 and 131, an integration time adjustment section 180, and a plurality of switches 100, 101, 110, and 111. Input current is integrated in different time duration with one clock and is stored in the integration capacitors 130 and 131 and charges stored in the integration capacitor from several clocks before to one clock before are added and the result is output. When charge is stored in the integration capacitors 130 and 131 with each clock, the integration time duration is changed, whereby it is made possible to weight and add output charge and the filter characteristic changes.

Abstract: Complex polyphase nonlinear equalizer (cpNLEQs) mitigate nonlinear distortions generated by complex in-phase/quadrature (I/Q) time-interleaved analog-to-digital converters (TIADCs). Example cpNLEQs upsample the digital waveform emitted by the TIADC, e.g., by a factor of two, then separate the upsampled digital waveform into upsampled in-phase and quadrature components. Processors in the cpNLEQs create real and imaginary nonlinear compensation terms from the upsampled in-phase and quadrature components. The nonlinear compensation terms are downsampled, and the downsampled imaginary nonlinear compensation term is phase-shifted, then combined with the downsampled real component to produce an estimated residual distortion. Subtracting the estimated residual distortion from the digital waveform emitted by the TIADC yields an equalized digital waveform suitable for further processing.

Abstract: Processor-implemented methods and systems for visually-assisted mixing of audio using a spectral analyzer are disclosed. The system calculates and displays a spectral view for each track in an arrangement in a multi-track view. A user can then request modification of the spectral view. In response to this request for modification, the system automatically adjusts associated mixing parameters for the modified track so that the spectral output of the track substantially matches the user-requested modified spectral view. This allows a user to visually mix an arrangement by imputing a desired spectral result and having the program make the changes necessary to achieve it.

Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Abstract: An adaptive filter includes: a filter configured to perform a filtering process for an input signal with a filter coefficient set therein, and output the processed input signal as an output signal; a calculating unit configured to calculate a value indicative of an error between an amplitude of the output signal and a reference amplitude; an output unit configured to output a first constant as a parameter when the amplitude of the output signal is greater than the predetermined amplitude, the parameter used when updating the filter coefficient, and output a second constant as the parameter when the amplitude of the output signal is smaller than the predetermined amplitude; and an updating unit configured to update the filter coefficient with an update amount corresponding to the parameter and the value indicative of the error, such that the error is reduced.

Abstract: An embodiment of an equalizer includes a voltage-to-current converter and a current-to-voltage converter. The voltage-to-current converter is configured to convert a differential input voltage to a differential current, and includes a differential amplifier with a first transistor and a second transistor, and a first source degeneration circuit coupled between the first transistor and the second transistor. An embodiment of the first source degeneration circuit includes a first resonant circuit. The current-to-voltage converter is coupled to the voltage-to-current converter, and is configured to convert the differential current to a differential output voltage. The current-to-voltage converter includes a first inverter with a first feedback circuit and a second inverter coupled to the first inverter, which includes a second feedback circuit. An embodiment of the first feedback circuit includes a second resonant circuit, and an embodiment of the second feedback circuit includes a third resonant circuit.

Abstract: Provided is a channel equalizing apparatus and method for improving channel equalization performance in an Orthogonal Frequency Division Multiplexing (OFDM) reception system applied to digital broadcasting or a communication system. The apparatus, includes: a channel estimating unit for performing channel estimation by using a pilot signal of a frequency domain; a digital filtering unit for changing a characteristic of a channel in a time domain based on an estimated channel estimation result; and a channel equalizing unit for performing channel equalization of a frequency domain on the signal after changing the channel characteristic.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: Techniques for operating a diversity receiver are described. A user equipment (UE) may include (i) a first receive chain having an equalizer and a first rake receiver and (ii) a second receive chain having a second rake receiver. The UE may support (i) a first mode in which only the equalizer is used to process a received transmission and (ii) a second mode in which both rake receivers are used to process the received transmission. The UE may determine a first performance metric for the first mode (e.g., based on the performance of the equalizer) and a second performance metric for the second mode (e.g., based on the performance of both rake receivers or only the first rake receiver). The UE may select the first or second mode based on the performance metrics and may power down the second receive chain if the first mode is selected.

Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

Abstract: A PAM-N decision feedback equalizer (DFE) comprises a coefficient computation unit; a feedback unit that mitigates, using computed feedback coefficients, effects of interference from data symbols; an error-and-decision unit for at least computing a least error value respective to one of a plurality of decision levels, wherein the least error value indicates a difference of a pseudo equalized input PAM-N data symbol from an optimal position of the one of the plurality of decision levels, wherein the one of the plurality of decision levels corresponds to a modulation level used to modulate data in the input PAM-N data symbol; and a calibration unit for adaptively setting the plurality of decision levels based, in part, on the least error value, thereby enabling for compensating for gain changes resulted by a cable on which the input PAM-N data symbol is received and further compensating for embedded offsets of the error-and-decision unit.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. The compensating is selectively locked and reset in response to specific conditions being detected, e.g., a locking condition and a reset condition.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: The present invention provides a signal processing device. The signal processing device includes a first feed forward equalizing unit, a first data slicing unit, a second feed forward equalizing unit, and a second data slicing unit. The first feed forward equalizing unit is utilized for performing a compensation operation according to a digital input signal so as to generate a first equalized signal. The first data slicing unit is coupled to the first feed forward equalizing unit, and utilized for generating a first output signal according to the first equalized signal. The second feed forward equalizing unit is coupled to the first data slicing unit, and utilized for generating a second equalized signal according to the first equalized signal. The second data slicing unit is coupled to the second feed forward equalizing unit, and utilized for generating a second output signal according to the second equalized signal.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: Methods and devices for phase shifting an RF signal for a base station antenna are provided. The device includes a transmission line that has a stationary ground plane coupled to the top of a substrate and a signal line on the bottom of the substrate. The signal line has an input port and an output port. The input port receives the RF signal with a certain phase and travels across the bottom of the substrate to the output port. The RF signal has a different phase at the output port because defected ground structures etched on the stationary ground plane shift the phase of the RF signal. In addition, the device includes a movable ground plane that may cover a portion of the defected ground structures, the substrate, and the stationary ground plane such that the moveable ground plane further adjusts the phase of the RF signal.

Abstract: According to an aspect of the embodiment, a signal transmission apparatus includes a sine wave output unit that outputs a sine wave to a transmission path, network analyzers and that analyze signals on the transmission path, an S parameter measurement unit that measures S parameters based on the analysis, a selection unit that selects a plurality of combinations of an amplitude, an emphasis characteristic, and an equalization characteristic based on the S parameters, measurement units that measure a BER or an eye opening of the transmission path for the plurality of combinations, and a setting unit that extracts single combination based on the measurement and that sets the amplitude, the emphasis characteristic, and the equalization characteristic to a transmission unit and a reception unit.

Abstract: In an RF signal transmission network such as the reverse channels of a coaxial cable network, there is provided at least one adaptive equalizer for pre- or post-filtering inter-symbol interference in the transmitted signals, the adaptive equalizer having a series of coefficients for which values are required. In order to improve the transmission efficiency the preamble used in these channels is shortened by coarsely estimating the channel using a short “unique word’ placed at the beginning of the equalizer training sequence. The coarse channel estimate is crudely inverted to produce a set of equalizer coefficients which partially equalize the channel. By initializing the adaptive equalizer with these approximate coefficients, it is possible to reduce the length of the training sequence needed for the equalizer to converge.