Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.

Abstract: The present invention relates to a waveform equalizer and a method for controlling the same, as well as a receiving apparatus and a method for controlling the same whereby better receiving characteristics are provided than before. In a filter 28, registers 911 through 915 delay an input DT1; multipliers 920 through 925 multiply outputs from the registers by filter coefficients C20 through C25 respectively; and adders 931 through 935 add up outputs from the multipliers to acquire DT2. A selector 81 either outputs a timing signal at intervals of a symbol period of DT1 to drive the filter 82 as a symbol rate equalizer, or outputs the timing signal at intervals of half the symbol period to operate the filter 82 as a fractionally spaced equalizer. The present invention may be applied to waveform equalizers performing waveform equalization of the input signal.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.

Abstract: An equalizer circuit receives digital amplitude data A[N] which represents the amplitude level of the N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and performs waveform shaping. The equalizer circuit includes: M (M is an integer) calculation units ECU1 through ECUm; and an adder ADD1 which adds the output data of the M calculation units ECU1 through ECUM and the amplitude data A[N] together so as to generate equalized amplitude data D[N]. A step response waveform RSTEP(t) for the transmission line is approximated by Expression RSTEP(t)=SSTEP(t)·(1?Sj=1:M fj(t)) using M (M is an integer of 2 or more) functions fj(t) (1?j?M) and a step waveform SSTEP(t) with the time t as an argument. The representative value of the function fj(t) in a range between T1 and T2 is represented by a function gj(T1, T2).

Abstract: A digital communication system, an indoor unit, and an outdoor unit in which characteristic variation due to temperature is small are provided. The digital communication system comprises an IDU 1 and an ODU 6 connected through a cable 8, in which the IDU 1 includes a slope equalizer 2 which applies a given frequency characteristic to a baseband signal, a DAC 3 which converts the baseband signal from digital form into analog form, and an AGC circuit 5 which amplifies the baseband signal converted from digital form into analog form with a given amplification factor and outputs the signal to the ODU 6, and the ODU 6 includes a power detection circuit 7 which detects a length of the cable 8, determines a frequency characteristic to be applied to the baseband signal and an amplification factor according to the detected length of the cable 8 and notifies the determined frequency characteristic and amplification factor to the slope equalizer 2 and the AGC circuit 5 respectively.

Abstract: The present invention relates to the field of communication devices, e.g. wireless communication devices. More particularly, the present invention relates to the field of signal equalization, especially minimum mean square error equalization. The present invention especially relates to an equalizer for a communication device, a method of equalizing one or more received signals and a software program product for carrying out the method. The present invention reduces the size of a look-up table needed for a division operation and, generally, provides for a reduced complexity of the equalizer and receiver.

Abstract: The equalizer presented includes a first feed-forward equalization module, a second feed-forward equalization module, and a phase error corrector. The first and the second feed-forward equalization modules respectively receives an input real-part component signal and an input imaginary-part component signal of a complex input signal and respectively equalizes the input real-part component signal and the input imaginary-part component signal to generate a first real-part component signal and a first imaginary-part component signal. The phase error corrector is coupled to the first and the second feed-forward equalization modules for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information.

Abstract: An equalizer and a related equalizing method for equalizing signal reflection caused by a stub at a transmitting end are provided. The equalizer includes a summing device and a delay device. The summing device is utilized for adding a feedback delay signal to the input signal to generate the equalized signal. The delay device is coupled to the summing device, and utilized for delaying the equalized signal to generate the feedback delay signal. Wherein the delay device has a variable delay time and the variable delay time is a non-integer multiple of a bit time of the input signal.

Abstract: In a transmission diversity control method in which a request to start or stop transmission diversity is issued by a reception station to a transmission station having a transmission diversity function, the reception station is provided with an equalizer to reduce multipath interference on the basis of a signal correlation, a transmission diversity start request is issued from the reception station to the transmission station when an effect generated by the equalizer is small, and a transmission diversity stop request is issued from the reception station to the transmission station when the effect generated by the equalizer is large.

Abstract: The present invention relates to a receiver apparatus and method of channel estimation in a telecommunication system which provides at least two pilot sequences, and to a computer program product. Channel estimation is achieved by estimating channel taps separately for each of the at least two pilot sequences in every transmission block, and for applying estimated channel taps obtained from the estimation to at least one of a temporal and spatial filtering or combining operation to refine the channel estimate. Accordingly, temporal correlations and cross-correlations of the at least two pilot sequences are exploited without requiring knowledge of path delays and beamforming parameters.

Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.

Abstract: A system and apparatus for compensating cable losses in a video signal transmission system includes feedback circuits to determine the spectral attenuation of a received signal and to control an equalizer circuit to amplify selected frequencies of the received signal, and to determine the various times of arrival of two or more video signals and selectively adjust one or more delay lines to reduce the differences in their arrival times.

Abstract: Tap coefficients of an FIR filter are prevented from converging to wrong values. A waveform equalizer for performing waveform equalization of an input signal and outputting a waveform equalization result as an output signal includes: an FIR filter for performing a convolution operation between the input signal and a plurality of tap coefficients; an IIR filter for performing a convolution operation between the output signal and a plurality of tap coefficients; an adding section for adding an operation result of the FIR filter and an operation result of the IIR filter and outputting an addition result as the output signal; an error detecting section for detecting an error of the output signal; and a tap coefficient updating section for updating respective tap coefficients of the FIR filter and the IIR filter based on the error.

Abstract: An adaptive cable equalizer includes a data signal input unit, a clock signal input unit, a variable equalizer that inputs a data signal input from the data signal input unit, and a transition time measuring portion that measures a transition time of a data signal output from the variable equalizer, with an equalizer control loop being configured that controls characteristics of the variable equalizer based on the output signal of the transition time measuring portion. The adaptive cable equalizer further includes a control circuit that controls response characteristics of the control loop according to the frequency of a clock signal input from the clock signal input unit. This enables a quick response at fast transfer rates by making the relationship between the response time of the control loop and the number of data bits substantially constant even when the transfer rate changes from a slow transfer rate to a fast transfer rate.

Abstract: A bass and treble audio tone control circuit configured as an integrated circuit, wherein a capacitor for setting a frequency band can be accommodated in an integrated circuit. A LPF extracts a low sound region component SLO from an initial sound signal SIN. A low sound region adjustment circuit adjusts the gain of SLO and generates signal SLT. An inverting circuit inverts SLO and an adding circuit extracts a high sound region component SHO by adding the inverted SLO and SIN. A high sound region adjustment circuit adjusts the gain of SHO and generates a signal SHT. A synthesizing circuit synthesizes SIN with SHT and SLT, and generates an output sound signal SOUT. The LPF is composed of an RC active filter, and the resistance that establishes the cutoff frequency is composed of an equivalent resistance using a switched capacitor circuit.

Abstract: A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.

Abstract: Method and apparatus for data reception are provided, retrieving digital values transmitted through a cable. In a data receiver, an equalizer equalizes an input signal based on a boost value to generate an equalized signal, and a data extractor samples the equalized signal to extract output values from each symbol period. The data extractor detects signal quality of the equalized signal to adjust the boost value accordingly. An optimal time point is detected within one symbol period where an output value is an ensured valid, and variation rate of the optimal time point is counted as an inverse indicator of the signal quality.

Abstract: A method and an apparatus for slicing an analog signal using an analog encoder.

Abstract: Aspects of a method and system for transmission and/or reception of signals utilizing a delay circuit and a DDFS are provided. In this regard, a first signal may be delayed by 90°, via a plurality of delay elements and variable capacitance, to generate a second signal. The first and second signal may be mixed to generate a first LO signal, which may be utilized for a first frequency conversion. A second LO signal may be generated via a DDFS and may be utilized for a second frequency conversion. A digital input word of the DDFS, a value of the variable capacitance, and/or at least a portion of the delay elements, may be programmatically controlled based on a desired frequency for transmission and/or desired frequency for reception. The first frequency conversions may be up-conversions and/or down-conversions to/from baseband, one or more intermediate frequencies, and/or RF.

Abstract: A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC) is described. In one embodiment, which both the AEQ and AEC process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the AEC using independent analog error signals.

Abstract: A delay line for deployment in an equalizer to insert a delay in a signal received by the delay line employs a plurality of cascaded delay stages where the delay per stage provided by an active unit-gain amplifier in each stage that provides sufficient impedance mismatch between the delay stages without substantial deterioration of the frequency response of the client signal undergoing deterioration of the frequency response of the client signal undergoing delay.

Abstract: A method and an apparatus for slicing a multilevel analog signal using a two-level slicer having one threshold level to generate an analog error signal. The method may be performed by delaying a received multilevel analog signal in a plurality of serial analog stages (n), further delaying a multilevel analog signal tapped from stage n, combining the further delayed signal from stage n with an analog error signal e(t) to provide an analog weighting function Wn, wherein the combining of the delayed signal from stage n with Wn results in a plurality of signals XnWn, summing the plurality of signals XnWn, slicing a multilevel analog signal resulting from the summing of the plurality of signals XnWn using one threshold level to generate the analog error signal e(t), and combining the delayed signal from stage n with Wn.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic tuning circuit for a continuous-time equalizer (CTE). In some embodiments, the automatic tuning circuit automatically tunes the magnitude response as a function of frequency of the CTE.

Abstract: A parallel equalizer for a DS-CDMA UWB system and method thereof are provided. The parallel equalizer includes: a filter block for filtering a training input signal in a ‘training mode’, and filtering the plurality of input signals in parallel in a ‘symbol decision mode’; a symbol decision block for obtaining a symbol error based on a output from the filter block and a training symbol in the ‘training mode’, and estimating a transmission symbol for each of the input signals in the ‘symbol decision mode’, obtaining an error of one among the estimated transmission symbols for a symbol error calculating input signal; and an weight update block for updating a filter tap coefficients of the filter block based on the training input signal or the symbol error calculating input signal and the symbol error and transmitting the updated filter tap coefficients into the filter block.

Abstract: In a signal processing apparatus adapted to process a signal transmitted via a transmission path, distortion of a waveform of a signal value of a specific symbol is predicted on the basis of a characteristic of distortion depending on values of symbols transmitted before the specific symbol, and the distortion is removed from the waveform of the received signal thereby producing a distortion-removed waveform. A comparison value is calculated for each allowable value of the specific symbol by subtracting a predicted signal value of the specific value from the distortion-removed waveform. A symbol value corresponding to the smallest comparison value is determined as the value of the specific symbol. An error suspicion level value indicating the degree of suspicion of being incorrect is calculated for each of the predetermined number of symbols, and already determined values of symbols are corrected in accordance with the error suspicion level values.

Abstract: A configurable receiver and a method for configuring a receiver, the method includes: (i) evaluating multiple nonzero taps allocations, wherein each nonzero taps allocation evaluation includes: (i.a) allocating nonzero taps between multiple sparse equalizers, wherein different sparse equalizers are expected to equalize signals transmitted over different channels; wherein each channel is associated with an information source out of multiple information sources and with a receiving antenna out of multiple receiving antennas; wherein the number of nonzero taps is bounded by a upper limit; and (i.b) calculating multiple channel reception parameters of the multiple channels in response to the nonzero taps allocation; and (ii) configuring the receiver in response to a comparison between reception parameters obtained during different nonzero taps allocations.

Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Abstract: Embodiments of a multicarrier receiver and method for generating soft bits in a multiple-input multiple-output system are generally described herein. In some embodiments, operational parameters for an equalizer and a soft-bit demapper in a multicarrier receiver are determined. Other embodiments may be described and claimed.

Abstract: A method having enhanced decoding operations associated with receiving multiple Radio Frequency (RF) Burst(s) is provided. Multiple RF burst(s) are received where the multiple RF Burst(s) include first RF bursts and second RF Burst(s). The second RF bursts may be transmitted in parallel or in response to a decoding error associated with the first RF burst. The received RF burst(s) are equalized and deinterleaved to yield extracted soft samples. Then the first estimated bit sequences and second estimated bit sequences are decoded from the extracted soft samples. A set of possible bit sequences may then be pruned based on based on combined knowledge of the first estimated bit sequence and the second estimated bit sequences. This pruned set may be compared using a sequence detector and the combined first estimated bit sequences and second estimated bit sequences to select a decoded bit sequence.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

Abstract: The feedback of reinterleaved correctly decoded data blocks to a decoder is provided for use in channel decoding operations of channel coded word containing data block. Once a properly decoded data block has been determined, feedback of constraints on the estimated bit sequences decoded data characteristics to a turbo decoder assist in additional decoding operations. Estimated bit sequences may be selected from those trellises that pass through the constraint imposed by knowledge of re-interleaving properly decoded data blocks. This allows the decoder to generate solutions having a minimum probability of error that are also confined by the re-interleaved properly decoded data blocks.

Abstract: Equalizers are provided including an N-tap feed forward filter, an M-tap feed backward filter, an L-tap filter, a control unit and an accumulator. The control unit is configured to connect the L-tap filter to the N-tap feed forward filter or the M-tap feed backward filter based on multipath information present in a communications channel. The accumulator is configured to sum output signals from at least one of the N-tap feed forward filter, the M-tap feed backward filter and the L-tap filter and to output a summation result. Related digital receivers, methods and computer program products are also provided.

Abstract: An integrated circuit arrangement (1; 2; 3; 4) for setting a predefined phase difference (phi_target) between a first high-frequency signal (x1; x1p, x1n) and a second high-frequency signal (x2; x2p, x2n), comprising: e) a chain connection of a plurality (N) of basic circuits (10; 20; 30; 40), whereby each basic circuit has a first transmission line (11; 11p, 11n) for transmitting the first signal (x1; x1p, x1n), a second transmission line (12; 12p, 12n) for transmitting the second signal (x2; x2p, x2n), and a controllable phase-influencing means (13; 23; 33; 43), connected to the first transmission line, for controllably influencing the phase of the first signal, f) a phase difference detector (14; 34), which is connected to the output-side basic circuit and is formed to detect a current phase difference (phi_actual) between the first and second signal, g) a control unit (15; 35), which is connected to the phase difference detector and each controllable phase-influencing means (13; 23; 33; 43) and is formed

Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.

Abstract: Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.

Abstract: In an equalizing filter circuit having an input terminal 101, an output terminal 102, delay devices 104 connected in multi-stage to the input terminal 101, and a plurality of weighting circuits 105 which are branched from and connected to the plurality of delay devices to thereby combine respective output signals of the weighting circuits, gain adjustment of the weighting circuits is performed to determine a coefficient of the equalizing filter circuit without depending on a load connected to the output terminal. Thus, an amount of compensation for a distorted waveform may be enhanced. To this end, an impedance converting circuit 108 is connected between at least one weighting circuit and the output terminal.

Abstract: There is disclosed a continuously variable equalizer. The continuously variable equalizer may include a series-tuned circuit connected between an RF signal input terminal and an RF signal output terminal. An adjustable T-pad may have an input terminal coupled to the RF signal input terminal, an output terminal coupled to the RF signal output terminal, and a common terminal. A parallel-tuned circuit may be coupled between the T-pad common terminal and a signal return.

Abstract: Embodiments of a programmable passive equalizer are described herein.

Abstract: A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE). An input data stream (DATA) is sliced into an even data stream and an odd data stream. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, half of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is then summed in current mode with the feedback data and converted to voltage prior to sampling of the currently received data bit.

Abstract: An equalizer may use a passive input stage to improve linearity and reduce power consumption. In addition, the equalizer may use two gain circuits, one in a high frequency amplification path and the other in an all-pass path. The relative proportion of all-pass to high frequency amplification may be adjusted using a single control signal. The equalizer may provide 20 dB of peaking at 5 GHz with good linearity, using CMOS technology.

Abstract: Tap coefficients of an FIR filter are prevented from converging to wrong values. A waveform equalizer for performing waveform equalization of an input signal and outputting a waveform equalization result as an output signal includes: an FIR filter for performing a convolution operation between the input signal and a plurality of tap coefficients; an IIR filter for performing a convolution operation between the output signal and a plurality of tap coefficients; an adding section for adding an operation result of the FIR filter and an operation result of the IIR filter and outputting an addition result as the output signal; an error detecting section for detecting an error of the output signal; and a tap coefficient updating section for updating respective tap coefficients of the FIR filter and the IIR filter based on the error.

Abstract: An equalizing filter circuit includes a first transmission line in which a plurality of first delay devices 104a are connected in cascade to input terminal 101, a second transmission line in which a plurality of second delay devices 107a are connected in cascade to output terminal 102, a plurality of weighting circuits 105a connected in parallel between the first transmission line and the second transmission line and having a gain which is adjustable by setting coefficients, and variable adjusting circuit 108a arranged at the output side of at least one of weighting circuits 105a for correcting a fluctuation of the output characteristics of the weighting circuits.

Abstract: Some embodiments of the invention include apparatus, systems, and methods to adjust a clock generator and an equalizer to reduce jitter in an output signal. A phase detector provides feedback information on a first feedback loop and a second feedback loop. A clock adjustment circuit uses the feedback information on the first feedback loop to adjust a clock generator. An equalizer adjustment circuit uses the feedback information on the second feedback loop to adjust the equalizer. Other embodiments are described and claimed.

Abstract: A transmission characteristic adjustment device and the like that can carry out circuit adjustment before an error occurs, and has a transmission characteristic with high reliability without generating an error are provided. The device determines existence or non-existence of a difference with respect to confirmed data based on each phase of a multiphase clock, detects a window width in a time axis direction of receiving data based on a result of the determination and a phase of the multiphase clock, and evaluates a setting value of a circuit element of the transmission element or the reception element that has an influence on a receiving waveform based on a fluctuation of the detected window width, and changes the setting value of the circuit element of the transmission element or the reception element based on a result of the evaluation.

Abstract: An adaptive channel equalization technique and method for wideband passive receivers is disclosed that reduces and tends to minimize distortions caused by circuitry within passive digital receivers. This equalization architecture provides an adaptive equalization solution for a wideband passive channel that receives unknown signals from the RF environment both temporally and spectrally. A wideband chirp signal or calibration signal is periodically injected to capture the spectral response of the receiver channel as it varies from the distortions induced over time and temperature for synthesis of equalization filter coefficients. Thus, the channel equalization is performed independent of receiver signal source and is employed to minimize digital receiver signal measurement distortions across the passband by providing an equalization filter whose magnitude and phase response compensates for the channel distortions of the passive data collection system.

Abstract: A waveform equalizer includes: a calculation circuit (7a) that permits free setting of the boost factor by which the gain, in a predetermined frequency range, for the input signal by varying the boost factor; and an all-pass filter (7b) that is connected to the stage preceding or following the calculation circuit, that has a first conductance amplifier and a second conductance amplifier, and that adjusts and thereby corrects the group delay characteristic of the input signal by varying the conductance of at least one of the first and second conductance amplifiers.

Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.

Abstract: A method for manufacturing an equalizer. The method first acquires a transmission line scattering-parameter, and a gain of the transmission line scattering-parameter at a frequency 1 ? ? ? ? , in which the gain represents an ideal gain; next, performs an integration about the transmission line scattering-parameter, the ideal gain and an equalizer scattering-parameter, and performs a differentiation about the transmission line scattering-parameter and the equalizer scattering-parameter to get the component impedances of the equalizer. Then manufacture the equalizer circuit with the derived component impedances.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.