Abstract: Receivers and methods for receiving a signal may result in improved performance by resolving specific impairments at particular levels. For example, bit error ratio (BER) in the downstream signal of an HFC network may be improved by resolving up to 6% AM hum. Thus, the receivers and methods described herein may function with dramatically improved error rates and continuous FEC lock, in relation to conventional receivers, in the presence of SCTE 40 impairments and full channel loading over the receivers entire input dynamic range.

Abstract: An adaptive digital filter includes a filtering circuit and a coefficient renewal circuit. The filtering circuit has a coefficient a defined by a fundamental formula: a[n+1]=a[n]+?·e[n]·q[n]/p[n]. ? is a number greater than 0 and smaller than 2, e[n] is a difference between the input and the output of the filter, and q[n] and p[n] are formulas. The renewal circuit calculates a renewal value of the coefficient a. The coefficient renewal circuit calculates 2m (m is an integer) greater than p[n] in the fundamental formula, and also calculates the renewal value of the coefficient a in accordance with an execution formula: a[n+1]=a[n]+?·e[n]·q[n]/2m in place of the fundamental formula.

Abstract: A thermal pad controlled equalizer that adjusts the slope and gain of an amplifier in response to changes in ambient temperature, effectively simulating automatic gain control. The equalizer has a slope pad and a gain pad. The slope pad increases the attenuation of the signal in response to increases in ambient temperature. The gain pad decreases the attenuation when ambient temperature increases. Thus, the slope and gain pads together compensate for temperature effects on the system.

Abstract: A testing apparatus for testing a device under test is provided, wherein the testing apparatus includes: a comparator for receiving a signal output from the device under test and converting the signal into a logic signal by comparing the signal with a first reference voltage; a driver for amplifying a logic signal to be output to the device under test on the basis of a second reference voltage and outputting to the device under test; a comparator setting unit for determining the first reference voltage so as to compensate for a delay amount of a reception signal received from the device under test and setting the comparator to be the first reference voltage; and a driver setting unit for determining the second reference voltage on the basis of the reference voltage of the comparator and setting the driver to be the second reference voltage.

Abstract: A transmission line is provided with added shunt resistance, RSH, distributed along the length of the micro transmission line permitting the extension of constant characteristic impedance to the transmission line to lower signal frequencies. The loss in gain to the signal propagating the transmission line due to the added resistance can be compensated for by amplification provided at the output of the transmission line or at output taps provided along the length of the transmission line such as in cases where the line is utilized as a circuit delay line. An exemplified application disclosed is an analog delay line formed as a metal microstrip in an IC chip circuit provided, for example, in a feed forward equalizer (FFE).

Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

Abstract: Attenuation compensation volume computing means (60, 61, 62, 63, 67, 68, 69, 70) of a signal receiver computes attenuation compensation volume of a video signal (GL, GH) on the basis of attenuation of pulses which are arranged in a digital sound signal LRD from the signal transmitter, and video signal attenuation compensation means (60, 61) of the signal receiver compensates the attenuation of the video signal (RAT, GAT, BAT) on the basis of the computed attenuation compensation volume (GL, GH), thereby stably compensating the attenuation of the video signal irrespective of kinds of displays or resolution of an image, and outputting good sounds to a video output machine as well as good videos.

Abstract: A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC), which both process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the AEC using independent analog error signals.

Abstract: Channel equalization in a 1000BASE-T receiver is performed by a fixed mode analog filter 2 suitable for the longest possible cable length, by a FFE (3), and by a digital filter 4. The digital filter (4) has two sets of taps. One set is optimal for shorter cable lengths and so cancels adaptation for long cable lengths and assists operation of the analog filter. A decision block (5) selects an appropriate set of taps.

Abstract: Embodiments of a programmable passive equalizer are described herein.

Abstract: Various methods and apparatus are described that use a filter. A receiver may be configured to receive multi-tone signals. The receiver has a Time Domain Equalizer filter employing an algorithm to shorten a length of an incoming impulse response to equal to or less than a guard period by calculating a minimum mean square error solution in combination with measuring an inter-symbol interference of a channel.

Abstract: A method for use in an equalization of a channel by means of an equalizer 22, 23 is shown, wherein the channel uses a certain frequency band for a transfer of signals. In order to enable a channel equalization which requires a low complexity and which provides at the same time a good performance, the method determines a channel response for at least one frequency point within the frequency band used by the channel. The method further sets at least one adjustable coefficient (?0k, bck, brk, a0k, a1k, a2k of the equalizer such that an equalizer response compensates optimally the determined channel response at the at least one selected frequency point. Also shown is a corresponding signal processing device 2, a corresponding signal processing system and a corresponding software program product.

Abstract: Disclosed is a channel equalizing apparatus and method for a digital television receiver that performs channel equalization using equalizing algorithms. The channel equalizing apparatus includes a channel equalizing section for compensating for channel distortion using a blind algorithm and a decision directed algorithm among equalizing algorithms, and a equalizing control section for calculating error values for compensating for the channel distortion from the blind algorithm and the decision directed algorithm and controlling the channel equalizing section to compensate for the channel distortion according to the calculated error values.

Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.

Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.

Abstract: A temperature compensated variable tilt equalizer configured to operate over a defined frequency range. The equalizer includes an RF input, an automatic temperature compensation circuit and a manual alignment circuit. The RF input receives an RF signal having a wide passband. The automatic temperature compensation circuit has an adjustable compensation range used to correct temperature-related tilt variances that occur on the passband of the RF signal over the defined frequency range. The manual alignment circuit is used to manually adjust tilt of the passband of the RF signal over the defined frequency range at a normal temperature. The variable tilt equalizer does not require a power source other than the RF signal.

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+?[sgn{d(t)}?sgn{z(t)?Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, ? determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

Abstract: A correlative error detection system (60) for a signal equalizer (10) that corrects a distorted communications signal. The detection system (60) correlates a sequence of bits in a signal from an FFE and/or a DFE processor (12, 14) with a predetermined sequence of correlation values. The detection system (60) includes a summing network (66) that sums the correlated signals. If the sequence of signal bits matches the sequence of correlation values, then the summed correlated signal will include a signal maxima. A peak detector (76) detects and holds the signal maxima so that a slow speed weight computer (40) can process the signal values to set weight values in the processors (12, 14). By knowing how often the sequence of bits that match the correlative values should occur in a random bit stream for an undistorted signal, the weight computer (40) can set the weight values to provide that magnitude of the bit sequence.

Abstract: A distributor 103 distributes an input signal into two lines of distributed signals with equal amplitudes and equal phases. Buffers 104, 105 suppress interference between distributed signals distributed into the two lines. A filter 106 performs a frequency selection which allows only a distributed signal in a predetermined band to pass. A differential amplifier 107 outputs a difference in amplitude components between a distributed signal frequency-selected by the filter 106 and the distributed signal which is not frequency-selected. This allows an attenuation characteristic or passage characteristic in a high-frequency band to be maintained.

Abstract: Equalisation of a communication channel is achieved through use of a Wiener filter frequency response mechanism that operates to transform at least a portion of a data stream generated from a plurality of space time coded (STC) symbol streams received from a plurality of transmit antenna elements into a packet spectrum. A training sequence for a channel through which the symbol streams have been sent is also transformed to a channel impulse response spectrum in order to assess the channel impulse response for the channel. The packet spectrum is equalised with the channel impulse response spectrum to produce an equalised packet spectrum in the transform domain. This is then converted into a time domain equalised data stream for recovery of originally transmitted information.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

Abstract: A circuit and method for receiving digital signals are disclosed. The circuit includes an input connected to a communications channel over which a digital signal is communicated and operates a plurality of multiple decision circuits at a frequency that is a fraction of the bit rate of the digital signal. A feedback and/or equalizer circuit receives the output of the decision circuits and applies a feedback signal to the input of the decision circuits that is representative of a combination of output signals of the decision circuits. The result is seen to improve the noise margin for correctly interpreting signals communicated over a communications channel having a low-pass characteristic.

Abstract: The present invention relates to a regulator for impedance balancing of first (104) and second wires (106) of a transmission wire pair having respective first and second impedances, the regular comprising: means (108) for determining a first signal (116) being representative of an average of square value of a first current (i1) flowing through the first wire, means (118) for determining a second signal (126) being representative of the average of square value of a second current (i2) flowing through the second wire, means (128, 130) for determining first and second coefficients (k1, k2) on the basis of the first and second signals, first feedback means (132, 134, 136) for regulating the first current on the basis of the first coefficient, second feedback means (138, 140, 142) for regulating the second current on the basis of the second coefficient.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: An in-phase and guadrature (IQ) imbalance error-correction method includes estimating, on the basis of a constellation error in a received orthogonal frequency division multiplexing (OFDM) signal, an extent of an I/Q imbalance error, caused by direct IQ conversion of the received OFDM signal. On the basis of that extent, an equalizing transformation that reduces that error is estimated.

Abstract: A data communication receiver comprises an equalizer for adapting to each of a plurality of channels to open the eye for each channel in a Gigabit (1000BASE-T) transceiver. The eye is open for a first channel (A) and a transformation process applies the coefficients of that adaptation to open the eye for the other dimensions. The transformation process keeps the magnitude response constant.

Abstract: A multi-bit time-delay adjuster with Radio Frequency (RF) MicroElectroMechanical (MEM) switches may be used in MultiCarrier Power Amplifiers (MCPAs) with a feed-forward linearization technique. The multi-bit time-delay adjuster makes it possible to automatically control a time-delay match with very high precision typically required in feed-forward MCPAs. A searching process for the automatic control of time-delay match is also introduced.

Abstract: A channel decoder employs a hybrid frequency-time domain equalizer for effectively combining a frequency domain equalizer with a time domain equalizer to achieve superior static and dynamic multi-path performance compared to conventional decision feedback equalizers. A frequency domain equalizer structure is included within the forward path of a time domain, decision feedback equalizer, with both the frequency domain and time domain portions employing a common error vector. Updates to the taps (frequency bins) may be adapted individually, or fully within the frequency domain without altering the feedback filter. Improved performance, including performance for noisy channels with deep notches, is achieved, and the frequency domain equalizer portion is relieved from equalizing minimum phase zeros of the channel.

Abstract: A forward signal equalizer for a forward amplifier for two-way coaxial cable systems, of the type having a distribution center distributing forward signals, and having reception facilities for receiving return signals from said cable system, the system having forward amplifiers for receiving forward signals, and having return amplifiers, and the forward signal equalizers are settable to provide varying amplifier specifications, and having receptacles for receiving plug-in equalizer components for varying the specifications of the forward amplifier, the equalizer components having a range of varying performance characteristics so that a component can be selected and plugged in to the forward signal equalizer to produce the performance specifications desired at a predetermined location in the cable system.

Abstract: An adjustable phase shifter generates a phase shifted reference signal by introducing a phase shift in a reference signal. A phase detector identifies a phase difference between the reference signal and the phase shifted reference signal. A control signal generator generates a plurality of control signals, each of which causes the adjustable phase shifter to adjust a magnitude of at least one component value in the adjustable phase shifter. The phase shift introduced by the adjustable phase shifter is based at least partially on the magnitude of the at least one component value in the adjustable phase shifter. The control signal generator also selects one of the control signals, where the selected control signal causes the adjustable phase shifter to produce the phase shifted reference signal such that the phase difference attains a specified value. The analog filter adjusts a magnitude of at least one component value in the analog filter based at least partially on the selected control signal.

Abstract: A current mode output driver includes a pre-driver for pre-equalization. The current mode output driver drives a transmission line with an alternating current (AC) signal and a direct current (DC) signal. Characteristics of the transmission line are measured by comparing a received amplitude of the AC signal and a received amplitude of the DC signal. A ratio of the AC received amplitude to the DC received amplitude is compared to ratios derived from possible equalization settings to determine an equalization setting appropriate to equalize the channel.

Abstract: The present invention provides a transmission system having a signal source which has an internal resistance, having a signal transmission line (102), one end of which is connected to the signal source, and having a terminating resistance which is connected to another end of the signal transmission line (102), the internal resistance of the signal source and the terminating resistance being complex and being chosen such that frequency-dependent signal attenuation in the transmission system is reduced in a frequency range which contains the frequencies of signals which are produced by the signal source.

Abstract: The invention relates to a method for equalizing a signal with a frame structure, received via a time-variable transmission channel. According to said method, a frame-type equalization is used. The channel unit pulse response is analyzed and one equalization alternative is selected from several provided alternatives. According to the principle of equalization with decision feedback, it is preferable if only two alternatives are provided; a conventional forward equalization and an inverse-time reversed equalization. A decision in favor of one or the other of these alternatives can be made simply based on the sign characterizing the so-called skewness.

Abstract: An electromagnetic borehole telemetry system providing improved signal to noise ratio. Adaptive filters use noise channels as references to remove noise from the signal channel. Multiple noise channels are coupled to series connected adaptive filters for removing each noise source from the signal channel. The order of noise removal is selected to remove the most significant first.

Abstract: Adaptive analog equalization. The present invention provides an analog equalization solution that is assured to converge irrespective of the initial conditions of the adaptation. For very high frequency communication applications, including DS3 or E3 line code applications operating at frequencies approaching 45 MHz, the analog adaptive equalization employs double sampling. One of the samples is used to make the decision if a transition actually goes to zero, and the other of the samples is used to drive the adaptation loop to converge. The present invention employs a high pass network and an adaptable gain to control an adaptive analog equalizer structure. There are two different feedback paths to ensure convergence of the present invention. In one embodiment, one feedback path is the gain control feedback path that is provided to the adaptive analog equalizer structure. The other feedback path is provided to a variable gain amplifier.

Abstract: A signal equalizer that employs micro-electromechanical machine devices for the tap weight controllers. The equalizer includes a substrate on which is formed a forward transmission line rail and a return transmission line rail. A cantilever stanchion is also formed on the substrate that runs parallel with the transmission line rails. A series of spaced apart cantilevers are pivotally mounted to the cantilever stanchion, and extend over the transmission line rails to define a gap therebetween. A weight tap line is coupled to each cantilever, and is responsive to a DC weight signal that controls the position of the cantilever to set the gap between the cantilever and the transmission line rails. A distorted signal is coupled from the forward transmission line rail to the return transmission line rail through the cantilevers.

Abstract: An error propagation detection method and apparatus for use in decision feedback equalization type detection is disclosed, with which it is possible to detect error propagation even when a specific code conversion rule is satisfied in an MDFE system. If the input signal of a comparative decider be a binary signal a(k) expressed as ±1, an error signal ev(k) expressed by ev(k)=[y(k)−Ideal y(k)] sign[a(k)] is determined using a(k−1)≠a(k+1) as an error computation condition. The error signal ev(k) thus determined is checked to see whether it exceeds a specific value. If so, the slice level of the comparative decider is controlled to a corresponding offset value.

Abstract: The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format.

Abstract: The invention relates to an equalizing device (62) intended to be used in a signal processing device (30) of a cable distribution network (1). The equalizing device according to the invention comprises two branches (B1, B2) brought together at the input (IN) and output (OUT) via two diplexers (SS, RC). At least either of the two branches includes an attenuator (V1, V2, V3). The passband of the two diplexers is determined to compensate for the faults caused by the distribution network. Advantageously, either of the two branches comprises an attenuator which is adjustable. The control of the adjustable attenuator is local or remote. The shape of the frequency response of such an equalizing device is regular when the value of the attenuation varies.

Abstract: A semiconductor integrated circuit device serving as a signal source, another semiconductor integrated circuit device serving as a destination and a transmission line form in combination a communication system; the transmission line is connected between a transmitting circuit of the semiconductor integrated circuit device and a receiving circuit of the other semiconductor integrated circuit device; equalizers are incorporated in the transmitting circuit and receiving circuit, respectively, so that the equalizer of the receiving circuit is not expected to exhibit a large amplification factor to the high frequency signal components; this results in that the received signal is restored to a waveform close to the original waveform.

Abstract: A switching amplifier is described which includes an input stage having a first node associated therewith and a power stage having a second node associated therewith. An actual loop delay is defined with reference to the first and second nodes. Delay detection circuitry compares the actual loop delay to a reference loop delay. A dynamic delay line controlled by the delay detection circuitry controls the actual loop delay to correspond to the reference loop delay.

Abstract: The invention relates to transmission path delay determination between a first and a second electronic circuit coupled to each other by a transmission path. A determination method includes, among other operations, transmitting at least one test signal from a first electronic circuit to a second electronic circuit, receiving at the first electronic circuit a reflection of the test signal from the second electronic circuit, measuring a time duration necessary for receiving the reflection of the test signal, determining a transmission path delay as half of the measured time duration, reconfiguring the line impedance termination between the first and second electronic circuit, adjusting the timing of a payload signal on the basis of the transmission path delay, and transmitting the payload signal between the first and second electronic circuit.

Abstract: In the present invention, a transmission line length estimation circuit with continuous feedback equalizer is provided. The transmission line length estimation circuit comprises a DC bias circuit and a peak detector circuit to generate a DC voltage according to a different cable length. An equalizer core circuit is for receiving the first signal and generating a second signal. A peak detector circuit is used for the first signal and the second signal. A transmission line length detector circuit is coupled to the peak detector circuit and used for generating a plurality of first parameters for phase shift and amplitude losses according to the different cable length. An internal pattern calibration circuit is multiplexed to the first signal and used for generating a plurality of second parameters for calibration of close loop.

Abstract: A data transmission system is proposed, for example for video-on-demand, internet or multimedia applications, in which a number of subscribers in a building are connected to a central server through at least in part twisted pair cables within the building. Compensation for the channel distortion caused by the use of twisted pair cables is provided by the use of pre-emphasis filters in the outgoing data lines from the server. The required coefficients for the pre-emphasis filters are established by first characterizing the distortion properties of a channel by the use of a test signal.

Abstract: A resonant waveguide load structure is provided for use in waveguide systems. The load structure includes a length of waveguide which is open at one end and closed at the other end. The load structure also includes a support pin mounted inside the waveguide near the closed end thereof. The load structure further includes a resonant body mounted on the support pin. The load structure also includes at least one spacer member mounted on the support pin for maintaining the position of the resonant body. This load structure may be combined with a waveguide circulator to provide a novel waveguide equalizer apparatus.

Abstract: Methods and circuits utilizing a two stage adaptation algorithm to determine the optimal code for an equalizer to compensate a received signal is disclosed. In the first stage, a coarse tuning algorithm is used to choose a range of codes based on the amplitude of the received signal. The chosen codes will be used as reference points in the second stage. In the second stage, a fine tuning algorithm is used to select a code in the range of reference codes determined in stage one. The fine tuning algorithm looks to the status of the data lock signal generated by the clock recovery circuit. If the data lock signal does not indicate a lock, the fine tuning algorithm cycles through the range of reference codes. If the data lock signal indicates a lock, then that particular code is continued to be used for the equalizer.

Abstract: A circuit and method for equalization of a communication signal received over a communication system transmission line using switched filter characteristics. Equalization for frequency-independent and frequency-dependent attenuation of the communication signal is accomplished with a linear equalization channel which includes an input biasing circuit which provides a common input signal to two parallel amplifier paths. One path includes a wideband, fixed-gain, frequency-independent amplifier stage. The other path is a wideband multiplier amplifier stage in series with a wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic. The outputs of the fixed-gain wideband frequency-independent amplifier stage and wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic are both tied in common to the input of a wideband gain buffer amplifier stage, which has a switchable high-frequency boost frequency response characteristic.

Abstract: According to an embodiment, an equalization loop has a comparator with an input to receive a transmission line analog signal level. The comparator has a substantially variable offset that is controllable to represent a variable reference level. An output of the comparator provides a value that represents a comparison between the transmission line analog signal level and the variable reference level.

Abstract: A serial digital data communications receiver with an improved automatic cable equalizer that is less susceptible to jitter and has greater multi-standards capability, and an improved automatic gain control system with a DC restorer that provides optimal edge jitter performance while avoiding the possibility of a latch-up condition at the start of data transmission. The automatic cable equalizer for equalizing signals received over cables of different lengths has multiple stages each having a transfer function of 1+Ki[fi(j&ohgr;)] wherein each of the Ki vary in accordance with a sequential gain control methodology. The AGC system uses the difference between band-pass filtered versions of the amplitudes of the input and output of a DC restorer based on quantized feedback, to regulate the AGC circuit.

Abstract: A method used in equalization processing is provided, in which a reference signal is received and a change point of transmission line characteristics is detected. A basic frequency signal of fluctuation period of the transmission line characteristics is extracted, and vectorized. The vector is adjusted such that vectors corresponding to two change points become symmetrical with respect to X axis. Then, fluctuation interval of transmission line characteristics is judged by comparing X component of the vector with a reference value. As a result, equalization processing is performed in accordance with the fluctuation.