Abstract: A vehicle driving apparatus includes an inverter which drives a permanent magnet motor. The inverter includes a three-phase bridge circuit including a plurality of switch elements, a drive circuit connected to the three-phase bridge circuit, a control circuit connected to the drive circuit, and an abnormality detecting unit which detects abnormality of the inverter. The drive circuit includes a three-phase-short-circuit-forming circuit which causes three phases of the permanent magnet motor to form short circuits, an abnormality accepting terminal which accepts an abnormality signal output from the abnormality detecting unit, and a check terminal which accepts an active check signal for causing the three-phase-short-circuit-forming circuit to perform three-phase short circuit control.

Abstract: According to a first aspect embodiments provide a transistor including at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300.

Abstract: Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.

Abstract: A system for calibrating operation of integrated differential signal receiver circuitry mounted on a substrate and coupled via surface conductors to edge mounted interface electrodes in which compensation is provided for variances among the resistances of the surface conductors.

Abstract: A system for calibrating operation of integrated differential signal receiver circuitry mounted on a substrate and coupled via surface conductors to edge mounted interface electrodes in which compensation is provided for variances among the resistances of the surface conductors.

Abstract: A switch arrangement comprises a photoconductor to be illuminated. The switch arrangement also comprises a conductor which is intended to further transmit light escaping from the photoconductor and directed to the conductor by a local contact, wherein the conductor and the photoconductor are further under the control of an external force, arranged to move in relation to each other and to cause the development, loss or change of the contact in such a way that a detectable change is caused in the light guided through it.

Abstract: Aspects of a switch matrix circuit are provided. In accordance with a circuit aspect, a plurality of switches are organized in a row and column configuration. Coupled to the plurality of switches is a current sensing circuit. The current sensing circuit includes a transistor and at least one resistor per column of the plurality of switches. Current amplified by the transistor and converted by the at least one resistor in a column is sensed as a logic level indicative of a switch status within the column for a selected row. The current sensing arrangement may also be used in an embodiment utilizing bi-directional signal control to minimize the number of I/O lines required to scan the switch matrix. The bi-directional signal scanning may also be implemented in another embodiment that senses voltage levels to determine switch closures.

Abstract: The invention relates to a switching device comprising a plurality of inputs and outputs which are interconnected by a matrix of interconnection points for transmitting electric signals supplied from the inputs to the outputs via transmission lines in accordance with a predefined switching plan. The device comprises a control member for controlling the operation of the matrix with control signals and local decoding for locally decoding the control signals and for deducing the switching state of the interconnection points. Application: packet switching in optical transmissions.

Abstract: A high-speed cross-point switch is built on a preferably silicon substrate and uses bipolar transistor switching elements. Preferably, the bipolar transistors are SiGe bipolar junction transistors. Intersecting conductive input and output microstrips are preferably thinned at their intersections to reduce shunt capacitance between the coupled lines. It is also preferred that the input buffer be connected in cascode fashion with the switching transistors in order to create an amplification stage. The signal and its inverse are carried on balanced microstrip pairs in order to reduce electromagnetic field strength at the center of the balanced line pairs thereby improving isolation between two crossing balanced pairs.

Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

Abstract: A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.

Abstract: A cross-bus switch apparatus which establishes simultaneously two or more pairs of connections between (i) a source bus arbitrarily selected from a plurality of source buses connected to one or more source apparatuses and (ii) a destination bus arbitrarily selected from a plurality of destination buses connected to one or more destination apparatuses. The cross-bus switch apparatus includes: a plurality of cross-bus switch units. The plurality of source buses are grouped into a plurality of source bus groups which are each connected to one of the plurality of cross-bus switch units. The plurality of destination buses are grouped into a plurality of destination bus groups which are each connected to one of the plurality of cross-bus switch units. Each cross-bus switch unit is connected to either (i) a source bus group or a destination bus group, or (ii) a source bus group and a destination bus group.

Abstract: A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.

Abstract: A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.