Abstract: Embodiments generally relate to an addressing circuit for a conductor array comprising intersecting row and column conductors. The addressing circuit comprises a switching circuit configured to selectively address an intersection between a selected row conductor and a selected column conductor for connection to a measuring circuit; and at least one voltage buffer selectively connectable to un-selected column conductors on opposite sides of and adjacent to the selected column conductor. The at least one voltage buffer is configured to equalise voltages between the un-selected column conductors and the selected column conductor.

Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.

Abstract: A three-wire forward and reverse LED light string control circuit, comprising an external power supply, a MCU, a driving circuit and an LED light group circuit, the driving circuit comprises a P-channel first FET, a P-channel third FET, a P-channel fifth FET, a P-channel seventh FET, an N-channel second FET, an N-channel fourth FET, and an N-channel sixth FET; a first port is provided on the wire between the drain of the second FET and the drain of the third FET, a second port is provided on the wire between the drain of the fourth FET and the drain of the fifth FET, and a third port is provided on the wire between the drain of the sixth FET and the drain of the seventh FET. A 6-way LED light string using the said three-wire forward and reverse LED light string control circuit is also provided.

Abstract: Disclosed is a communication network having at least one network access segment including one or more network access points, wherein a selective packet bridge appliance integral or otherwise functionally associated with the at least one network access segment, is adapted to selectively shunt packet flow between two or more mobile communication devices communicatively coupled to the at least one network access segment through access points of the at least one network segment, and wherein a packet is selected for shunting at least partially based on an intended destination of the packet and at least partially based on a payload type of the packets.

Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to a qualified stacked silicon interconnect (SSI) technology programmable integrated circuit (IC) region by providing an interface (e.g., an HBM buffer region implemented with a hierarchical switch network) between the added feature device and the programmable IC region. One example apparatus generally includes a programmable IC region and an interface region configured to couple the programmable IC region to at least one fixed feature die via a first plurality of ports associated with the at least one fixed feature die and a second plurality of ports associated with the programmable IC region. The interface region is configured as a switch network between the first plurality of ports and the second plurality of ports, and the switch network includes a plurality of full crossbar switch networks.

Abstract: A method for managing data includes obtaining, by a storage controller, data from a host, applying an erasure coding procedure to the data to obtain a plurality of data chunks and at least one parity chunk, deduplicating the plurality of data chunks to obtain a plurality of deduplicated data chunks, generating storage metadata associated with the plurality of data chunks and the at least one parity chunk, storing, across a plurality of persistent storage devices, the plurality of deduplicated data chunks and the at least one parity chunk, wherein the plurality of persistent storage devices is operatively connected to the storage controller and a second storage controller, storing the storage metadata in the storage controller, and sending a copy of the storage metadata to the second storage controller.

Abstract: A programmable architecture specialized for convolutional neural networks (CNNs) processing such that different applications of CNNs may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for CNN applications that may be computationally intensive, requiring a huge number of convolution operations per second to process inputs such as video streams in real time.

Abstract: According to an example, coordination of adjustments to network frame hold time parameters between network devices in a network is initiated based on a trigger condition. Time data may be obtained from a plurality of network devices in the network, where the time data describes a network frame hold time parameter of each network device in the plurality and a network frame processing time of each network device. A set of affected network devices affected by network back pressure in the network, and a set of non-affected network devices in the plurality not included in the set of affected network devices, may be determined. Based on the time data, a pairing may be determined between a time-available network device from the set of non-affected network devices and a time-needed network devices, from the set of affected network devices, to receive an allocation of time credit from the time-available network device.

Abstract: A communication method includes: transmitting a transfer request and setting information from first to second server apparatus; transmitting a transfer notification from second to third server apparatus directly or through the first server apparatus; transmitting a transfer response from third to first server apparatus; receiving a first information request from the third server apparatus during a first period; transmitting, after the first period elapses, the first information request from first to second server apparatus; receiving a plurality of second information requests transmitted from the third server apparatus during a second period, and retaining the second information requests in a received order; and after the second period elapses, transmitting first setting information corresponding to the first information request from second to third server apparatus, and subsequently transmitting a plurality of second setting information corresponding to the second information requests from second to third se

Abstract: Example implementations relate to an arbitration node. For example, an arbitration node can include instructions to receive, at the arbitration node at a level of a binary tree structure, a first request including a first request signal and a first priority signal and receive a second request including a second request signal and a second priority signal. In some examples, the arbitration node can include instructions to determine priority of requests by comparing the first request signal and the second request signal and by comparing the first priority signal and the second priority, and send a request signal and a priority signal of the request with the determined priority to a subsequent arbitration node at a subsequent level of the binary tree structure.

Abstract: A method and apparatus are disclosed that apply multiuser detection (MUD) analysis to an aggregated RF response from a plurality of simultaneously queried RFID tags, so as to distinguish the individual tag responses. The claimed method thereby significantly reduces RFID detection latency when multiple tags are simultaneously queried. Some embodiments transmit carrier waves at more than one frequency, such as a plurality of equally-spaced frequencies, so as to enhance the MUD analysis by incorporating a multi-frequency dimension. Other embodiments incorporate additional spatial dimensions by deploying multiple RF detection antennae at separated locations. The number of colliding tag responses must be estimated before MUD analysis can be applied.

Abstract: A control system CPU card includes a control CPU chip having a first core and a second core, and a main memory for storing information. A standby system CPU card includes a standby CPU chip having a first core and a second core, and a main memory for storing information. An I/F performs communication to allow the CPU cards to share the information. In the control system CPU card, when the first core is normal, the first core performs control calculation and outputs a calculation result. When the first core is abnormal, the second core is switched to a control core, to perform control calculation and continue output of a calculation result. When the cores are both abnormal, system switching is performed from the control system CPU card to the standby system CPU card.

Abstract: A method and apparatus are disclosed that apply multiuser detection (MUD) analysis to an aggregated RF response from a plurality of simultaneously queried RFID tags, so as to distinguish the individual tag responses. The claimed method thereby significantly reduces RFID detection latency when multiple tags are simultaneously queried. Some embodiments transmit carrier waves at more than one frequency, such as a plurality of equally-spaced frequencies, so as to enhance the MUD analysis by incorporating a multi-frequency dimension. Other embodiments incorporate additional spatial dimensions by deploying multiple RF detection antennae at separated locations. The number of colliding tag responses must be estimated before MUD analysis can be applied.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. Alternatively, the conductive ink is deposited by dispensing the conductive ink through a nozzle into the patterned trench. The conductive ink is cured by ultraviolet light at room temperature. A second insulating layer is formed over the first insulating layer and conductive ink. An interconnect structure is formed over the conductive ink. An encapsulant can be deposited around the semiconductor die. The patterned trench is formed in the encapsulant and the conductive ink is deposited in the patterned trench in the encapsulant.

Abstract: A programmable frequency termination shunt suitable to terminate a portion of a railroad track circuit. The programmable frequency termination shunt includes a multi-frequency shunt circuit having a plurality of selectable shunt frequencies and a processor coupled to the multi-frequency shunt circuit. The processor is adapted to set the termination frequency of the shunt by selecting one of the shunt frequencies of the multi-frequency shunt circuit. The shunt is powered by signals transmitted along the rails of the railroad track and can be programmed in response to signals from a rail-based communication link or a wireless communication link.

Abstract: Some embodiments of the invention relate to WRAs that implement removable memory units (RMUs). The ability to load operational, maintenance, and mission data through RMUs is critical for avionics platform safety and logistics. However, due to strong hardware dependence, universality, or rather platform-invariance is not currently available for aircraft data acquisition (including the real-time recording of new performance, operational (flight) and environmental data) or mission data loading via prior art WRAs.

Abstract: Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.

Abstract: A switch matrix module (600) includes programmable stub breakers (508-512, 514-518) which can break off the bus and isolate unused portion of the switch matrix. Using three-way stub breakers (508-512, 514-518) at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices, allows for the formation of very large matrices which have improved operational performance.

Abstract: In a key scanning circuit, a key input unit has a parallel connection of a plurality of circuits having a series connection of resistors and switches between a power supply input terminal and a key scanning terminal. The resistors connected in parallel have different resistances. A current mirror has a first terminal connected to the key scanning terminal. A reference current source is connected between a second terminal of the current mirror and the power supply input terminal.

Abstract: A matrix switch is provided with a plurality of input-terminals, a plurality of output-terminals, a plurality of connector switch elements connecting the plurality of input-terminals with the plurality of output-terminals, a plurality of input-terminal shunts associated with the plurality of input-terminals, and a plurality of output-terminal shunts associated with the plurality of output-terminals. Each input-terminal is connected to at least any one of the plurality of input-terminal shunts, and the input-terminal shunt connects the associated input-terminal to a predetermined impedance load as necessary. Each output-terminal is connected to at least any one of the plurality of output-terminal shunts, and the output-terminal shunt terminates the associated output-terminal in a predetermined impedance as necessary.

Abstract: A communication system wherein each endpoint device which has received an interrogating signal from an interrogator responds with a reflected signal generated by modulating the interrogating signal with appropriate information, wherein each endpoint device includes a distance detecting portion operable to detect a distance between the interrogator and the endpoint device, a reflecting portion operable to receive and reflect the interrogating signal, an information generating portion operable to generate replying information to be transmitted to the interrogator, a band determining portion operable to determine, on the basis of the detected distance, a frequency band of a modulating signal used to modulate a reflected signal generated by the reflecting portion, and a modulating-signal generating portion operable, according to the replying information, to generate the modulating signal having a frequency within the determined frequency band.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: A key system utilizes two operation nodes to detect the status of a plurality of keys, and each operation node can output and read a high, a low, and a clock signal. When an operation node outputs a high signal and reads a return signal and then outputs a low signal and reads a return signal, the other operation node outputs a clock signal. Therefore, the two operation nodes can detect the status of six keys.

Abstract: The present invention provides a method of restoring a remotely-located control device of a wireless load control system to a default factory setting. The control device is operable to be coupled to a source of power and has a memory for storing programming information. First, a beacon message is transmitted repeatedly on a predetermined channel. Second, power is applied to the control device. Subsequently, the control device listens for the beacon message for a predetermined amount of time on each of the plurality of channels, and receives the beacon message on the predetermined channel. Next, the a first signal uniquely identifying the control device is transmitted wirelessly from the control device on the predetermined channel within a predetermined amount of time power is applied to the control device. Finally, the control device receives a second signal transmitted on the predetermined channel, and programs the memory with the default factory setting in response to the second signal.

Abstract: An interrogator autonomously reduces interference of receiving radio waves in a wireless tag. The interrogator transmitting and receiving a signal to and from a wireless tag, comprises a carrier sense unit detecting an idle channel in a plurality of channels used for communications with the wireless tags, a transmitting unit transmitting the signal to the wireless tag by use of the detected idle channel, an abnormality detecting unit detecting communication abnormality in the communications with the wireless tag, and a control unit controlling so as to interrupt, when detecting the communication abnormality, the transmission to the wireless tag, re-detect an idle channel after an elapse of a predetermined transmission halt period, and resume the signal transmission to the wireless tag by using the re-detected idle channel.

Abstract: A multiplexer can include a signal line arranged on a substrate and including a plurality of data wires extending in a first direction and electrically insulated from one another, where each of the data wires has at least one recess to provide at least two data wiring pieces. An address line is arranged on the signal line and includes a plurality of coding lines extending in a second direction different from the first direction and electrically insulated from the data wires. A plurality of switching elements are positioned in the recesses of the data wires and make electrical contact with the coding lines, where the switching element is configured to switch a data signal applied to the data wiring on and off in accordance with a coding signal applied to the coding lines, so that one of the data wires is selected according to a binary code of the address line corresponding to combinations of the coding lines to which coding signal is applied.

Abstract: Embodiments of the present invention provide a system and method for handling persistent reservations. More particularly, according to one embodiment of the present invention, a routing device that routes commands from multiple initiators to a target device can assert reservations for the initiators using its own reservation key rather than a reservation key provided by an initiator. The routing device can further maintain a registry of keys for multiple initiators that access the target device through the routing device. For a persistent reservation command received using a persistent reservation key in the registry, the routing device can forward the command to the target device server using the routing device's key. Thus, reservations for the multiple initiators will be held using the routing device's key. For persistent reservation commands received from initiators registered with the routing device, the routing device can handle conflict resolution and other persistent reservation processing.

Abstract: The present invention provides a more efficient use of control signal capacity to control multiparameter automated luminaries by remapping channel assignments within a luminaire. The system taught allows parameter mappings to be group for programming convenience. It allows parameters to be skipped and allows flexibility in the resolution allowable for controlling a parameter. It also allow luminaries to share some channel assignments.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: The invention relates to an active distribution device (1) in the subscriber access area, comprising a multi-service access node (2) which has one interface to a switching center and at least two interfaces to a distribution device, with a first message service being provided via the at least one first interface (7) to the distribution device (3), and a second message service being provided via the at least one second interface (8), the first and/or second interfaces (7, 8) being connected to the distribution device (3), in which the distribution device (3) comprises a changeover device (11) and a switching matrix (12), the first interfaces (7) are connected to first inputs (13) of the changeover device (11), at least the second interfaces (8) are connected to inputs (18) of the switching matrix (12), with the number of inputs (18) of the switching matrix (12) being less than the number of inputs (13) of the changeover device (11), the outputs (15) of the switching matrix (12) being connected to second inputs

Abstract: A rearrangeably nonblocking multicast network includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, where m?n1+n2. The network has all multicast connections set up such that each multicast connection passes through at most two middle switches to be connected to the destination outlet links.

Abstract: A communications method including the steps of: activating a plurality of signal sources, and transmitting a synchronization event to the plurality of signal sources to cause the plurality of signal sources to simultaneously transmit data in response to the synchronization event.

Abstract: In a data switching system, the ingress and egress ports of a memoryless cross-bar switch are controlled by an arbitration method. The arbitration method uses a three phase process involving (i) a request phase in which each ingress port sends its connection requests to egress ports to which a connection is required, (ii) a grant phase in which each egress port uses a grant pointer to select one of the requests directed to it using a grant pointer, and generates a grant signal, and (iii) an accept phase in which each ingress port selects one of the received grant signals to accept, so defining an ingress to egress port connection across the cross-bar switch. The transition sequences for each of the grant pointers are mutually exclusive, so that any synchronisation of the grant pointers is eliminated on the next arbitration cycle. This is arranged by a setting of the paths taken by request and grant signals.

Abstract: A remote control system for precisely identifying a distance from the vehicle to an entry key and favorably controlling a vehicle-mounted device such as a door corresponding to the distance. The system comprises a transmitter transmitting different types of response demand signals within a predetermined communication area outside the vehicle, a vehicle mounted receiver for receiving a response signal released from a portable transmitter/receiver in response to the reception of the response demand signal, a controller controlling the vehicle mounted device corresponding to the reception of the response signal by the vehicle mounted receiver. Locking and/or unlocking door(s) of the vehicle are controlled on the basis of whether or not the receiver receives the response signal to a response demand signal other than one having the largest communication area.

Abstract: The invention relates to a switching device comprising a plurality of inputs and outputs which are interconnected by a matrix of interconnection points for transmitting electric signals supplied from the inputs to the outputs via transmission lines in accordance with a predefined switching plan. The device comprises a control member for controlling the operation of the matrix with control signals and local decoding for locally decoding the control signals and for deducing the switching state of the interconnection points. Application: packet switching in optical transmissions.

Abstract: A switching apparatus is disclosed that employs a relatively simple and inexpensive switching matrix, but which avoids interruption of existing connections when connections are added or removed. The switching matrix switches errorlessly by controlling the point in time at which switching occurs. Using such a technique, switching can be performed without disturbing the connections already configured in the switching matrix, and so is referred to herein as being non-blocking. Optionally, the incoming data can be rearranged to provide a larger window of time in which the switching matrix can be switched. In the case of a switch using an optical backplane, this also allows more time for various components of the system (e.g., clock/data recovery units) to re-acquire lock. The switching apparatus includes a switching matrix and control circuitry. The switching matrix has a matrix input, a control input and a number of matrix outputs, and is configured to receive an information stream at the matrix input.

Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

Abstract: A rearrangeably nonblocking multicast network in accordance with the invention includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, where m?n1+n2. The network has all multicast connections set up such that each multicast connection passes through at most two middle switches to be connected to the destination outlet links. When the number of inlet links in each input switch n1 is equal to the number of outlet links in each output switch n2, and n1=n2=n, a three-stage network is operated in rearrangeably nonblocking manner in accordance with the invention, where m?2*n.

Abstract: A cross-bus switch apparatus which establishes simultaneously two or more pairs of connections between (i) a source bus arbitrarily selected from a plurality of source buses connected to one or more source apparatuses and (ii) a destination bus arbitrarily selected from a plurality of destination buses connected to one or more destination apparatuses. The cross-bus switch apparatus includes: a plurality of cross-bus switch units. The plurality of source buses are grouped into a plurality of source bus groups which are each connected to one of the plurality of cross-bus switch units. The plurality of destination buses are grouped into a plurality of destination bus groups which are each connected to one of the plurality of cross-bus switch units. Each cross-bus switch unit is connected to either (i) a source bus group or a destination bus group, or (ii) a source bus group and a destination bus group.

Abstract: A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.

Abstract: A method and apparatus for adapting a single computer to drive at least two displays is disclosed. In one embodiment, an apparatus for adapting a single computer to drive at least two displays is disclosed. The apparatus comprises a controller, coupled between a user input device such as a computer, the controller for providing a control signal according to a user input; and a video switcher, for selectively providing a signal from the computer to one of at least two video displays in response to the control signal. In another embodiment, a method of presenting information on at least two displays communicatively coupled to a computer is disclosed. The method comprises the steps of intercepting a user input to the computer, and directing a video output signal from the computer to one of at least two video displays according to the intercepted video input.

Abstract: A remote control system for precisely identifying a distance from the vehicle to an entry key and favorably controlling a vehicle-mounted device such as a door corresponding to the distance. The system comprises a transmitter transmitting different types of response demand signals within a predetermined communication area outside the vehicle, a vehicle mounted receiver for receiving a response signal released from a portable transmitter/receiver in response to the reception of the response demand signal, a controller controlling the vehicle mounted device corresponding to the reception of the response signal by the vehicle mounted receiver. Locking and/or unlocking door(s) of the vehicle are controlled on the basis of whether or not the receiver receives the response signal to a response demand signal other than one having the largest communication area.

Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

Abstract: A method for communicating from a source port (i) to a destination port (j) is employed within a switching system that has m ports, each of the ports being coupled to a local area network via a Hub. The connectivity between the inputs and outputs of the m ports forms a matrix of cross points having m rows and m columns. Each port has a transmit line coupled to a row of the matrix and a receive line coupled to a column of the matrix. A transmission operation from the source port (i) to the destination port (j) involves a first control circuit for unilaterally connecting the port (i) to the port (j), a second control circuit for unilaterally connecting the port (j) to the port (i). The method includes the use of a third control circuit, and a column control bus that couples the third control circuit to a plurality of control circuits including the second control circuit.

Abstract: In a three stage non-blocking switching matrix (10), there are originating stages (12), center stages (14), and terminating stages (16). In order to establish matrix connections for either a one input/two output scenario or a two input/one output scenario, a determination must be made as to whether there is a center stage (12) common to all three ports. If so, then the matrix connection is established through the available center stage (12). If there is no common center stage (12) among the three ports, then rearrangement candidates are identified to free up an available center stage. One or more matrix connections are rearranged without affecting live traffic. After rearrangement, the matrix connection for the three ports is established through the freed up center stage (12).

Abstract: Enhanced performance is realized in a multi-fabric/multi switch group interconnect network by providing asymmetric fabric topologies wherein at least one link between a user-port and a switch-port (or between a pair of switch ports) is different in the fabrics. Asymmetry in fabric topology can increase lower-distance (distance-1) pairs, increase network bisection capacity, or reduce the number of switches employed. End nodes can choose at the time of connection the fabric which offers a shorter connection or fewer router hops. Alternatively, a connection can be set up to use either fabric with the end node dynamically exercising its preference for the fabric that offers the shorter path at the time of data transfer. While the number of router hops does not significantly alter message latency in wormhole-routed networks, it does lower link occupancy and thereby average link contention.

Abstract: An arrangement of a plurality of status keys in a keyboard for entering information in an electronic device. The keyboard comprises a plurality of regular keys connected to a resistive strip at a plurality of locations for providing a first signal when one of the regular keys is pressed and the first signal is indicative of the location associated with the pressed regular key; a plurality of resistors, each having a different resistance, connected in series to the resistive strip, and separately connected in parallel to the status keys so that the resistors can be selectively by-passed by pressing one or more status keys, wherein a second signal is provided when one of the regular keys is pressed together with at least one status key, and wherein the second signal is indicative of the resistance the status key for identifying the pressed status key.

Abstract: A high density electronic switching matrix (ESM) includes several splitting modules (200) arranged along a first axis, each including a signal input (202) and several splitter outputs (204). The ESM (500, 600) further includes several switching modules (400) arranged along a second axis perpendicular to the first axis. Each switching module (400) includes switching inputs (402) coupled individually to an output of each of the splitting modules (200). The ESM (500, 600) is further characterized by couplings between the splitter modules and the switching modules. The couplings are formed by mating male and female connectors (300) integrated into the splitting modules and the switching modules. The couplings support extremely high frequency operation. The splitting modules (200) and the switching modules (400) may thus be coupled closely together to form a dense, high frequency, switching matrix, and may be stacked upon one another.

Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.

Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.