Abstract: A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.

Abstract: A photoelectric conversion apparatus includes a pixel, an A/D conversion portion and an output circuit. The pixel includes first and second photoelectric conversion portions and an accumulation portion configured to accumulate a signal charge in a location other than the photoelectric conversion portions. The A/D conversion portion is configured to perform A/D conversions on signals based on signal charges generated in the photoelectric conversions. The output circuit reads out first and second signals based on first and second signal charges accumulated in the first and second photoelectric conversion portions during an electric charge accumulation period and a third signal based on a third signal charge generated in the second photoelectric conversion portion and accumulated in the accumulation portion during the electric charge accumulation period. Conversion periods for analog-to-digital conversion to be performed on at least two of the first, second, or third signals have different lengths.

Abstract: An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.

Abstract: A semiconductor device comprising: a voltage generator configured to generate a voltage; a first analog-to-digital (AD) converter configured to convert an analog value based on a voltage generated by the voltage generator into a first digital value; and a second AD converter configured to convert an analog value based on a voltage generated by the voltage generator into a second digital value, wherein the voltage generator generates voltages by dividing a power supply voltage by resistive elements.

Abstract: An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.

Abstract: A photoelectric conversion apparatus includes a pixel, an A/D conversion portion and an output circuit. The pixel includes first and second photoelectric conversion portions and an accumulation portion configured to accumulate a signal charge in a location other than the photoelectric conversion portions. The A/D conversion portion is configured to perform A/D conversions on signals based on signal charges generated in the photoelectric conversions. The output circuit reads out first and second signals based on first and second signal charges accumulated in the first and second photoelectric conversion portions during an electric charge accumulation period and a third signal based on a third signal charge generated in the second photoelectric conversion portion and accumulated in the accumulation portion during the electric charge accumulation period. Conversion periods for analog-to-digital conversion to be performed on at least two of the first, second, or third signals have different lengths.

Abstract: An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.

Abstract: Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

Abstract: A ramp voltage generator includes: a ramping cell array including a plurality of ramping current cells; a calibration cell array including a plurality of calibration current cells; and a current-voltage converter suitable for converting a current supplied from activated ramping current cells among the ramping current cells and activated calibration current cells among the calibration current cells into a voltage to generate a ramp voltage.

Abstract: A sub-ranging programmable gain amplifier resolves an incoming signal into one of multiple amplitude sub-ranges and dynamically steps down the PGA output according to the identified sub-range.

Abstract: An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

Abstract: Techniques are described for implementing counter architectures to support high-speed, high-resolution pixel conversions, such as for CMOS image sensor applications. Embodiments implement a counter block that uses loadable true-signal-phase-clocking (L-TSPC) flops for at least a portion of the counter flops. Some embodiments support efficient two-phase pixel conversion by integrating counting, subtraction, and shifting out in the counter. For example, embodiments can perform a first high-speed pixel conversion phase to obtain a first conversion count. Prior to a second phase, the initial counter can be pre-subtracted by the amount of the first conversion count. Embodiments can then perform a second high-speed pixel conversion phase to obtain a second conversion count. As the second conversion count already has the first conversion count pre-subtracted, the second conversion count represents the final two-phase conversion result.

Abstract: An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (Vth) to a pixel signal (SVSL). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.

Abstract: Various embodiments relate to a single slope analog to digital converter (ADC), including: a voltage slope generator; a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage, where the first reference voltage equals the sum of the second reference voltage and the third reference voltage; a first comparator configured to compare a voltage to a voltage output from the voltage slope generator; a first register configured to store a first count based upon the first reference voltage being input into the first comparator; a second register configured to store a second count based upon the second reference voltage being input into the first comparator; a third register configured to store a third count based upon the third reference voltage being input into the first comparator; a fourth register configured to store a fourth count based upon a first input voltage being input into the first comparator, wherein the first input voltage i

Abstract: A circuit assemblage for carrying out a comparison between a first signal and a second signal in consideration of a reference signal, the circuit assemblage encompassing: a first channel in which the first signal is processed; and a second channel in which the second signal is processed, a first differential amplifier, which obtains a first difference between the first signal and the reference signal, and a first unit for obtaining an absolute value, which obtains a first absolute value from the first difference, being provided in the first channel, and a second differential amplifier, which obtains a second difference between the second signal and the reference signal, and a second unit for obtaining an absolute value, which obtains a second absolute value from the second difference, being provided in the second channel; and a comparator that compares the first absolute value with the second absolute value.

Abstract: Various embodiments relate to a single slope analog to digital converter (ADC), including: a voltage slope generator configured to generate a voltage slope based upon a fixed current and variable current; an analog comparator configured to compare a voltage to a voltage output from the voltage slope generator; a first register configured to store a first count based upon a reference voltage being input into the analog comparator; a second register configured to store a second count based upon an input voltage being input into the analog comparator, wherein the input voltage is the voltage to be converted to a digital value by the ADC; and a digital to analog converter (DAC) configured to produce a slope trim signal based upon the voltage slope output by the voltage slope generator, the first count, and a count target associated with the voltage reference, wherein the variable current in the voltage slope generator is based upon the slope trim signal.

Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.

Abstract: In an image pickup apparatus including first circuits, second circuits, and conversion units, an operation period of the second circuit is shorter than an operation period of the first circuit, and a number of the first circuit arranged in each unit cell is greater than a number of the second circuit arranged in each unit cell.

Abstract: To prevent a decline in image quality by reducing a fluctuation in an image signal that is based on a fluctuation in a voltage of a negative voltage power source. An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal.

Abstract: A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: In a pixel section of an image sensor, pixels are arranged two-dimensionally, each of the pixels including an amplifier transistor that is connected to a power voltage and has a gate into which a voltage of a signal charge generated by a photoelectric conversion area is input and a selection transistor that is connected to the amplifier transistor and a signal line. The image sensor includes an AD conversion circuit having a reference transistor having a gate into which a ramp signal is input and a constant current source that is connected to the reference transistor and the signal line. The voltage of the ramp signal or a driving ability of the reference transistor changes depending on whether one selection transistor or a plurality of selection transistors is/are turned on per signal line to obtain a signal charge to be AD-converted.

Abstract: An analog-to-digital signal processing method applied for an image sensor includes: providing a global analog-to-digital converter (ADC) capable of converting analog signals of all pixels of a pixel array into digital signals; providing a column-parallel ADC capable of respectively converting a plurality of analog signals of a plurality of pixels on different columns of the pixel array into a plurality of digital signals by using a plurality of ADC circuits; and, dynamically selecting and switching to enable one of the global ADC and column-parallel ADC to perform analog-to-digital conversion for analog data/signals of pixels on the pixel array.

Abstract: In a pixel section of an image sensor, pixels are arranged two-dimensionally, each of the pixels including an amplifier transistor that is connected to a power voltage and has a gate into which a voltage of a signal charge generated by a photoelectric conversion area is input and a selection transistor that is connected to the amplifier transistor and a signal line. The image sensor includes an AD conversion circuit having a reference transistor having a gate into which a ramp signal is input and a constant current source that is connected to the reference transistor and the signal line. The voltage of the ramp signal or a driving ability of the reference transistor changes depending on whether one selection transistor or a plurality of selection transistors is/are turned on per signal line to obtain a signal charge to be AD-converted.

Abstract: The present technology relates to an imaging element, a processing method, and an electronic device which are capable of reducing deterioration in an image quality of a captured image caused by power fluctuation. A counting unit includes a counting operation unit that performs a counting operation of counting the count value and a dummy operation unit that performs a dummy counting operation at a timing complementary to the counting operation of the counting operation unit. The present technology can be applied to, for example, an imaging element that counts a count value and performs AD conversion.

Abstract: The present disclosure illustrates an image sensor. The image sensor includes an image sensing array and a voltage supply array. The image sensing array and the voltage supply array are coupled to an analog-to-digital converter array. The image sensing array captures image data. The image sensing array supports one of a rolling shutter mechanism and a global shutter mechanism according to setting. The voltage supply array includes a plurality of voltage supply circuits to supply dummy voltage. During an auto-zero period, the voltage supply array provides the dummy voltage to the analog-to-digital converter array. Pluralities of comparators of the analog-to-digital converter array execute an auto-zero function based on the dummy voltage. After finishing the auto-zero function, the image sensing array outputs the image data to the analog-to-digital converter array. The analog-to-digital converter array makes the image data be digital.

Abstract: An image sensing device includes: a pixel suitable for generating a pixel signal based on a first driving voltage; a ramp signal generation block based on a variable resistance, the ramp signal generation block being suitable for generating a ramp signal whose slope is controlled by a resistance value varied according to an analog gain; a noise compensation block based on a fixed resistance suitable for sensing a noise component included in the first driving voltage to generate a noise signal and reflecting the noise signal in the ramp signal; and a digital processing block suitable for generating a digital signal based on the pixel signal and the ramp signal.

Abstract: According to one aspect, embodiments herein provide a TDI image sensor comprising an array of light sensing elements, at least one clock, and an image processor, wherein the at least one clock is configured to operate a first plurality of the light sensing elements to transfer accumulated charge to an adjacent element at a first phase and to operate a second plurality of the light sensing elements to transfer accumulated charge to an adjacent element at a second phase, and wherein the image processor is configured to read out a first signal from the first plurality of light sensing elements corresponding to a total charge accumulated at the first phase, to read out a second signal from the second plurality of light sensing elements corresponding to a total charge accumulated at the second phase, and to combine the first signal and the second signal to generate an image.

Abstract: Comparator circuits suitable for use in a column-parallel single-slope ADC comprise a comparator, an input voltage sampling switch connected between an input voltage Vin and a first node, and a sampling capacitor connected between the first and second nodes and which stores a voltage which varies with Vin when the sampling switch is closed. A first reset switch is connected between the second node and a reset voltage, an isolation buffer is coupled between the second node and a comparator input, and a voltage ramp switch applies a voltage ramp Vramp to the first node when closed. The comparator output toggles when Vramp exceeds Vin, with the isolation buffer maintaining a nearly constant capacitive load on Vramp. A ‘ramp disconnect’ feature can be used to increase the circuit's input range, and a dummy capacitor can be employed to maintain a constant capacitance on Vramp.

Abstract: An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.

Abstract: A solid-state imaging device includes: a first substrate; a second substrate; a pixel unit in which pixels are disposed in a matrix; and an A/D conversion unit that is disposed for every columns of the pixels and counts a count clock for only a period according to a magnitude of the pixel signal. The A/D conversion unit includes: counter units that is provided in one of the first substrate and the second substrate and generates n-bit count signals; memory units that is provided in the other of the first substrate and the second substrate and holds the count signals and outputs the held count signals to horizontal signal transfer lines; and a connection unit that connects each counter unit to a corresponding one of the memory units and simultaneously transfer the count signals from at least two counter units to at least two memory units.

Abstract: A method of operating an image sensor includes generating a plurality of ramping up/down signals, and comparing a correlated double sampled pixel signal produced from an output of a pixel with a correlated double sampled first ramping up/down signal among the plurality of ramping up/down signals in a reset interval. The method further includes comparing the correlated double sampled pixel signal with the correlated double sampled first ramping up/down signal at one sampling time or more in an image interval, and a step of outputting a selected ramping up/down signal among the plurality of ramping up/down signals based on a result of the comparison.

Abstract: One or more analog-to-digital converters and methods for analog-to-digital conversion are provided. The analog-to-digital converter comprises a ramp generator and a direct current (DC) generator respectively configured to apply a ramp voltage waveform and a DC voltage waveform to a comparator. During a pixel signal level conversion, a first portion of the ramp voltage waveform is applied to the comparator. A control circuit then makes a determination regarding an output of the comparator. If the output corresponds to a first output, or first logic state, the ramp voltage generator applies a second portion of the ramp voltage waveform to the comparator. If the output corresponds to a second output, or second logic state, the DC generator adjusts the DC voltage waveform applied to the comparator.

Abstract: A shared counter circuit for a column-parallel single-slope ADC includes an n-bit counter; n low-voltage (LV) drivers connected to receive respective counter output bits and to provide a logic high or logic low output signal which tracks the received bit, the voltage difference between the logic high and logic low output signals being less than Vdd; and a plurality of sets of regenerative latches powered by a supply voltage Vdd, each of which receives an output from a respective LV driver and latches and regenerates the received output as a rail-to-rail CMOS signal upon the occurrence of a trigger event. One typical trigger event occurs when a periodic ramp voltage exceeds an input voltage provided to the ADC which may originate, for example, from the columns of a photodetector array.

Abstract: A solid-state imaging apparatus includes: a ramp signal generator for generating first and second time-changing ramp signals during first and second analog-to-digital conversion periods, respectively; comparators for comparing a reset signal of a pixel with the first ramp signal during the first analog-to-digital conversion period, and comparing a pixel signal with the second ramp signal during the second analog-to-digital conversion period; and memories for storing, as first and second digital data, count values of counting from a start of changing the first and second ramp signals until an inversion of outputs of the comparators, during the first and second analog-to-digital conversion periods, wherein the ramp signal generator supplies a current from a current generator to a first capacitor element by a sampling and holding operation of a switch, and generates the first and second ramp signals based on the same bias voltage held by the first capacitor element.

Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.

Abstract: Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.

Abstract: An image sensor in which a plurality of pixels are arrayed in a row direction and a column direction, and an A/D converter is provided on each column of the plurality of pixels. The A/D converter performs one of charge and discharge from an initial value which is a voltage corresponding to an output signal from a pixel, outputs, as a digital value of the output signal, a value corresponding to a time taken for the voltage to become higher or lower than a predetermined reference voltage, and changes one of an amount of charge and an amount of discharge per unit time according to a possible value of the output signal.

Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a first condenser that is disposed between a gate electrode of the first transistor and a reference signal supply unit; a second condenser that is disposed between a gate electrode of the second transistor and a pixel signal wiring; a third transistor that connects a connection point of the gate electrode of the first transistor and the first condenser to the pixel signal wiring; and a fourth transistor that connects a connection point of the gate electrode of the second transistor and the second condenser to the pixel signal wiring.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.

Abstract: An image sensing device includes, inter alia, a ramp signal generation unit generating a ramp signal that decreases during first and second periods for finding data values corresponding to a pixel signal and an offset value, respectively. The image sensing device also includes a comparison unit compares the pixel signal with the ramp signal during the first period, and compares the ramp signal with an internally generated offset value during the second period. A first counting unit is configured to perform a counting operation during the first period, and a second counting unit configured to latch a count value of the first counting unit as a data value in response to the result of the first comparison operation during the first period, perform a down-count operation from the latched data value in response to the result of the second comparison operation during the second period, and latch a counting result.

Abstract: In a solid-state imaging device which includes column analog-to-digital conversion circuits (ADCs) for converting pixel signals output from pixels into digital signals, each of the column ADCs includes a comparator which outputs a result of voltage comparison (comparison result signal) between the voltage of the pixel signal and an analog ramp voltage; a column counter which counts a column counter clock signal, which is either a clock signal or a phase-shifted clock signal, and stores a value represented by upper bits of a count value at a time of change in the comparison result signal; and a first latch unit which stores a value represented by lower bits of the count value. A second latch unit stores the value stored in the first latch unit.

Abstract: A photoelectric conversion device includes a counter circuit configured to count a first clock signal to output a count signal thereof, a second clock signal generation unit configured to generate a second clock signal based on the first clock signal, and a clock synchronization unit configured to output a count start signal in synchronization with the second clock signal, wherein the counter circuit performs a counting operation in response to the count start signal synchronized with the second clock signal.

Abstract: A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.

Abstract: An imaging device includes a comparator that compares a noise signal with each of a first reference signal and a second reference signal having potentials with different changing quantities per unit time, and that compares a photoelectric conversion signal with each of the first reference signal and the second reference signal. Also, the imaging device AD-converts signals obtained by amplifying the noise signal by a first gain and a second gain having different gains, and AD-converts a signal obtained by amplifying the photoelectric conversion signal by one of a first gain and a second gain.

Abstract: An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.

Abstract: A system and method are provided for selecting a remote controlled device to be controlled from among a plurality of remote controllable devices. The system includes an electronic device having a registration interface configured to register device data corresponding to the plurality of remote controllable devices, a position locator configured to determine position data corresponding to a position of the electronic device, and an orientation interface configured to receive orientation data corresponding to an orientation of a user. A controller is configured to select the remote controlled device based on the device data, the position data, and the orientation data. The plurality of remote controllable devices each may include a respective data source configured to provide the device data, and a headset may be configured to generate the orientation data.

Abstract: An analog-to-digital conversion circuit includes a reference current generating unit suitable for generating a reference current varied by a given level in a sampling stage, a ramp voltage generating unit suitable for generating a ramp voltage corresponding to the reference current, and a comparison unit suitable for comparing the ramp voltage with a voltage level of a pixel signal to output a comparison signal.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.