Abstract: A Sigma Rho A/D converter (10) includes a transconductance element (R) having an input node for receiving an input voltage signal V.sub.in and an output node providing an analog current I.sub.in ; a charge integrator (12) having an input coupled to the output node, the charge integrator having feedback provided by an integrating capacitor C and an output node providing an output signal V.sub.o ; and a clocked voltage comparator (14) having an input coupled to V.sub.o for comparing V.sub.o to a reference potential. An output of the comparator updates in response to an occurrence of a first clock signal CLK1. A current sink (16) is switchably coupled to the output node of the transconductance element as a function of the logic state of the output of the comparator.

Abstract: A current-to-frequency converter which uses current balancing and pulse width modulation. An analog signal from a measurement instrument, such as an accelerometer, is integrated and transmitted to a pulse width modulator. The output from the pulse width modulator controls feedback signals which in turn control current balancing. The output of the pulse width modulating circuit is also connected to a counter which provides a digital output.

Abstract: An analog-to-digital converter (ADC) generates multiple analog waveforms, preferably as voltage ramps, that progressively increase in signal value over time but at different rates of increase. The ramp with the greatest slope is initially compared with an input signal sample until the ramp exceeds the sample, at which time the system switches to the ramp with the next greatest slope for comparison with the input. The operation then repeats, with the system switching to the next lower ramp each time the current ramp exceeds the input. Both the number of ramp switching events that occur during a sample cycle, and the clock count at the time of the most recent ramp switch, are recorded and used respectively as the most and least significant bits of a digital output. The switching event count proceeds from an initial maximum value from which it subtracts at each switching event, while the clock count builds up from an initial minimum value.

Abstract: This flash analog-to-digital converter with integrating input stage has a very high speed and resolution due to drastically reduced number of components. The input signal is integrated for providing a varying ramp signal to comparators. A plurality of the comparator codes produced thereby is sampled, whereby a code sequence is established. A resistor or capacitor network determines quantization levels for the comparators so that the code sequence is different for any substantially different input signal. The code sequence is converted by means of an encoder, adder and decoder into the output code of the converter.

Abstract: An analog to digital converter (ADC) is disclosed having a coarse converter to generate the most significant bits of the output and double folding interpolation circuitry to generate the least significant bits. Each side of the double folding circuit includes additional folding stages coupled to reference voltages above and below the full scale input range of the ADC to cancel offset errors and improve circuit linearity. The interpolation circuit includes one interpolation stage, having two multiplier networks, for each least significant bit. Each interpolation stage receives two pairs of signals from the preceding stage and outputs two pairs of signals to the next stage. One of the pairs of output signals from each interpolation stage is also sent to a latched comparator. The outputs of all of the latched comparators can be read directly as the ADC output bits without requiring a decoder.

Abstract: An integrated circuit analog-to-digital converter for use on the focal plane of an infrared detector array. The analog-to-digital converter has a sample and hold circuit, a comparator circuit, and a latch circuit. A single slope conversion technique is used to generate digital signals representative of the amplitude of the input analog signal.

Abstract: In a binary system for generating sound, digital signals representing an audio analog signal are stored in memory, a first voltage level is produced for a time t.sub.1 proportional to the value of a respective stored digital signal, and a second voltage level is produced for a time t.sub.2 =t.sub.c -t.sub.1, where t.sub.c is a fixed clock signal time interval. The first and second voltage levels are successively supplied to a speaker to operate the speaker in a type of frequency modulated mode to produce sound corresponding to the audio analog signal.

Abstract: Analog-to-digital converter is particularly for digital systems requiring a fast and accurate high resolution conversion of an analog input signal into a corresponding digital output code. A comparator compares the input signal against a ramp signal. A plurality of counters is responsive to the comparator for providing the output code. Each counter has a weight and counts subsequently to the counting of the counter having a higher weight. A digital-to-analog converter converts the output code from the counters into a reference signal prior to the counting of each counter. An integrator provides the ramp signal in reference to the reference signal and at a rate corresponding to the weight of the counter currently counting. A switch zeroes the integrator prior to the counting of each counter. An optional flash analog-to-digital converter estimates the input signal and determines an initial count of the counters.

Abstract: A serial-type analog-to-digital converter includes a plurality of serially connected folding circuits. Each folding circuit includes a first operational amplifier having an inverting input connected to an input terminal, and a second operational amplifier having a noninverting input connected to the input terminal. The bases of first and second transistors are respectively connected to the outputs of the first and second operational amplifiers. The emitters of the transistors are commonly connected to an output terminal. Feedback connections are provided for coupling the output terminal to the inverting input of each operational amplifier. Furthermore, circuitry is provided for calculating an estimated offset error based on maximum values of a folded analog signal provided at an output terminal of one of the folding circuits.

Abstract: An analog-to-digital converter comprises an output generator for forming an output signal in response to application of a start signal; a comparator for comparing an analog signal, to be converted to a digital signal, with the level of the output signal formed by the output generator and for providing an output representing the time period from initiation of formation of the output signal to occurrence of a predetermined relation between the output signal and the analog signal; and a clock signal generator. The converter further comprises a digital computer that includes an output terminal from which the start signal is applied to the output generator and an input terminal for receiving the output from the comparator.

Abstract: The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Abstract: The invention is for an analog-to-digital converter which is useful for audio applications owing to its insensitivity to noise. The converter achieves this insensitivity by utilizing a differential, common node integrator having a non-switching capacitive feed-back loop.

Abstract: A ramp voltage generator which utilizes a simple resistance/capacitance charging circuit to generate a linear ramp voltage is reset by means of a shorting transistor connected across the capacitor. The shorting transistor is, in turn, controlled by the output of a flip-flop that responds to set and reset signals applied to the circuit. In order to decrease the overall reset time of the circuit and thereby increase the operational frequency, a current switch is provided which bypasses the flip-flop and immediately diverts current to the shorting transistor upon the application of a reset signal to the circuit.

Abstract: A power steering control unit for use with an electric motor assisted vehicle power steering system. The control unit includes two microprocessor controllers that monitor vehicle speed and a torque applied through a vehicle steering column in calculating a duty cycle for the assist motor. The response to the speeed and torque inputs can be adjusted by setting a group of four control switches on the vehicle dashboard. Each microprocessor not only calculates an optimum motor energization but also monitors motor performance. In the event this performance deviates from an expected range the assist is removed and in some cases corrective steps taken to correct the unit's performance. An electrically erasable read only memory coupled to the microprocessors stores constants needed in calculating an energization sequence. The EEROM also stores indicators of the control unit performance to aid in diagnosing difficulties.

Abstract: An addressable transducer interface which may be associated with a particular electrical transducer, comprises means (107) for storing correction data for the correction of errors as herein defined relating to that transducer so that on addressing of the interface by external control means, the correction data may be transmitted to the control means together with measurement data from the transducer. The storing means is arranged to store said correction data in digital form.

Abstract: Analog-to-digital conversion in which a coarse digital representation of an input analog signal is converted to a coarse analog representation, and the difference between the original analog signal and the coarse analog representation is determined. A ramp waveform signal is generated, and a change in that waveform by an amount substantially equal to the difference between the original analog signal and the coarse analog representation is sensed. A plural bit fine digital signal corresponding to the sensed change of the ramp waveform is produced. The combination of the coarse and fine digital signals constitute the digital representation of the input analog signal. In one embodiment, the ramp waveform is increased until it is equal to the difference between the analog signal and the coarse analog representation, whereupon the ramp waveform is digitized.