Abstract: Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal.

Abstract: A method, an apparatus and a device for simultaneously sampling multiples signals and a medium are provided. The method includes: modulating multiple target input signals with CDM, to obtain a single target analog signal; performing ?? modulation on the single target analog signal to obtain a target digital bit stream; demodulating the target digital bit stream to obtain a target demodulated bit stream; and filtering the target demodulated bit stream to obtain multiple target output signals. With the method, the hardware overhead for simultaneous sampling of multiple-channel signals is reduced while ensuring accuracy. Accordingly, the apparatus and the device, and the medium have the above beneficial effects.

Abstract: An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate includes a first PMOS switch controlled by a voltage of a second control node, second PMOS switch controlled by a control voltage, a first control switch unit controlling voltages of first and second control nodes, a first NMOS switch controlled by a voltage of a fourth control node, a second NMOS switch controlled by the control voltage und, and a second control switch unit controlling voltages of third and fourth control nodes.

Abstract: Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.

Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.

Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

Abstract: A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.

Abstract: A motion sensor with sigma-delta analog-to-digital converter (ADC) having improved bias instability is presented herein. Differential outputs of a differential amplifier of the sigma-delta ADC are electrically coupled, via respective capacitances, to differential inputs of the differential amplifier. To minimize bias instability corresponding to flicker noise that has been injected into the differential inputs, the differential inputs are electrically coupled, via respective pairs of electronic switches, to feedback resistances based on a pair of switch control signals. In this regard, a first feedback resistance of the feedback resistances is electrically coupled to a first defined voltage, and a second feedback resistance of the feedback resistances is electrically coupled to a second defined reference voltage.

Abstract: The present disclosure relates to an analog-to-digital conversion circuit comprising: N sampling and conversion modules connected in parallel, configured to simultaneously sample and sequentially convert first analog signals of N channels to output second analog signals, wherein each of the sampling and conversion modules includes a plurality of sampling capacitors connected in parallel, wherein N is an integer greater than 1; a comparator connected to the N sampling and conversion modules, configured to comparing the second analog signals respectively to obtain comparison signals; and a control module connected to the N sampling and conversion modules and the comparator, configured to control the N sampling and conversion modules to output converted digital signals based on the comparison signals.

Abstract: An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

Abstract: A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a plurality of pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.

Abstract: A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

Abstract: Lossless digital cancelation of internally generated spurious products within a signal receiver system is provided. In embodiments, the receiver system generates reference frequencies corresponding to internal components within the receiver (e.g., mixers, oscillators, clocks, analog-digital converters (ADC)) that introduce spurious products into the digitization of a received RF signal. The receiver system precisely duplicates each introduced spurious product based on the reference frequencies and filters out each corresponding spurious product out of the digitized signal. Individualized canceler circuits for each introduced spurious product adjust the corresponding duplicate spurious products to cancel out the introduced spurious product from the digitized signal, resulting in an output signal free of self-generated interference.

Abstract: A voltage detector comprises an input, a resistor divider circuit having resistors coupled in series with one another between the input and a reference node, and N intermediate nodes joining adjacent pairs of the resistors. The voltage detector has N switches coupled to the respective intermediate nodes, as well as a comparator with an input coupled to the switches, a state machine having an input coupled to the output of the comparator, and a decoder having N decoder outputs coupled to respective control terminals of the N switches.

Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors and compare signals at outputs of the switched capacitors. The SAR ADC may also determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated and update the value of the tunable time interval based on whether the metastability flag was set.

Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N?K)th capacitor, and a constant binary weight from the (N?K)th capacitor to a (N?K?2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.

Abstract: A successive approximation register analog to digital converter includes a sampling circuitry, a comparator circuit, and a controller circuitry. The sampling circuitry generates first and second signals according to a sampled signal. The comparator circuit compares the first signal with the second signal to generate first decision signals. The controller circuitry generates digital codes according to the first decision signals, and controls the comparator circuit to perform comparisons repeatedly to generate second decision signals, in order to generate a digital output according to the digital codes, a statistical noise value, and the second decision signals.

Abstract: The invention relates to a power providing device (2) for providing power to a plurality of power receiving devices (31), a power distribution system including such power providing device (2), a method for providing power to a plurality of power receiving devices (31) and a corresponding computer program. During standby the power providing device (2) is beneficially supplied with power coming from a power source (1) dedicated or adjusted for the low energy consumption, e.g. a uplink port (23) or a shared power bus. The current drawn from such power source (1) (or the power provided to the downlink power receiving devices (31)) is measured and, for example, the derivative is used in order detecting a current increase just when it starts. This information may be used such the main power supply (29) gets started in order to be available for more power demand than available through the hierarchical powering coming from the standby power source (1).

Abstract: A touch processing circuit includes: a front-end circuit including an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches each having two ends that are selectively connected each other, the front-end circuit being configured to process an input signal varying according to a touch; and a controller controlling the plurality of switches so that the front-end circuit is configured as a first circuit that accumulates deviation of the input signal between a first phase and a second phase during an integration period and a second circuit that converts the accumulated deviation into a digital signal during a conversion period.

Abstract: Multiple adjustment capacitors corresponding to multiple source bus lines on a one-to-one correspondence basis are arranged. Each adjustment capacitor includes a first electrode supplied with an adjustment signal and a second electrode connected to the source bus line. The adjustment capacitors are divided into multiple groups. An adjustment signal having a amplitude different from group to group is supplied to the adjustment capacitor. A potential of the adjustment signal is raised after a liquid-crystal capacitor is charged in a pixel formation region including a thin-film transistor (TFT) that is turned on with a gate driver causing a scanning signal to rise and before the gate driver causes the scanning signal to fall.

Abstract: Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential.

Abstract: A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.

Abstract: There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal.

Abstract: Apparatus and methods of impedance sensing are described. One method includes performing a first digital conversion of an attribute of a sensor electrode and performing a second digital conversion of the attribute of the sensor electrode. The second digital conversion differs by at least one characteristic from the first digital conversion. The method further includes calculating a resistance of the sensor electrode from a first and second digital value of the first and second digital conversions, respectively; and calculating a capacitance of the sensor electrode from the first and second digital value of the first and second digital conversions, respectively.

Abstract: Apparatuses and methods for analog-digital conversion and corresponding systems having a sensor and an apparatus of this type are provided. Demodulation is executed with no variable preamplification, followed by continuous-time analog-digital conversion, at least in time segments, which further employs chopper techniques.

Abstract: An ADC system comprises a coarse ADC for determining a coarse word representing an input signal, and an incremental ADC for determining a fine word based on a combination of the input signal and a feedback signal. A first combiner generates a first intermediate output word by joining the coarse word and the fine word. A feedback path generates the feedback signal based on the first intermediate output word. A decimation filter generates a second intermediate output word by filtering the first intermediate output word. A correction block determines a correction word based on the coarse word, on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word by addition of the second intermediate output word and the correction word.

Abstract: An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

Abstract: An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.

Abstract: An analog-digital conversion circuit is disclosed for comparing a comparison potential with a reference potential generated based on a reference power supply to convert a comparison potential to a digital value. An analog-to-digital converter generates the comparison potential based on a sampled and held input potential, the digital value, and the reference power supply. A current amount control unit controls current amount flowing to the current amount control element in each bit circuit. In response to second switches of the bit circuits being turned on in order from the upper bit in each bit circuit by the digital value, the current amount control unit applies a current control potential to the current amount control element in any of the bit circuits that the noise current is more than allowable value while the noise current proportional to the charge flowing from the capacitor is more than the allowable value.

Abstract: Techniques are disclosed to compensate for changes in the impedance of stage(s) preceding a trans-impedance amplifier (TIA) that is used within an RF chain. The techniques identify the changes in the source impedance value of the input stage (e.g., the mixers and LNAs) as a result of a gain state change, which alters the signal-to-transfer function (STF) of the TIA during operation and negatively impacts radio performance. The STF is maintained for changes in the source impedance value throughout different gain states without using switchable shunt components by using tunable elements to compensate for the source impedance changes, thus keeping the STF constant.

Abstract: An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.

Abstract: Apparatuses and methods of capacitance-to-digital code conversion are described. One apparatus includes a bridge circuit and a modulator front-end circuit. The bridge circuit includes a first terminal to couple to a reference cell and a second terminal to couple to a sensor cell. The modulator front-end circuit includes a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator. The modulator front-end circuit provides a digital bitstream. A duty cycle of the digital bitstream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell.

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

Abstract: A successive-approximation register analog-to-digital converter (SAR ADC), a correction method and a correction system are provided. The SAR ADC generates an original weight value sequence according to multiple original weight values. The SAR ADC converts an analog time-varying signal to establish a transforming curve corresponding to the original weight values. In addition, the SAR ADC generates an offset value sequence according to an offset of the transforming curve, uses the offset value sequence to correct the original weight value sequence to generate a corrected weight value sequence, and uses multiple corrected weight values of the corrected weight sequence to improve linearity of the transforming curve.

Abstract: A mixed analog-to-digital converter circuit capable of stabilizing voltages at two ends of a load and reducing output voltage ripples, includes a power supply, a digital converter, an analog converter, and a load assembly. The analog converter includes power supply capacitors arranged in parallel; and when working, the load assembly is connected to corresponding power supply capacitors, and the power supply capacitors not connected to the load assembly are connected to the digital converter. The digital converter includes a component multiplexer connected to input and output ends of a power supply through wires; the component multiplexer includes power supply capacitors arranged in series; the analog converter includes the component multiplexer; two ends of each power supply capacitor in the component multiplexer are respectively connected to input and output ends of the load assembly through discharge wires; and when working, the load assembly is connected to corresponding power supply capacitors.

Abstract: A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

Abstract: A time-interleaved analog to digital converter includes capacitor array circuits, at least one successive approximation register circuitry, and at least one noise shaping circuitry. The capacitor array circuits are configured to alternately sample an input signal, in order to generate a sampled input signal. The at least one successive approximation register circuitry is configured to perform an analog to digital conversion according to the sampled input signal and a residue signal, in order to generate at least one digital output. The at least one noise shaping circuitry is configured to utilize at least one first circuit in switched-capacitor circuits to transfer the residue signal from a first capacitor array circuit in the capacitor array circuits, and randomly select at least one second circuit from the switched-capacitor circuits to cooperate with a second capacitor array circuit in the capacitor array circuits to sample the input signal.

Abstract: The present invention provides a circuit applied to a biopotential acquisition system, wherein the circuit includes an active current source and an amplifier. In the operations of the circuit, the active current source is configured to provide a current to two input terminals of the circuit, wherein the two input terminals of the circuit are coupled to two input electrodes of the biopotential acquisition system; and the amplifier is configured to receive input signals from the two input terminals to generate an output signal.

Abstract: An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

Abstract: A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a Kth sampling period, a quantization error signal for a Kth period according to an internal signal, a quantization error signal for a (K?1)th period, a filtered quantization error signal for the (K?1)th period and a filtered quantization error signal for a (K?2)th period; an integrating capacitor configured to store the quantization error signal for the Kth period, to weight the internal signal in a (K+1)th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the Kth period in a Kth discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1)th sampling period and a (K+2)th sampling period; and a comparator configured to quantize the quantization error signal for the Kth period.

Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Abstract: Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

Abstract: An analog-to-digital conversion device and analog-to-digital conversion method thereof are provided. The analog-to-digital conversion device includes an analog circuit configured to output an analog input signal, and an analog-to-digital converter configured to receive the analog input signal and configured to outputting a digital output signal corresponding to the analog input signal with the use of first and second capacitor arrays, each of the first and second capacitor arrays including a first capacitor having a calibration capacitor connected thereto and a second capacitor having no calibration capacitor connected thereto, wherein the analog-to-digital converter is configured to calibrate the capacitance of the first capacitor by providing a first calibration voltage to the calibration capacitor and is configured to output the digital output signal corresponding to the analog input signal with the use of the calibrated capacitance of the first capacitor.

Abstract: An optimal detection voltage obtaining method, a reading control method and an apparatus are provided.

Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

Abstract: A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.

Abstract: A capacitor circuit includes a first capacitor bank and a second capacitor bank. The first capacitor bank includes p switch-capacitor circuits connected to each other in parallel, where p is a natural number of 2 or more, wherein at least two switch-capacitor circuits among the p switch-capacitor circuits have mutually different capacitance values based on a first weight. The second capacitor bank includes q switch-capacitor circuits connected to each other in parallel, where q is a natural number greater than p, wherein at least two of the q switch-capacitor circuits have mutually different capacitance values based on a second weight different from the first weight.

Abstract: In certain aspects, an analog-to-digital converter (ADC) includes a comparator having a first input, a second input, and an output. The ADC also includes a digital-to-analog converter (DAC) coupled to the first input of the comparator, a switching circuit, a first capacitor coupled between the first input of the comparator and the switching circuit, a second capacitor coupled between the first input of the comparator and the switching circuit, and an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to the switching circuit. The ADC further includes a first switch coupled between the output of the amplifying circuit and the DAC, and a successive approximation register (SAR) having an input and an output, wherein the input of the SAR is coupled to the output of the comparator, and the output of the SAR is coupled to the DAC.

Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.