Abstract: The successive approximation A/D converter includes: switch groups 105—1 to 105—x each of which is connected to the other end of each corresponding capacitor of capacitors 106—1 to 106—x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.

Abstract: A capacitive voltage divider arrangement includes a first and second voltage divider and a first and second parasitic capacitance formed between the first and second capacitive voltage divider. The first capacitive voltage divider includes: a signal terminal; first capacitance for coupling the terminal to a reference potential; second capacitance; and third capacitance that is coupleable to the reference potential, the second capacitance being coupled in-between the terminal and third capacitance.

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract: An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.

Abstract: A switched-capacitor amplifier comprises an operational amplifier (op-amp), a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a plurality of switches connected to these capacitors. The first capacitor equals the third capacitor, the second capacitor equals the fourth capacitor, and the first capacitor is asymmetric to the second capacitor, the third capacitor is asymmetric to the fourth capacitor. A ratio of the first capacitor and the second capacitor is a function of a simulated parasitic capacitance of the switched-capacitor amplifier, a simulated DC gain of the operational amplifier, and a target gain of the switched-capacitor circuit.

Abstract: A differential analog-digital converter is provided. The converter comprises a decision unit for evaluating a potential difference between two input signal lines, a number of charging units for each input signal line each configured to add a predetermined charge onto the respective input signal line, a number of discharging units for each input signal line each configured to remove a predetermined charge from the respective input signal line and a control unit for selectively switching each of the charging units and discharging units so that depending on one result of evaluating the potential difference between the two input signal lines one of the input signal lines is charged by adding the predetermined charge of the respective switched charging unit while the respective other of the input signal lines is discharged by removing the predetermined charge of the respective switched discharging unit.

Abstract: A circuit including an amplifier. The circuit includes N capacitances that include first ends and second ends. The first ends communicate with an input of the amplifier. A first switch is configured to selectively connect the input of the amplifier to a reference potential during a first phase. N switches are configured to connect each of the second ends of the N capacitances to a voltage input, the reference potential and a voltage reference and selectively connect each of the second ends of the N capacitances to one of a voltage input, the reference potential and a voltage reference during a second phase. The first and second phases are non-overlapping.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: A multiplying analog-to-digital converter is provided. A sample-and-hold unit samples an analog signal, to obtain a sample level. A analog-to-digital converting unit converts the analog signal to a digital signal. A digital-to-analog converting unit converts the digital signal to a recovered signal level. A operating unit provides an output signal according to the difference between the sample level and the recovered signal level. A comparator compares a level of the output signal with an upper threshold level and a lower threshold level, and accordingly provides an indicating signal, wherein the upper and lower threshold levels define a predetermined level range. When the indicating signal indicates that the level of the output signal is outside the predetermined level range, a controller shifts a value of the digital signal and accordingly provides an adjusted digital signal.

Abstract: The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-n) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . . , b0) in the digital output word that correspond to the capacitors (Cn-1, . . .

Abstract: A charge redistribution SAR analog-to-digital converter includes a source of a reference voltage, a digital-to-analog converter, and a reset circuit. The digital-to-analog converter includes converter stages that range in significance from most significant to least significant. Each converter stage includes respective capacitors and switches. The switches are controllable to selectively connect the capacitors to the reference voltage or to ground. The capacitors of the converter stages are weighted in capacitance in accordance with significance of the converter stage. The reset circuit is to control the switches to reset the converter stages with a temporal offset between at least two of the converter stages. The temporal offset between the at least two of the converter stages reduces the dependence of the charge drawn from the reference voltage source during each conversion cycle on the sample of an analog input signal converted to a digital value during the conversion cycle.

Abstract: A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

Abstract: The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (Cn-1, . . . , Co) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (Cn-1, . . . , Co) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . .

Abstract: A SAR ADC and a method thereof are provided. Particularly, in each bit determining duration of last several bit determining durations, a comparer is used to consecutively compare a first potential with a second potential on a sampling and digital-to-analog converting circuit a plurality of times to obtain a plurality of comparison results, and then an SAR control circuit generates a corresponding output bit according to the obtained plurality of comparison results.

Abstract: A successive approximation (SA) analog-to-digital converter (ADC) capable of estimating its own capacitance weight errors includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

Abstract: A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising a differential amplifier, a first capacitor, one terminal of the first capacitor being connected to a non-inverting input terminal of the differential amplifier, a second capacitor, one terminal of the second capacitor being connected to an inverting input terminal of the differential amplifier, a first switch configured to connect the other terminal of the first capacitor to one of a first reference voltage and a second reference voltage, a second switch configured to connect the other terminal of the second capacitor to one of the first reference voltage and the second reference voltage, and a third switch configured to connect the other terminal of the first capacitor to the other terminal of the second capacitor.

Abstract: An analog to digital converting system (200) includes an analog to digital converter (ADC) circuit that is formed by a plurality of parallel ADCs (ADC 1 ADC N) for continuous sequential processing of an input analog voltage signal. Each of the ADCs is a type that employs a capacitor digital to analog converter (DAC) (209, 701) therein. The system further includes a sample and hold circuit (220) coupled to the parallel ADCs by a conductive interconnect wiring pattern (203). The sample and hold circuit includes a sampling switch (207) and a hold capacitance formed by the parallel combination of a hold capacitor (205) and the distributed parasitic capacitance (204) of the conductive interconnect wiring pattern (203). During the hold phase of the sample and hold circuit, charge is redistributed from the hold capacitance to all of the capacitors (211) of the capacitor DAC, which serve as a secondary hold capacitance.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N?1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.

Abstract: A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.

Abstract: To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps, an AD converter includes: a signal generation unit that generates a ramp voltage based on a count signal; a signal conversion unit including a circuit that holds an input signal voltage, a successive approximation capacitance group that outputs bias voltages according to a connection combination of capacitances having different capacitance values, and a unit that compares one of the ramp voltage and the bias voltage with the signal voltage; and a control unit generating a digital signal of the signal voltage based on a comparison result of the bias voltage and the comparison result of the ramp voltage while acquiring data for calibration of the capacitance group based on the connection combination and the ramp voltage.

Abstract: A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.

Abstract: Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.

Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.

Abstract: Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.

Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) includes an amplifier, a first variable capacitance circuit coupled to a first input to the amplifier, a second variable capacitance circuit coupled to a second input to the amplifier, a third variable capacitance circuit coupled to a first output of the amplifier, and a fourth variable capacitance circuit coupled to a second output of the amplifier. An output of the third and fourth capacitance circuits are coupled to one another and to inputs to the first and second variable capacitance circuits. Capacitance values of the first, second, third and fourth variable capacitance circuits are higher when inputs to the ADC correspond to a selected number of more significant bits than when inputs to the ADC correspond to a remaining number of less significant bits.

Abstract: A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ?? modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract: A successive approximation ADC made of a low voltage configurable differential amplifier and low voltage logic circuits which can convert a high voltage analog input to a digital equivalent. The differential amplifier can be configured as either an op amp or a comparator depending upon the mode of operation. An input capacitor C1 is switchably coupled to an electrode selected for voltage sampling. A switched capacitor array C2 is coupled across the differential amplifier input and output. A SAR coupled to the switched capacitor array provides a digital output corresponding to the sampled analog voltage. During a sampling interval and a charge transfer interval, the differential amplifier is configured as an op amp. During the transfer interval, the voltage on the input capacitor multiplied by the ratio C1/C2 is transferred to the switched capacitor array. During an analog to digital conversion interval, the ADC converts the analog voltage to an equivalent digital output.

Abstract: The present invention provides an integration and analog to digital conversion circuit sharing common capacitors. The circuit comprises a capacitor array module, an integration circuit, and an analog to digital conversion (ADC) logic. The capacitor array module has a plurality of capacitors. The integration circuit is configured to integrate an analog signal by the capacitor array module. The ADC logic is configured to convert the output of the capacitor array module to a digital signal.

Abstract: An analog to digital converter can operate in a sampling mode or in a comparing mode. The analog to digital converter comprises: a comparator; a first capacitor, comprising a first terminal coupled to a first input terminal of the comparator; a second capacitor; a first switch module; a control unit, for controlling the conductive states of the first switch module corresponding to the sampling mode or the comparing mode. The first capacitor samples a value of a first input signal and the second capacitor samples a value of a first reference signal via the first switch module in the sampling mode. The first capacitor and the second capacitor are not coupled to each other in the sampling mode. The first capacitor and the second capacitor are coupled in series via the first switch module in the comparing mode.

Abstract: This disclosure relates to analog to digital converter (ADC) component with a comparator function for analog signals.

Abstract: Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract: An ADC includes a comparator and first and second amplifier circuits including a fully-differential operational amplifier. The comparator converts an analog signal output from the operational amplifier into digital data. The first amplifier circuit stores charge corresponding to a signal having a phase reverse to an input signal in each of a pair of capacitors during a first period and transfers the charge in one of the pair of capacitors to the other via the operational amplifier during a second period to amplify the reversed phase signal twofold. The second amplifier circuit amplifies the input signal twofold similarly to the first amplifier circuit.

Abstract: A balanced signal processing circuit includes: a comparator; a first capacitor having a first end connected to a non-inverting input terminal of the comparator; a second capacitor having a first end connected to an inverting input terminal of the comparator; a first switch configured to apply a voltage signal to the first end of the first capacitor; a second switch configured to apply a voltage signal to the first end of the second capacitor; an operation state detection section configured to detect an operation state of the comparator; and an offset voltage correction section configured to apply a predetermined offset voltage to a second end of the first capacitor and a second end of the second capacitor when the operation state detection section detects an abnormal operation state of the comparator.

Abstract: An arithmetic operation circuit provided in a delta-sigma modulator of a delta-sigma A/D converter includes two reference capacitors which are respectively provided at a positive side input node and a negative side input node of an operational amplifier. When a signal corresponding to an output of the modulator is added or subtracted to or from an input signal, the amount of charge added to the input node of the operational amplifier is made to be always the same regardless of the reference voltage by complementarily switching the connection of the reference capacitors at the positive side input node and the negative side input node, and thereby the potential of the input node of the operational amplifier is made to converge to the common mode potential of the circuit.

Abstract: A pipeline analog-to-digital converter is disclosed. An example of a pipeline analog-to-digital converter comprises a plurality of stages. Each of the plurality of stages comprises an analog-to-digital conversion circuit comprising a comparator configured to produce an n-bit digital domain output; and a switchable conductance digital-to-analog conversion circuit operatively coupled to the comparator and configured to switch between at least two conductance values in response to a value of the n-bit digital domain output.

Abstract: Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is accumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.

Abstract: A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.

Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input.

Abstract: A quantizer includes a voltage reference network and a set of comparators coupled with the voltage reference network. The voltage reference network generates a plurality of reference voltages. Each of the comparators receives an input signal and produces a sequence of digital samples. The set of comparators includes first, second, and third subsets of comparators. Each comparator of the first subset includes a switched capacitor stage, each comparator of the second subset includes a preamplifier stage, and each comparator of the third subset includes a switched capacitor stage. The first and third subsets of comparators compares the input signal with reference voltages corresponding to the upper and lower voltage ranges of the input signal, and the second subset of comparators compares the input signal with reference voltages corresponding to the middle voltage range of the input signal.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

Abstract: This A/D convertor includes: a first D/A conversion unit configured to sample an analog input signal, and to generate a first difference signal by performing successive comparison of the analog input signal based on a reference voltage; a precharge capacitor unit configured to hold the reference voltage; a first comparing unit configured to compare the first difference signal with a reference value to generate a first digital signal; and an amplifying unit configured to calculate by using the first difference signal and the reference voltage to generate a residual signal.

Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Abstract: An analogue to digital converter includes a first input connection to receive a first part of the analogue input signal, a second input connection to receive a second part of the analogue input signal, a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors During a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors and the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors. Further, a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of a digital output signal.

Abstract: A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.