Abstract: The invention is a novel scheme of performing an analog to digital conversion of simultaneous sampled analog inputs using multiple sample and hold circuits and a single successive approximation analog to digital converter (“SAR ADC”). Each of the analog inputs are stored on capacitors in the sample and hold circuits, and the sample and holds are sequentially connected to the capacitor DAC. After the digital conversion of the of the input signals stored on a sample and hold, the connected sample and hold is disconnected and the charge on the DAC is reset before the next sample and hold circuit is connected. The process is repeated until all analog inputs have been converted.

Abstract: A column A/D converter includes two column A/D converting elements. Each of the column A/D converting elements is operable to divide a pixel signal read out from a pixel array into two blocks i.e. an upper block constituted of upper two bit data, and a lower block constituted of lower two bit data, and sequentially perform A/D conversion with respect to the blocks in the unit of one horizontal scanning period. A controller causes each of the column A/D converting elements to concurrently perform A/D conversion with respect to different blocks of pixel signals at different rows.

Abstract: Provided is an AD conversion apparatus including: a differential amplifier that generates a differential input voltage according to an analog input signal; a differential DA converter of a charge redistribution type, which outputs a differential output voltage resulting from subtracting the differential input voltage from a differential comparison voltage that is in accordance with comparison data; a comparator that compares a positive output voltage and a negative output voltage in the differential output voltage; a control section that identifies the comparison data at which the differential output voltage becomes substantially 0 based on a comparison result of the comparator, and outputs the identified comparison data as output data; and a setting section that sets at least one of a common potential of the differential amplifier and a common potential of the differential DA converter, according to a targeted value of a common potential of the comparator

Abstract: A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Abstract: An analogue to digital converter (ADC) is provided which comprises an signal sampling device, a signal comparison device, and a digital signal generator. An analogue signal to be converted to a digital signal is input into the ADC, the signal sampling device produces samples of the analogue signal, the signal comparison device receives the analogue signal and the analogue signal samples, performs a comparison between them and outputs comparison signals, and the digital signal generator receives the comparison signals and uses them to generate a digital signal. The signal sampling device may produce voltage samples or current samples of the analogue signal.

Abstract: An A/D converter device is provided, which has a D/A conversion function and changes a resolution of A/D conversion and D/A conversion. The A/D converter device is configured to selectively execute an A/D conversion operation and a D/A conversion operation, by the operation of a control circuit controlling switching of switches according to an ADC/DAC function switching signal supplied from an external side. The A/D conversion operation performs A/D conversion of an input signal voltage inputted via a signal input terminal from an external side and outputs an A/D conversion value of 12 bits. The D/A conversion operation outputs, via a signal output terminal, an analog voltage produced by performing D/A conversion of a digital value supplied from the external side.

Abstract: According to embodiments of the present technique, a system and a method for obtaining low-noise measurements for a wide range of analog signal strengths is provided. According to aspects of the present technique, a low-gain measurement of an input pixel charge is performed, wherein the input pixel charge is distributed to two feedback capacitors, which together provide a relatively low integrator gain. After the low-gain measurement, a high-gain measurement is performed, wherein one of the capacitors is remove from the feedback loop and the charge is redistributed to the remaining capacitor.

Abstract: An A/D conversion apparatus includes: a first and a second D/A converter to sample an analog signal and successively compare the analog signal and a reference signal to generate a first and a second comparison signal respectively; a first comparator to compare the first comparison signal generated by the first D/A converter with a benchmark signal; a second comparator to compare the second comparison signal generated by the second D/A converter with the benchmark signal; and a converter to convert the analog signal to a digital signal according to results of the comparisons by the first and second comparators.

Abstract: A digital-to-analog converter generates a voltage from power supply and ground voltages, generates upper and lower limit reference voltages for a reference width which regards the generated voltage as an intermediate potential, converts a change in an analog input signal with respect to the upper and lower limit reference voltages into a digital code, and performs a control in order to achieve a sample and hold of the analog input signal.

Abstract: A pipelined analog to digital converter that includes a first stage and a second stage. The first stage is configured to (i) receive a first phase component and a second phase component and (ii) generate a first integrated component and a second integrated component. The second stage is configured to sample and integrate the first integrated component and the second integrated component. The first stage is configured to: sample the first phase component to generate a first sampled component; sample the second phase component to generate a second sampled component; during a first portion of a first clock phase, (i) sample the first phase component and (ii) integrate the second sampled component to generate the second integrated component; and during a second portion of the first clock phase, (i) sample the second phase component and (ii) integrate the first sampled component to generate the first integrated component.

Abstract: A control circuit connects a capacitor to an input terminal and an output terminal of an operational amplifier and applies a signal charge to charge the capacitor with a switch being turned off. Thus, a conversion voltage corresponding to the signal charge is outputted from the operational amplifier. The control circuit then sets charges, which correspond to the conversion voltage, in capacitors and reallocates the charges among the capacitors by connecting non-common electrodes of the capacitors to either one of a plurality of reference voltage lines in accordance with a conversion result of an A/D conversion circuit with the capacitor being connected to the input terminal and the output terminal of the operational amplifier. The control circuit thereafter performs, a number of times, charge setting, initialization and subsequent charge reallocation in accordance with a residual voltage outputted from the operational amplifier.

Abstract: A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2?-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.

Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) with a compact structure comprises a loop filter, a summing circuit, a quantizer, and a current Digital to Analog Converter (DAC). The loop filter is utilized for receiving and noise-shaping an analog input signal, and accordingly outputting a positive and a negative loop voltages. The summing circuit comprises a positive and a negative summing resistors. The summing resistors are utilized for transforming a positive and negative feedback currents to be a positive and a negative feedback voltages, and summing the loop voltages and the feedback voltages so as to generate a positive and a negative summing voltages, respectively. The quantizer is utilized for outputting a digital output signal according to a difference between the positive and the negative summing voltages. The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal.

Abstract: A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.

Abstract: This disclosure relates to analog to digital converter (ADC) component with a comparator function for analog signals.

Abstract: A D/A converter includes plus-side and minus-side input terminals; plus-side and minus-side D/A converters each including plural plus-side or minus-side capacitors having capacitance values weighted by the powers of two, a plus-side or minus-side output terminals connected to first electrodes of the plus-side or minus-side capacitors, and plural plus-side or minus-side switches for connecting each second electrode of the plus-side or minus-side capacitors to either the plus-side or minus-side input terminal, a plus-side reference voltage terminal or a minus-side reference voltage terminal according to plus-side or minus-side control digital signals; and plural short-circuit switches provided between identically weighted plus-side and minus-side capacitors respectively.

Abstract: A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.

Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (4)1) to a first input voltage (±Vm) and on a second clock signal (?1) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negative

Abstract: A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b, 22c, 22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr).

Abstract: Methods and systems are described for providing an analog-to-digital converter that uses reduced power and supply voltage. The analog-to-digital converter includes a sample phase configured to sample an incoming analog signal having an input signal range and compare the incoming analog signal to a reference voltage. The analog-to-digital converter also includes a feedback phase wherein the feedback phase receives sampled signal data corresponding to the incoming analog signal from the sample phase and is configured to produce an output signal comprising an output signal range, wherein the output signal range is equal to one half of the input signal range, and wherein the analog-to-digital converter has a feedback factor that is substantially greater than ?.

Abstract: Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.

Abstract: Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipeline analog-to-digital converter includes a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade. At least one of the MDAC stages includes two or more flash ADCs connected in parallel, operating alternately to generate digital signals from an analog input voltage. In one embodiment, the flash ADCs provide the digital signals in an alternating manner to a capacitor block that receives a delayed analog input voltage. In another embodiment, the at least one MDAC may include two or more capacitor blocks, each of which is associated with a respective one of the flash ADCs, forming two or more sets of a flash ADC and a capacitor block. In yet another embodiment, the at least one MDAC also include three or more capacitor blocks, each of which can be randomly selected for one of the flash ADCs.

Abstract: A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register.

Abstract: An analog-to-digital converter circuit includes: a capacitor array including a plurality of first capacitors, each having a first terminal connecting to a common node and having a capacitance represented by the nth power of 2 (2n) on the basis of the smallest of the capacitances of the first capacitors=1; a second capacitor for contributing to attenuation of the voltage on the common node; a switch array, each switch of the switch array supplying and disconnecting one of a first reference voltage, a second reference voltage, and the voltage of an input signal to and from a second terminal of an associated one of the first capacitors; a second switch supplying and disconnecting a third reference voltage to and from the common node; a comparator comparing a voltage on the common node with the third reference voltage; and a control circuit controlling the first switches and the second switch.

Abstract: An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage.

Abstract: Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipelined analog-to-digital converter includes a control and correction circuit; and a plurality of MDAC stages. At least one of the MDAC stages includes: an MDAC input to receive an analog input voltage; and a dual latch flash ADC comprising one or more dual latch comparators. At least one of the dual latch comparators includes: a pre-amplifier having an input coupled to the MDAC input, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch may generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch may generate a second digital signal.

Abstract: An analog to digital conversion circuit and method is presented. The analog to digital circuit (100) comprises a first capacitor (103), arranged for being switchably (102) connected on one side to an input voltage (101), at least one successive approximation circuit (104), a comparator (108) arranged for outputting a sign indicative of the difference between the voltage on the first capacitor (103) and a comparison voltage (109), and a control block (110), arranged for converting said comparator's output into steering signals and in a digital output signal. The successive approximation circuit comprises a second capacitive structure (106), switchably connected to a pre-charge circuit (107) arranged for pre-charging the second capacitive structure (106), whereby the second capacitive structure (106) is connected in parallel with the first capacitor (103) via a charge copying circuit (105).

Abstract: In one embodiment, an A/D converter samples an analog input signal voltage by applying the input signal to a first capacitor terminal, while a second capacitor terminal is connected to ground via an NMOS sampling switch, to charge the capacitor to the input signal voltage. During an analog-to-digital conversion process, the second capacitor terminal may swing in a voltage range that extends below ground. A controller circuit provides bias voltage signals to a gate terminal and to a p-well of the NMOS sampling switch, to selectively turn the sampling switch on and off. In a first step of a multi-step sampling process, the controller very quickly discharges the gate terminal to ground to isolate a quantity of charge on the second capacitor plate. In a subsequent step of the sampling process, the controller circuit applies a negative voltage to the gate terminal and p-well to ensure that the quantity of change is substantially preserved during the ensuing analog-to-digital conversion process.

Abstract: A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising a differential amplifier, a first capacitor, one terminal of the first capacitor being connected to a non-inverting input terminal of the differential amplifier, a second capacitor, one terminal of the second capacitor being connected to an inverting input terminal of the differential amplifier, a first switch configured to connect the other terminal of the first capacitor to one of a first reference voltage and a second reference voltage, a second switch configured to connect the other terminal of the second capacitor to one of the first reference voltage and the second reference voltage, and a third switch configured to connect the other terminal of the first capacitor to the other terminal of the second capacitor.

Abstract: A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising an amplifier, at least one capacitor, one terminal of the capacitor being connected to an input terminal of the amplifier, and a first switch configured to selectively connect the other terminal of the capacitor to one of a first reference voltage, a second reference voltage, and a third reference voltage, wherein the first switch connects the other terminal of the capacitor to the first reference voltage so as to perform offset correction of ternary weight 0, the first switch connects the other terminal of the capacitor to the second reference voltage so as to perform offset correction of ternary weight 1, the first switch connects the other terminal of the capacitor to the third reference voltage so as to perform offset correction of ternary weight 2.

Abstract: With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.

Abstract: An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.

Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.

Abstract: A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.

Abstract: An apparatus for analog-to-digital conversion using successive approximation is provided, which is adapted to be supplied with a single ended supply voltage. The device includes: a first analog-to-digital conversion stage including a first set of capacitors coupled with a side at a common node and adapted to sample an input voltage and to be coupled to either a first reference voltage level or a second reference voltage level, at least one capacitor of the first set of capacitors being adapted to be left floating, a control stage being adapted to connect the at least one floating capacitor to the first reference voltage level or the second reference voltage level in response to an analog-to-digital conversion decision made by a second analog-to-digital conversion stage. The first analog-to-digital conversion stage is operable to couple the common node to a supply voltage level, in particular ground, during analog-to-digital conversion.

Abstract: An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code.

Abstract: A circuit for converting a charge signal into a binary format of output bits comprises: an integration circuit including an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between the inverting input terminal and the output terminal, the integrating capacitor for storing a charge input selectively provided by a sensor diode; and a folding circuit having a fold capacitor, the fold capacitor switchably coupled either to a fold voltage source via a fold buffer for charging the fold capacitor to a predetermined fold charge value, or to the integrating capacitor for selectively removing at least a portion of the stored charge input.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: A successive approximation A/D converter includes a capacitive D/A converter including capacitors, and generates a voltage based on the input voltage and a first digital signal including J bits; a resistive D/A converter that generates a voltage based on a second digital signal; a capacitor that capacity-couples the voltage to an output node; a comparator that generates a result based on the voltage; a control circuit that supplies the first digital signal to the capacitive D/A converter according to the result and outputs a third digital signal indicating a correction and a fourth digital signal including K bits; and a digital calculating circuit that generates the second digital signal including K bits based on the third digital signal and the fourth digital signal, and supplies the second digital signal to the resistive D/A converter, a (J+K) bit digital data is generated based on the input signal.

Abstract: Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipelined analog-to-digital converter includes a control and correction circuit; and a plurality of MDAC stages. At least one of the MDAC stages includes: an MDAC input to receive an analog input voltage; and a dual latch flash ADC comprising one or more dual latch comparators. At least one of the dual latch comparators includes: a pre-amplifier having an input coupled to the MDAC input, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch may generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch may generate a second digital signal.

Abstract: A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced.

Abstract: A low-power communication interface, such as used with 10 Gigabit Ethernet, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline.

Abstract: Method and system for analog-to-digital conversion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a different operational amplifier, which includes a first output, a second output, a first input, and a second input. The operational amplifier is associated with an amplification factor. The integrated circuit also includes a first voltage input. The first voltage input can be characterized by a first voltage. Additionally, the integrated circuit includes a second voltage input. The second voltage input can be characterized by a second voltage. Furthermore, the integrated circuit includes a first voltage source configured to provide a first reference voltage. In addition, the integrated circuit includes a second voltage source configured to provide a second reference voltage. Furthermore, the integrated circuit includes a first capacitor being electrically coupled to the first input and disengageably coupled to the first voltage input.

Abstract: In one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second i

Abstract: A K-Delta-1-Sigma modulator filters or integrates (Sigma) the difference (Delta) between K-feedback paths and an input signal. By using K-feedback paths the topology enables sample rates that are K times the clock frequency of any one feedback path. The sigma block can be implemented in a number of ways including an active or passive integrator or a filter with specific characteristics. When implemented as an integrator, the sigma block is common to all the feedback paths, so that the modulation noise is pushed to a portion of the spectrum where it can be reduced by filtering. The delta block can be implemented in a number of ways including analog adders or switched capacitors.

Abstract: A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal.

Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: A pipeline analog-to-digital converter (ADC) comprises a plurality of pipeline stages is disclosed. The first pipeline stage has programmable gain function. The first pipeline stage includes a sub-analog-to-digital converter (sub-ADC) and a multiplying digital-to-analog converter (MDAC) implemented by switched capacitor (SC) circuits. Different capacitances in the sub-ADC and MDAC are provided so as to provide different gains by controlling switches in the SC circuits.

Abstract: A solid-state image pickup device includes a pixel array including pixels arranged in a matrix, a pixel signal readout unit, and a timing control unit for controlling processing of the pixel signal readout unit by using a timing signal. The pixel signal readout unit includes: a plurality of comparators for comparing a readout signal potential with a reference voltage to generate a determination signal and outputting the determination signal, and a plurality of counters. Each counter counts a comparison time of each corresponding one of the comparators. The timing control unit (a) divides a predetermined processing period into at least a first-time readout period, a first comparison period, a second-time readout period, and a second-time comparison period, (b) classifies the periods into two periods, and (c) generates a timing signal of processing of each divided period by counting for each divided period in the counter.