Abstract: An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal.

Abstract: A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN?) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage.

Abstract: A multiplying digital-to-analog converter suited to maintain impedance balancing during phases. In an embodiment, an input signal may be sampled onto nodes of impedance elements during an initial phase. In a second phase the impedance elements are directly coupled either to a non-inverting reference input or the inverting reference input of an amplifier depending on an output of a related flash ADC output. The determination as to which capacitor is to be coupled to inverting or non-inverting input nodes may be directly programmed into the MDAC using switches, such that a thermometric to binary converter is not required in an example embodiment. Thus, the number of impedance elements coupled to the non-inverting reference input or inverting reference input REFM remains constant in each cycle such that there is no need to settle the non-inverting reference input or inverting reference input to full accuracy.

Abstract: An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: A method and apparatus for analog-to-digital conversion. An Analog-to-Digital Converter (ADC) includes M ADCj, j=1, 2, . . . , M. Each ADCj comprises a number of cells each of which comprises a first switch, a second switch, a current sink and an inverter. An inverter of a cell in an ADCj changes state in response to a current associate with an input signal of the ADCj exceeding a threshold, thus switching on the next cell. Each ADCj is enabled to perform analog-to-digital conversion on a residual current of a previous ADCj-1 after the previous ADCj-1 has completed its analog-to-digital conversion and has been disabled.

Abstract: In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.

Abstract: A reference circuit for use with a charge redistribution analog to digital converter, having a capacitor array, the reference circuit comprising: an input for receiving a signal; an output for supplying a reference voltage to at least one capacitor of the charge redistribution capacitor array; a storage capacitor for storing the reference voltage; a voltage modification circuit for comparing the reference voltage stored on the storage capacitor with the reference signal, and based on the comparison to supply a correction so as to reduce a difference between the reference voltage and the reference signal, the correction being applied during a correction phase; and a first switch for selectively connecting the storage capacitor to the input during an acquisition phase.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract: Systems and methods are provided for converting analog data to digital data that can include performing N successive analog subtractions from an initial data charge Qin. The analog subtractions are performed using an amplifier coupled to a discharge capacitor and a divider circuit coupled to an input of the amplifier. The divider circuit includes a first capacitor, a second capacitor, and a switch to alternately divide a remaining charge Q by 2N between the first and second capacitors until the remaining charge Qin at the amplifier is below a threshold value. A compensating circuit compensates for fluctuations in the charge held by the first and second capacitors due to operation of the switch.

Abstract: Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.

Abstract: A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

Abstract: Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract: An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference.

Abstract: Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is aaccumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Abstract: An analog-to-digital converting (ADC) apparatus is disclosed. The ADC apparatus includes a coarse comparing module, at least one pre-switching detection module, at least one fine comparing module, and an encoder. The coarse comparing module compares an input signal and a plurality of first reference signals to generate a previous comparing result and a coarse comparing result in sequence. The pre-switching detection module generates a plurality of previous selecting signals according to the received previous comparing result. The encoder generates a previous encoding result according to the coarse comparing result. The fine comparing module selects a selected reference signal to be compared with the input signal from a plurality of second reference signals according to the previous selecting signals and the previous encoding result, so as to generate a fine comparing result.

Abstract: An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

Abstract: Method consists in accumulation of electric charge in the sampling capacitor (Cn) by parallel connection of the sampling capacitor (Cn) to the source of converted voltage (UIN) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next trigger signal (Px+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent trigger signal (Px+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again.

Abstract: In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.

Abstract: Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

Abstract: In order to minimize noise and current consumption in a hearing aid, an input converter comprising a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract: A successive approximation register analog to digital converter (SAR ADC) and a method of linearity calibration therein are provided. Each composed element Ei in a part of the composed elements includes a main constructed element Ei0 and wi sub constructed element Ei1, Ei2, . . . , Eiwi. The SAR ADC selects a part of the sub constructed elements Ei1, Ei2, . . . , Eiwi and make them non-functional when a missing decision level is caused by the composed element Ei. An overlap cancellation to the obtained missing code numbers is performed, compensation coefficients are updated according to the missing code numbers after the overlap cancellation, and a compensation to the corresponding digital value is performed according to the compensation coefficients. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: An analog-to-digital converter comprises a switched capacitor array configured to receive an analog input signal, a comparator having inputs coupled to respective outputs of the switched capacitor array, register circuitry having inputs coupled to respective outputs of the comparator, and a metastability detector associated with the register circuitry. The register circuitry is configured to generate control signals for application to respective control inputs of the switched capacitor array and to provide a digital output signal corresponding to the analog input signal. The metastability detector is configured to detect a metastability condition relating to signals at the respective outputs of the comparator. The register circuitry responsive to detection of the metastability condition forces bits of the digital output signal to particular logic levels.

Abstract: The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (Cn-1, . . . , Co) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (Cn-1, . . . , Co) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1, . . .

Abstract: A successive approximation analog to digital converter and a conversion method thereof are provided. The successive approximation analog to digital converter includes a sample circuit, a conversion circuit, and a filtering control circuit. The sample circuit is configured to sample an analog voltage from an analog signal. The conversion circuit is configured to convert the analog voltage into a digital voltage. The filtering control circuit is configured to transmit a filtering control signal to the sample circuit according to the digital voltage. The sample circuit further samples a next analog voltage from the analog signal and adjusts the next analog voltage into an adjusted analog voltage according to the filtering control signal. The conversion circuit further converts the adjusted analog voltage into a next digital voltage, wherein the next digital voltage is a filtered digital voltage.

Abstract: A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.

Abstract: The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A server rack includes a main body, an electronic scale, and an alarm. The main body is used for receiving a number of servers. The electronic scale includes a pressure sensor and a microcontroller. The main body presses on the pressure sensor so that the pressure sensor can measure the pressure from the main body to obtain a pressure signal. The microcontroller analyzes the pressure signal to calculating the total weight of the main body and the servers. The alarm stores a predetermined weight threshold, which is the total weight of the main body and the maximum servers that the main body can bear. The alarm also compares the measured total weight with the predetermined weight threshold. When the measured total weight is larger than the predetermined weight threshold, the alarm alarms.

Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Abstract: A system and a method are disclosed for establishing the biasing point of a comparator in a successive approximation analog-to-digital converter (SAR ADC) by transferring an electric charge from a series of capacitors in a switched-capacitor array into a frame capacitor. The frame capacitor is formed by a parasitic capacitance between the series of capacitors and a conductive metal frame that surrounds the capacitors. To induce the charge transfer, the conductive metal frame is connected to a clock signal, which alternately drives the frame between a supply voltage and ground. By using the frame capacitor instead of a separate power source to establish the biasing point, the current consumption of the SAR ADC is reduced.

Abstract: An analogue to digital converter comprises a first input connection to receive a first part of the analogue input signal; a second input connection to receive a second part of the analogue input signal; a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors; wherein, during a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors, the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors, and a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of the digital output signal.

Abstract: For analog to digital conversion with correlated double sampling in an image sensor, a pixel signal from a given pixel is sampled to generate a respective sampled signal N-times, with N>1 within a horizontal scan time period. A ramp signal is generated with a respective ramping portion for each respective sampled signal. Each respective sampled signal is compared with a respective ramping portion to generate a respective comparison signal that determines a respective digital code. The N respective digital codes are summed to generate a final digital code with reduced random noise.

Abstract: An SAR ADC capable of reducing energy consumption, including a voltage selecting circuit for configuring a capacitor circuit to form a first equivalent capacitor having a capacitance of (2m?1)C, a second equivalent capacitor having a capacitance of (2n?2m?1)C, a fourth equivalent capacitor having a capacitance of (2m?1)C, and a fifth equivalent capacitor having a capacitance of (2n?2m?1)C, wherein, the first equivalent capacitor has one terminal coupled to a reference voltage or a ground voltage, and the other terminal coupled to a positive input end of a comparator; the second equivalent capacitor is coupled between a common mode voltage and the positive input end; the fourth equivalent capacitor has one terminal coupled to the ground voltage or the reference voltage, and the other terminal coupled to a negative input end of the comparator; and the fifth equivalent capacitor is coupled between the common mode voltage and the negative input end.

Abstract: In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.

Abstract: The present invention provides an integration and analog to digital conversion circuit sharing common capacitors. The circuit comprises a capacitor array module, an integration circuit, and an analog to digital conversion (ADC) logic. The capacitor array module has a plurality of capacitors. The integration circuit is configured to integrate an analog signal by the capacitor array module. The ADC logic is configured to convert the output of the capacitor array module to a digital signal.

Abstract: The present invention provides an integration and analog to digital conversion circuit sharing common capacitors. The circuit comprises a first capacitor array module, a second capacitor module, an integration circuit, an analog to digital conversion (ADC) logic. The first capacitor array module has a plurality of capacitors. The second capacitor array module has a plurality of capacitors. The integration circuit is configured to integrate an analog signal by said first or said second capacitor array module. The ADC logic is configured to convert the output of said first or said second capacitor array module to a digital signal. The ADC logic performs conversion by said first capacitor array module while said integration circuit performs integration by said second capacitor array module, and said ADC logic performs conversion by said second capacitor array module while said integration circuit performs integration by said first capacitor array module.

Abstract: The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuit arranged in array and a plurality of Stage 2 integration circuit arrange in array. Each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal. Each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal.

Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.

Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (?1) to a first input voltage (±Vm) and on a second clock signal (?2) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negative r

Abstract: The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract: A Direct Current (DC) charge comparator that provides low input offset by feeding complimentary plus and minus charge inputs to a single amplification path via an alternate input path switch. Multiple sample and hold circuits at the output of the amplification path permit comparison of the result when each of the charge inputs travels down each of the paths, to determine a correction.