Abstract: A data demodulator includes: a conversion means for converting an RLL code obtained by converting data in which information bits including specific bits are inserted at fixed intervals which is included in an input signal in accordance with a modulation table having variable-length conversion rules into data in accordance with a demodulation table corresponding to the modulation table; a determination means for determining control segments for performing calculation intended by the information bits from the converted data; a calculation means for executing calculation intended by the specific bit inserted in the control segment different from a calculation target with respect to the data of the control segment as the calculation target; and a correction output means for selecting one of first data converted by the conversion means and second data obtained by converting the RLL code of the input signal corrected based on the calculation result in accordance with the demodulation table and outputting the data.

Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

Abstract: According to one embodiment, a run length limiter includes a searcher configured to search a received digital data for a specific symbol, an operator configured to operate an exclusive OR operation of the specific symbol and the digital data, and an output module configured to output the exclusive OR operated digital data with the specific symbol.

Abstract: Transform coefficients of sample blocks of a macroblock of a video picture are encoded by adaptively encoding a combination, the number of non-zero coefficients before the trailing one coefficients and the number of trailing one coefficients. The transform coefficients may be further encoded by adaptively encoding one or more of the signs of the trailing one coefficients, the level measures of the interposed in the non-zero coefficients. Adaptive encoding of the number and trailing one coefficients may be performed in view of one or more neighboring sample blocks, whereas adaptive encoding of level measure may be performed in view of quantization parameters of a macroblock and previously encoded level measures. Decoding may be performed in an inverse manner.

Abstract: A network device is disclosed. The network device includes a port to allow the device to communicate on a full bandwidth channel, a main processor to control reception and transmission of data and a compressor. The compressor identifies repeated fixed sequences in the data, and replaces repeated fixed sequences with an identifier sequence, a count of repetitions and the fixed sequence. The network device may have a decompressor instead of, or in addition to, the compressor that can decompress received data that is compressed.

Abstract: Disclosed is an apparatus in which there are provided a first storage unit for storing signals to which indexes are given in order to distinguish each of a plurality of signals that are to be coded; a first index computing unit for computing first indexes of non-zero signals among the signals stored in the first storage unit; a second index computing unit for computing second indexes from a base index and the first indexes; a second index storage position search unit for searching for a storage position in a second storage unit in which the second indexes are to be stored based on values of the indexes stored in the second storage unit; a second index preserving unit for preserving the second index in the second storage unit based on a storage position searched for by the second index storage position search unit; and a control unit for giving the base index to the second index computing unit and for controlling operation of the first index computing unit, the second index computing unit the second index stor

Abstract: To reduce the complexity of the encoding/decoding of pulse positions and/or pulse magnitudes associated with complex combinatorial computations, a method and structure for encoding and decoding of pulse position and/or pulse magnitudes requires fewer computations of these combinatorial functions. Adaptive switching between coding or encoding is performed in accordance with the estimated density of the plurality of occupied positions.

Abstract: A system for compressing digital data by representing a portion of it predictionally and transformationally as a block of transform coefficients, then quantizing that block selectively into a set of encoding symbols based on an indication whether the transform coefficients represent the portion as having a particular characteristic, and then by encoding the set of encoding symbols into a data bit stream. In particular, frequency may be used as the characteristic of the digital data in many applications.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo-random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo-random data streams. An encoder RLL-modulates the plurality of types of pseudo-random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A communications channel includes a buffer configured to store data. The data includes a plurality of symbols. A data dependent scrambler is configured to select a non-zero symbol and compare the non-zero symbol to each of the plurality of symbols stored in the buffer. In response to the non-zero symbol being different than each of the plurality of symbols stored in the buffer, the data dependent scrambler is further configured to generate a scrambling sequence to be used in scrambling the data, and the non-zero symbol is a seed of the scrambling sequence.

Abstract: Systems and methods are provided for encoding and decoding constrained codewords using an enumerative coding graph. The constrained codewords may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has multiple branches that lead to other states. Each state in the enumerative coding graph is associated with at least two bits of an enumerative codeword. Configuring the structure of the graph and cardinalities associated with each state allows the encoder to generate a code that conforms to defined constraints.

Abstract: A coder is fed with pre-coded data such that the absolute value of the RDS of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words the RDS of the first code word is compensated by the RDS of the second conde word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS. This principle can easily be applied to the 17PP coder.

Abstract: A method for modulating a video input signal received into a modulation circuit is disclosed. A first step of the method generally comprises (A) during a first modulation pass, generating (i) a primary frame by inserting a plurality of primary synchronization codes into the video input signal, (ii) a secondary frame by inserting a plurality of secondary synchronization codes into the video input signal, (iii) a plurality of first values and a first digital sum value both for the primary frame and (iv) a plurality of second values and a second digital sum value both for the secondary frame. A second step of the method generally comprises (B) during a second modulation pass, generating a video output signal presented from the modulation circuit by modulating the video input signal using one set of (i) the first values and (ii) the second values as determined by the first digital sum value relative to the second digital sum value.

Abstract: A method, apparatus and system employing a 17 B/20 B coder is disclosed. The 17 B/20 B coder to receive an incoming stream including a 17 B block and a 20 B block, and partition the 17 B block into first blocks, and partitioning the 20 B into second blocks. The coder is further to code 17 B to 20 B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17 B block and the second blocks of the 20 B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

Abstract: A block encode circuit (800) including a scanner (820) operable to scan a block having data values spaced apart in the block by run-lengths to produce a succession of pairs of values of Level and Run representing each data value and run-length, and wherein the Level values include one or more AC values succeeded by a DC value in the succession, and a Run-Level encoder (830) responsive to said scanner (820) to encode the values of Level and Run in a same AC to DC order as in the succession of pairs of values from said scanner (820) to deliver an encoded output. Other encoders, decoders, codecs and systems and processes for their operation and manufacture are disclosed.

Abstract: Converting a mask constraint into a bitset constraint. For example, a method of converting a mask constraint into a bitset constraint may include determining an intermediate bitset based on a variable-bit component of the mask constraint; and generating the bitset constraint based on the intermediate bitset and on a fixed-bit component of the mask constraint. Other embodiments are described and claimed.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.

Abstract: A seed generator for a scrambler comprises a seed set identifier that identifies a seed set based on received user data symbols, which include a plurality of M-bit symbols. A seed selector selects a scrambling seed for the scrambler from the seed set based on Hamming distances between at least two of the M-bit symbols in the seed set.

Abstract: A method and system are provided to minimize the size and complexity of bitstreams associated with encoded data by using a new compression scheme. An entropy encoder receives a list of run/data value pairs and entropy encodes separately the runs and data values, selecting their codewords according to length and magnitude, respectively, and catenates the resulting codeword pairs—run codeword first—in an encoded bitstream.

Abstract: According to one embodiment, a run length limiting apparatus comprises an input section configured to input, a digital data string including a predetermined number of symbols which have the same number of bits, a search section configured to search for a specific symbol having a pattern that does not match any of the symbols included in the input digital data string, a calculation section configured to perform an exclusive OR operation between the specific symbol searched for and each of the symbols included in the input digital data string, and an output section configured to output the calculated digital data string together with the specific symbol.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: A coder converts M-bit information words into N-bit code words by generating a first and a second provisional code sequence using a coding rule by which, code words are logically assigned to information words so that a two's complement of a sum of coding bits included in the first provisional code sequence, is always different from a two's complement of a sum of coding bib included in the second provisional code sequence, when a first code state of the first sequence encoded starting from a predetermined original state is identical to a second code state of the second sequence encoded starting from said predetermined original state. Then, selecting either the first sequence or the second sequence depending on a value of at least one parameter that correlates with a DC content of the coded bit stream.

Abstract: Methods and apparatus are provided for partitioning a stream of binary input data into two binary output streams for supply to respective modulation encoders in a modulation coding system. A 4-ary enumerative encoding algorithm is applied to each of a succession of input words in the input bit-stream to produce a succession of 4-ary output symbols from the input word. The 4-ary algorithm simultaneously encodes respective j=? Fibonacci codes in the odd and even interleaves of the input word such that the two bit-sequences formed by respective corresponding bits of the succession of output symbols are range-limited codewords. The two binary output streams are then produced by separating the two range-limited codewords generated from each successive input word. The binary output streams can then be independently encoded by respective modulation encoders, and the encoder outputs interleaved to produce a modulation-constrained output stream. Corresponding decoding systems are also provided.

Abstract: A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

Abstract: For controlling the DC-content of a Run Length Limited RLL modulated channel bit stream organized in data blocks, control bits are periodically inserted into control blocks which are dynamically placed and sized near the data block boundaries in such a way as to enable independent dk-encoding of the data blocks body and the control blocks. Running digital sum differences are calculated. Control bit insertion is done in such a way that the d,k constraints of the RLL code are not violated, that the encoded dk sequence of the data block body is not altered, and that the running digital sum is minimized by eventually inverting the contribution of the data block body thereto. Compared to the number of data bits per data block, few control bits are sufficient to keep the digital sum variation DSV of the Running Digital Sum RDS small.

Abstract: In a channel encoder comprising a dk-encoder stage and a precoding stage, obeyance of a repeated minimum transition runlength constraint is achieved because, between the dk-encoder and the precoder, data are passed through an RMTR encoder which replaces occurrences of a forbidden pattern by a current replacement pattern having the same length as the forbidden pattern. By appropriately selecting current replacement patterns from a predefined set of two different replacement patterns, DC-control can be achieved for the encoder output. The corresponding decoder is described, which also employs pattern replacement. These results are provided by a method of channel encoding binary data, wherein the data is contained in a n input sequence of data tuples. An input sequence of constrained tuples is generated that obeys the relationships heretorfore set forth. A post encoding step is applied with NRZI modulation to be used in a channel as described.

Abstract: The invention is related to a method and a device for encoding of a bit sequence. Said method comprises generating, for each run of Ones comprised in the bit sequence, a unary representation of length of the respective run of Ones, generating a first sequence by concatenating the generated unary representations of lengths of runs of Ones, generating, for each run of Zeroes comprised in the bit sequence, a unary representation of the length of the respective run of Zeroes, generating a second sequence by concatenating the generated unary representations of lengths of runs of Zeroes, and bit plane encoding the generated first and second sequence of unary representations. In most cases, overall entropy of bit planes of unary representations of run lengths is smaller than entropy of the bit sequence. Thus, more compact encoding can be achieved.

Abstract: According to the present disclosure, a transmitter for transmitting control characters to a display device over an interface includes a transmitter portion configured to transmit a control character having a plurality of bit values to the display device. The transmitter also includes logic configured to determine values of the bits in the control character and construct a corresponding plurality of rebalancing control characters based on the determination of the values of the plurality of bits in the control character to have bit values selected such that the combination of the control character and rebalancing control character is DC balanced. As such, the transmitter provides DC balance correction to non-DC balanced control characters in such a way as to allow DVI and HDMI to operate properly on an AC-coupled connection.

Abstract: Systems and methods for encoding and decoding data utilize selective substitution of a conversion table for converting data having a basic data length of m bits into a variable length code (d, k; m, n) having a minimum run of d (d>0), a maximum run length of k and a basic codeword length of n bits, wherein the systems and methods use a basic conversion table and a substitute conversion table for converting the data. The selective substitution of the conversion table in a preferred exemplary embodiment is based on control information of a data string and/or a variable length code string.

Abstract: It is an object of the present invention to provide coding techniques which allow for higher efficiency and easier synchronization with coded data. In order to attain the object, a coding device according to the present invention converts 2-bit informational data into 4-bit coded data according to a predetermined coding rule. According to the coding rule employed in the coding device, one of four possible kinds of bit strings of informational data is converted into alternately a bit string of four bits in which each of values of two successive bits is “1” and a bit string of four bits in which each of values of all bits is “0”. Then, the other kinds of bit strings are converted into bit strings of four bits which differ from one another, in each of which a value of only one bit is “1”.

Abstract: An encoding scheme generates an encoded nine bit code word from each input eight bit data word. The coding scheme is such that the encoded data words have advantageous properties, such as a minimum of two polarity transitions in each encoded data word, and a maximum of five bits without a polarity transition. Five of the bits from the input eight bit data word appear unchanged in the encoded data word, while the other four bits of the encoded data word are obtained by applying appropriate logical operators to the remaining three bits of the input data word in combination with two of the five bits that appear unchanged in the encoded data word. Exception codes can also be defined, that is, nine bit code words that cannot be obtained from any eight bit data word by means of the coding scheme, and can be used to embed control information into the data stream. For example, the exception codes may advantageously have six or seven bits without a polarity transition.

Abstract: According to one embodiment, a run length limiter includes a searcher configured to search a received digital data for a specific symbol, an operator configured to operate an exclusive OR operation of the specific symbol and the digital data, and an output module configured to output the exclusive OR operated digital data with the specific symbol.

Abstract: Entropy coding and decoding techniques are described, which may be implemented separately or in combination. For example, a video encoder uses two-layer run level coding to reduce bitrate for frequency transform coefficients in a quick and efficient manner, and a video decoder uses corresponding two-layer run level decoding. This two-layer coding/decoding can be generalized to more than two layers of run level coding/decoding. The video encoder and decoder exploit common patterns in run level information to reduce code table size and create opportunities for early termination of decoding. Using zoned Huffman code tables helps limit overall table size while still providing a level of adaptivity in encoding and decoding. Using embedded Huffman code tables allows the encoder and decoder to reuse codes for 8×8, 8×4, 4×8, and 4×4 blocks.

Abstract: Methods and apparatus are provided for modulation coding of input data. In a first scheme, a modulation encoder applies a modulation code to input data to produce an (L,K)-constrained encoded bit-sequence, where K is maximum run-length of 0's, and L is the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence. Then, a precoder effects 1/(1?D4) preceding of the encoded bit-sequence. In a second scheme, a modulation encoder applies a modulation code to the input data to produce a K-constrained encoded bit-sequence. In this scheme, a precoder then effects 1/(1?D?D2?D3) preceding of the encoded bit-sequence. In both schemes, the effect of the precoder is to produce a precoded sequence in which, in addition to other constraints, the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value CVFO.

Abstract: A method and system are provided to minimize the size and complexity of bitstreams associated with encoded data by using a new compression scheme. An entropy encoder receives a list of run/data value pairs and entropy encodes separately the runs and data values, selecting their codewords according to length and magnitude, respectively, and catenates the resulting codeword pairs—run codeword first—in an encoded bitstream.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients which are obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table that is selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table that is selected according to the number of already-processed run values.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N?2k?2+k?1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k?1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

Abstract: A phase locking apparatus is disclosed which, includes a phase error information detecting device to detect phase error information indicating the phase error. The device has a phase position determining device to determine, based on run length limited information, whether or not phase positions of a first and second value from among sampling values constituting synchronous data are under a reverse phase condition in effect when only one of the first and the second values is in excess of a predetermined threshold, and a phase error information calculating device to calculate the phase error information in each of two cases determined, one with the reverse phase condition found to be in effect and the other without effect.

Abstract: A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

Abstract: A method and apparatus for compressing data is described. In one embodiment, a processor receives one or more strings of data to be compressed. Duplicate strings are replaced with pointers using a first compression algorithm. An output of the first compression algorithm is processed with a second compression algorithm using a variable context dynamic encoder to generate a tree of non-overlapping bit-sequences where the length of each sequence is being inversely proportional of the likelihood of that symbol needing to be encoded. Unused symbols are not generated on the tree.

Abstract: In accordance with one or more embodiments data may be encoded into a code word that meets run length constraints and has a reduced running digital sum by encoding (N?y)?1 data bits and y flag bits into m first n-bit patterns that form a first N-bit code word, producing a second N-bit code word by encoding the (N?y)?1 data bits and the y flag bits into m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, and selecting the code word that satisfies selection criteria. The selection criteria may, for example, be the word with the fewest transitions, the word with the smallest running digital sum, and so forth.

Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m?n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

Abstract: A method of generating a code that minimizes error propagation by selecting integers m, n, mrl, and a range of fractions od, where m represents the number of bits in an unencoded sequence, where n represents the number of bits in an encoded sequence, where mrl represents the maximum run length of an encoded sequence, and where od represents a range of ones densities of an encoded sequence. Next, generating an encoding map M that maps each unencoded sequence to an n-bit encoded sequence that satisfies od and mrl. Next, generating a decoding map N that maps each n-bit sequence to an m-bit sequence. Next, determining an error-propagation score for M and N. Then, returning to the step of generating M if a user requires a lower error-propagation score.

Abstract: An encoder includes a mapping module that receives input words including first input words and second input words. The mapping module maps the first input words to first output words that are run-length limited and have a digital sum that is equal to zero. The mapping module maps the second input words to second output words that are run-length limited and have one of a positive and a negative digital sum. An inverter module selectively inverts the second output words based on a cumulative digital sum of the second output words.

Abstract: A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit (“RLL”) constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Abstract: Systems and methods are provided for encoding and decoding constrained codes using an enumerative coding graph. The constrained code may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has two branches that lead to other states. Each state in the enumerative coding graph is assigned a cardinality. Configuring the structure of the graph and the cardinalities associated with each state allow the encoder to generate a code that conforms to defined constraints.