Abstract: A block code error correcting system is used in a compact disk reading system to increase the decoding capability of the compact disk reading system. The system includes a data slicer, a data bit to channel bit modulation pulse width determinator, a demodulator, an erase address detector and an error correction code (ECC) decoder. A pulse width of an eight-to-sixteen modulation (EFM+) signal is detected to thereby produce an erase control signal when the pulse width of the EFM+ signal is in a predefined window or is an illegal pulse width. A codeword corresponding to the EFM+ signal is set as an erasure, and accordingly an erase address is produced.

Abstract: Disclosed is an apparatus in which there are provided a first storage unit for storing signals to which indexes are given in order to distinguish each of a plurality of signals that are to be coded; a first index computing unit for computing first indexes of non-zero signals among the signals stored in the first storage unit; a second index computing unit for computing second indexes from a base index and the first indexes; a second index storage position search unit for searching for a storage position in a second storage unit in which the second indexes are to be stored based on values of the indexes stored in the second storage unit; a second index preserving unit for preserving the second index in the second storage unit based on a storage position searched for by the second index storage position search unit; and a control unit for giving the base index to the second index computing unit and for controlling operation of the first index computing unit, the second index computing unit the second index stor

Abstract: The described embodiments provide a system that encodes a sequence of integers using a variable-length compression technique. During operation, the system scans the sequence of integers and observes the sizes of the integers to determine a threshold value, K, from the observed sizes. For a given integer of length N bits, if N?K is greater than zero, the system generates a tag for the encoded integer comprising a sequence of N?K zeros followed by a one, and generates a set of remaining bits for the encoded integer as a sequence of the N?1 least-significant bits which make up the integer. Otherwise, the system generates a tag for the encoded integer as a single one, and generates a set of remaining bits for the encoded integer by padding the N bits which make up the integer with zeros so that the set of remaining bits is K bits in length.

Abstract: A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling system. Such a method comprises determining a coding gain for each of a plurality of transition-limiting codes, and selecting one of the plurality of transition-limiting codes having a largest coding gain for use in the multi-level signaling system.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.

Abstract: A method of encoding data comprises the steps of dividing the data into sets of data, transforming each set of data into a set of transform coefficients (A, B, C), assigning each transform coefficient to a single sub-set (S0, S1, . . . ) of the respective set of transform coefficients in dependence of its magnitude, and encoding each sub-set separately. The method may include the step of comparing the magnitudes of the transform coefficients of each set with at least one threshold value (T1, T2, . . . ). As each sub-set contains the entire magnitude of selected transform coefficients, the loss of another sub-set during transmission has no effect on these transform coefficients. The method is particularly suitable for encoding picture data.

Abstract: A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N?1 coding bits indicating whether corresponding ones of N?1 of the N portions of the data block include one of all ones and all zeros, where N is an integer greater than two. A mapping module generates an RLL codeword including N portions comprising bits that are determined by a first mapping table, a second mapping table, bits of the data block and the N?1 coding bits.

Abstract: In accordance with one or more embodiments data may be encoded into a code word that meets run length constraints and has a reduced running digital sum by encoding (N-y)?1 data bits and y flag bits into m first n-bit patterns that form a first N-bit code word, producing a second N-bit code word by encoding the (N-y)?1 data bits and the y flag bits into m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, and selecting the code word that satisfies selection criteria. The selection criteria may, for example, be the word with the fewest transitions, the word with the smallest running digital sum, and so forth.

Abstract: A system that encodes a sequence of integers using a variable-length compression technique is described. During operation, the system scans the sequence of integers and observes the sizes of the integers to determine a threshold value K from the observed sizes. For a given integer which is N bits in length, if N?K is greater than or equal to zero, the system generates a tag for the encoded integer which comprises a sequence of N?K zeros followed by a one, and generates a set of remaining bits for the encoded integer as a sequence of the N bits which make up the integer. Otherwise, if N?K is less than zero, the system generates a tag for the encoded integer as a single one, and generates a set of remaining bits for the encoded integer by padding the N bits which make up the integer with zeros so that the set of remaining bits is K bits in length.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A record reproduction apparatus includes an encoding unit that encodes sector data to be written into a recording medium, by dividing the data into a predetermined number of blocks, and an iterative decoding unit that iteratively decodes the sector data read from the recording medium, by dividing the sector data into the predetermined number of blocks.

Abstract: A method and system of lossless adaptive Golomb/Rice (G/R) encoding of integer data using a novel backward-adaptive technique having novel adaptation rules. The adaptive G/R encoder and decoder (codec) and method uses adaptation rules that adjust the G/R parameter after each codeword is generated. These adaptation rules include defining an adaptation value and adjusting the G/R parameter based on the adaptation value. If the adaptation value equals zero, then the G/R parameter is decreased by an integer constant. If the adaptation value equals one, then the G/R parameter is left unchanged. If the adaptation value is greater than one, then the G/R parameter is increased by the adaptation value. In addition, the adaptive G/R encoder and method include fractional adaptation, which defines a scaled G/R parameter in terms of the G/R parameter and updates and adapts the scaled G/R parameter to slow down the rate of adaptation.

Abstract: A method of controlling a Digital Sum Value (DSV), including generating a plurality of DSV control bit patterns indicating predetermined information represented by at least one bit; and inserting any one of the generated DSV control bit patterns at a predetermined location of a modulated codeword. The plurality of the DSV control bit patterns indicate predetermined information represented by at least one bit so that the DSV control bit patterns control the DSV and can be used as predetermined information, instead of being discarded after the demodulation is completed.

Abstract: A method of designing a look-up table of a finite-state encoder, applied to a finite-state encoder, comprises steps of: determining a bit length of a legal output codeword derived from the finite-state encoder and a restrict condition; collecting a plurality of legal output codeword satisfied the restrict condition; determining a bit length of an input codeword derived to the finite-state encoder according to the amount of the plurality of the legal output codeword; determining the amount of states in the finite-state encoder according to the bit length of the input codeword and the bit length of the legal output codeword; dividing the plurality of legal output codeword to a plurality of subset according to the amount of the states in the finite-state encoder and a specific mathematic equation; determining the amount of the legal output codewords in the plurality of subset; and, completing the look-up table through determining a relationship among a present state, a previous state, and a corresponding subset,

Abstract: Computer graphics data coding apparatus includes unit configured to acquire computer graphics data items, unit configured to pre-process acquired computer graphics data items, controlling/coding unit configured to subject pre-processed computer graphics data items to process for controlling number of codes to be finally output, to generate codes, accumulation unit configured to accumulate parts to be subjected to entropy coding, which are contained in generated codes, calculation unit configured to calculate entropy information based on accumulated parts, and generate code words based on entropy information, entropy information indicating amount of entropy, entropy coding unit configured to subject generated codes to entropy coding based on generated code words, to generate entropy codes, extraction unit configured to extract, from entropy information, minimum information for decoding, extracted-information coding unit configured to code minimum information in order to reduce amount of minimum information, an

Abstract: A method and an apparatus for encoding and decoding a modulation code are provided. The method includes: adding an error detection bit(s) to source information; performing k-constraint coding by inserting an error pattern that can be detected using an error detection code into a data stream that violates a k-constraint for a run length limited (RLL) code in a data stream comprising the error detection bit(s) and the source information, and recording the data stream after being k-constraint coded onto a recording medium; and reading the data stream recorded onto the recording medium and determining whether an error is present in the data stream.

Abstract: This invention provides an encoding apparatus including a group generating unit that puts plural information values to be compressed together and generates a group of information values to be compressed; a code assignment unit that assigns a code to each group generated by the group generating unit; and an information encoding unit that encodes the information values to be compressed belonging to each group, using the code assigned to each group.

Abstract: Methods and apparatus are provided for modulation coding of input data. In a first scheme, a modulation encoder applies a modulation code to input data to produce an (L,K)-constrained encoded bit-sequence, where K is maximum run-length of 0's, and L is the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence. Then, a precoder effects 1/(1?D4) preceding of the encoded bit-sequence. In a second scheme, a modulation encoder applies a modulation code to the input data to produce a K-constrained encoded bit-sequence. In this scheme, a precoder then effects 1/(1?D?D2?D3) preceding of the encoded bit-sequence. In both schemes, the effect of the precoder is to produce a precoded sequence in which, in addition to other constraints, the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value CVFO.

Abstract: There is provided an apparatus which obtains a circumstance where LDPC codes are interleaved without damaging modulation rules and thereby a correction ability of LDPC encoding and decoding method is fully exhibited. The apparatus includes an RLL rule applying section which modulates user data by applying an RLL rule to the user data and thereby obtains RLL encoded sequence data, an interleave section which interleaves the RLL encoded sequence data and thereby obtains interleaved sequence data, an LDPC parity generating section which subjects the interleaved sequence data to LDPC encoding processing and thereby obtains LDPC parity sequence data, an inserting section which inserts parity of the LDPC parity sequence data in the RLL encoded sequence data in a distribution manner and thereby obtains output data, and an output section which records or transmits the output data.

Abstract: The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method divides a data word, which a sync signal is to be added in front or rear of when it is written in a recording medium, into two or more word segments, generates for each word segment a number of intermediate sequences by combining mutually different digital words with that word segment, scrambles these intermediate sequences to form alternative sequences, translates each alternative sequence into a (d,k) constrained sequence, checks how many undesired sub-sequences are contained in each (d,k) constrained sequence, and selects one (d,k) constrained sequence for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences not having the undesired sub-sequence. Applying this method to a modulating device, DSV control can be conducted by much simpler hardware.

Abstract: Methods and systems for generating 10-bit control codes for use in 8-bit to 10-bit encoding are disclosed. Such control codes can have low subblock disparity (where subblocks include 6-bit and 4-bit blocks), limited run lengths when concatenated, limited run lengths within sub-blocks, meet minimal allowable cumulative disparity values at predetermined bit locations (not violate a transition matrix), and not form an aliased comma character sequence within a code, or when codes are concatenated with other codes or encoded data values. Preferably, new codes are added to existing 8B10B schemes with less than sixteen control codes to arrive at a control code set of at least sixteen.

Abstract: It is an object of the present invention to provide an encoding device and an encoding method that allow even faster speeds to be achieved by reducing the waiting time during which variable-length encoding is performed. An encoding device performing run-length encoding and variable-length encoding sequentially inputs one block of m×n data, determines whether a value of each unit of input data is 0 (zero), stores the results of the determination to an information register and stores input data to a data buffer, controls the reading of data from the data buffer based on the results of the determination, performs run-length encoding using the data read from the data buffer and the results of the determination, and performs variable-length encoding using as a data pair the data and the number of consecutive data having a value of 0 (zero).

Abstract: A method and systems are provided for efficiently implementing content adaptive variable length coding on a modern processor. Some embodiments comprise encoding a non-zero coefficient in an array of coefficients in an iteration of an encoding loop. The code value of the encoded non-zero coefficient is determined, at least in part, by the magnitude of another non-zero coefficient in the array of coefficients. A run of zero coefficients preceding a non-zero coefficient in the array of coefficients is also encoded in the iteration of the encoding loop. The encoded non-zero coefficient is appended to an encoded video bitstream when encoded. The encoded run of zero coefficients is stored in a storage device and appended to the encoded video bitstream after all non-zero coefficients in the array of coefficients have been encoded.

Abstract: A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.

Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m?n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

Abstract: A demodulation table for converting variable length code (d, k; m, n; r) is provided. The variable length code has a maximum constraint length r>1, has a minimum run of d (d>0), has a maximum run of k, and a basic codeword length of n bits into data having a basic data length of m bits. The demodulation table includes: a basic table for converting code patterns composed of basic codes having a basic codeword length of n bits into data patterns composed of basic data having a basic data length of m bits; and a substitution table for converting code patterns of a plurality of different minimum run successive occurrence limiting patterns determined so as to limit successive occurrences of the minimum run to a maximum of N (N>1) times into a corresponding identical data pattern.

Abstract: Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t.

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.

Abstract: A data processing apparatus for processing a plurality of input signals to increase the number of bits thereof to disperse 0s and 1s therein and then converting the input signals into a serial signal. A signal generating unit generates including signal generating means for generating the serial signal having a second bit rate which is represented by the product of a first bit rate of the input signals, the number of the input signals, and a ratio of a bit length after the number of bits is increased to a bit length before the number of bits is increased.

Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2k evaluation values and outputting the maximum value as an evaluation result.

Abstract: The field of the invention is that of serial digital data transmissions. Such digital data is, in particular, of video type. In certain types of transmission, the links used cannot pass direct current. Such is the case in particular with the so-called “AC-coupled” links used in aeronautics for transferring video signals between computers. In this case, it becomes essential to transmit binary words comprising, if possible, similar quantities of zeroes and ones. The subject of the invention is an encoder or a decoder of 9-bit binary words into 10-bit binary words, said 10-bit binary words being designed to be transmitted over links that cannot pass direct current, said binary words comprising between four ones and six ones regardless of the initial 9-bit binary word.

Abstract: The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N?2k?2+k?1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k?1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

Abstract: This invention relates to a method of converting a user bitstream into a coded bitstream by means of a runlengh limited (d, k) channel code where the channel code has a constraint of d=1. In order to ensure an improvement in bit detection performance an additional RMTR constraint of r=2 is imposed limiting to two the maximum number of minimum runs allowed by the d=1 constraint. An additional advantage of such a code is a limitation of the back-tracking depth of a Viterbi bit-detector Based on two different k constraints the construction of such d=1 and r=2 codes is disclosed.

Abstract: Techniques and tools for escape mode code resizing are described. For example, a video decoder receives encoded information (e.g., runs, levels) for transform coefficients of blocks. For at least some of the encoded information, the decoder decodes in an escape mode for which codes have sizes signaled on a sub-frame basis (e.g., on a per-interlaced field basis in a video frame, or on a per-slice basis in a video frame). A video encoder performs corresponding encoding and signaling.

Abstract: A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m?n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) preceding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

Abstract: For controlling the DC-content of a Run Length Limited RLL modulated channel bit stream organized in data blocks, control bits are periodically inserted into control blocks which are dynamically placed and sized near the data block boundaries in such a way as to enable independent dk-encoding of the data blocks body and the control blocks. Running digital sum differences are calculated. Control bit insertion is done in such a way that the d,k constraints of the RLL code are not violated, that the encoded dk sequence of the data block body is not altered, and that the running digital sum is minimized by eventually inverting the contribution of the data block body thereto. Compared to the number of data bits per data block, few control bits are sufficient to keep the digital sum variation DSV of the Running Digital Sum RDS small.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo-random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo-random data streams. An encoder RLL-modulates the plurality of types of pseudo-random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: In a channel encoder comprising a dk-encoder stage and a precoding stage, obeyance of a repeated minimum transition runlength constraint is achieved because, between the dk-encoder and the precoder, data are passed through an RMTR encoder which replaces occurrences of a forbidden pattern by a current replacement pattern having the same length as the forbidden pattern. By appropriately selecting current replacement patterns from a predefined set of two different replacement patterns, DC-control can be achieved for the encoder output. The corresponding decoder is described, which also employs pattern replacement.

Abstract: A system and method for decompression optimization employing a data input and a dedicated back buffer and data parser. The system and method also relate to accelerating the parsing process during decompression of a block of data by taking advantage of those naturally occurring redundancies within the block of data identified at compression time. The system of the invention includes a parser and an annotated back buffer which operate collectively to optimize the parsing process during decompression.

Abstract: A run-length limited (RLL) encoder includes a problematic-block detection module that receives a data block and that generates coding bits that indicate whether at least one of N portions of the data block include one of all ones and all zeros, where N is an integer greater than one. A mapping module generates an RLL codeword based on the data block and the coding bits. The RLL codeword includes N portions. One of the N portions of the RLL codeword is populated with the coding bits. At least another one of the remaining portions of the RLL codeword is populated with at least part of the data from one of the N portions of the data block that corresponds with the one of the N portions of the RLL codeword.

Abstract: A method and an encoder (1001) are disclosed for encoding an input bitstream derived from a block of coefficients relating to video data. Leading zeros and tailing zeros are determined and removed (4050, 4070) from the input bitstream. Parity bits are generated (60) for bits remaining in the input bitstream. An encoded bitstream (1032) is then generated, where the encoded bitstream (1032) comprises the number of leading zeros, the number of tailing zeros, and the parity bits.

Abstract: Method and apparatus are provided for encoding and decoding rate-(s(K+1)/s(K+1)+1) TCMTR(j,k,t,a) codes, where s is the ECC symbol size in bits and K is the number of unencoded symbols that are interleaved with an (s+1)-bit encoded block at the output of a rate-s/(s+1) encoder that encodes the r-th s-bit symbol. K=m/s?1 where m=s(K+1) is the total number of bits to be encoded. Error propagation is reduced, thus allowing the ECC code to correct errors efficiently. Header error-rate is also reduced by eliminating occurrence of likely error events at the detector output. Although initially an RLL code may be designed for an ECC symbol size of s bits, the RLL encoding of the present invention may be used in conjunction with ECC schemes that utilize symbol sizes other than s bits.

Abstract: The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N?2k?2+k?1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k?1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

Abstract: A method of generating codewords that conform to a run length limited (RLL) constraint represented by (d, k, a, b), where d is a minimum run length of a codeword, k is a maximum run length of the codeword, a is a length of source data, and b is a length of the codeword. The method includes generating codewords conforming to the RLL(d, k) constraint, and removing codewords in which a relatively long T and a relatively short T are placed adjacent to each other from the generated codewords.

Abstract: A data converter (1) capable of reducing a size of the total implementation in a device is a processing apparatus that performs secret converting processing predetermined to input data with 64 bits, the data converter including a finite field polynomial cubing unit (10), data integrating units (11a) to (11d), (12) and (13), a first converter (14), a second converter (15), a data splitting unit (16), and a data integrating unit (17). The finite field polynomial cubing unit (10) performs cubing, on the 32 bits data, in the polynomial residue class ring with a value in the finite field GF (28) as a coefficient and respectively outputs data with 32 bits.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.