Abstract: The present disclosure provides systems and methods for performing adaptive resolution change during video encoding and decoding. The methods include: comparing resolutions of a target picture and a first reference picture; in response to the target picture and the first reference picture having different resolutions, resampling the first reference picture to generate a second reference picture; and encoding or decoding the target picture using the second reference picture.

Abstract: A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

Abstract: Systems, apparatuses, methods and computer processes to separate and select frequency components of a signal in real time without phase delay by predicting or forecasting future values of the signal and using that forecast and past measurements in a noncausal zero-phase filtering algorithm are provided. The method of separating and selecting frequency components of a signal in real time without phase delay using a zero-phase filter, comprises obtaining past measurements of the signal; obtaining predicted values of the signal; and using the predicted values of the signal and the past measurements of the signal as components of an input signal in a noncausal zero-phase filtering algorithm for a zero-phase filter, the zero-phase filter producing an output signal.

Abstract: A method for parallel processing of a data stream is provided. In the method, a data stream that includes a plurality of segments is received. A split operation is performed on the data stream based on a split buffer to split the plurality of segments into N sub-streams. Each of the N sub-streams includes one or more segments of the plurality of segments, the N being a positive integer. The split buffer includes an input indexed first in first out (iFIFO) buffer, the input iFIFO buffer being configured to receive the plurality of segments of the data stream and output the plurality of segments to N sub-input iFIFO buffers to generate the N sub-streams. N sub-processing tasks are performed on the N sub-streams to generate N processed sub-streams.

Abstract: Communication buses enable devices to communicate and exchange information and control signals. There is a growing concern over the security of such types of buses. Since any device can transmit any message, and device on the bus which can be compromised poses a threat for the bus. Described is a system to authenticate the source of messages from various devices on a communication bus.

Abstract: A system and method for multi-rate synchronization of a digital sensor that provides a digital sensor output signal and a processor arrangement that processes the digital sensor output signal according to a processing algorithm and that provides a processor output signal, including operating the digital sensor to provide the digital sensor output signal with a first sample rate, and operating the processor arrangement to provide a processor output signal with a second sample rate. The second sample rate is an integer multiple of the first sample rate.

Abstract: A signal conversion from an input signal to an output signal where the filter used is factorized so that the conversion comprises determining 1) only a first factor at each sampling time of the input signal, where this first factor is independent on the sampling times of the output signal, and 2) only a second factor at each sampling time of the output signal, where this second factor is independent of the sampling times of the input signal. This reduces the computational load for this conversion. In addition, for most filters, the factors may be calculated recursively further increasing the computational load and also reducing the storage requirements. This allows for instantaneous changes in the sampling rates or non-uniform sampling rates with low computational requirements and low memory usage.

Abstract: A method and apparatus are described for aligning cross-faded audio signals using beats. In an embodiment, a controller includes a cross-fade module having at least first and second audio inputs and an audio output port to provide an audio output signal to an external audio reproduction system. A control signal determines whether to provide the first or the second audio signal to the audio output, and the cross-fade module cross-fades the audio output signal from one audio signal to the other audio signal. A beat alignment module determines a delay between a first beat of the first audio signal and a second beat of the second audio signal, and a delay module delays either the first or the second audio signal to compensate for the delay into the cross-fade module.

Abstract: Techniques described herein are directed toward creating one or more “dynamic profiles” for media (video) streaming in which an encoding bit rate (and optionally other profile settings) is optimized for particular content. More specifically, techniques involve performing one or more “probe” encodings of the particular content to determine an encoding bit rate (and optionally other profile settings) that results in an encoding having a quality value sufficiently near (within a threshold) a target quality value.

Abstract: A method, a computer-readable medium, and an apparatus for resampling audio signal are provided. The apparatus resamples the audio signal in order to preserve the audio playback quality when dealing with audio playback overrun and underrun problem. The apparatus may receive a data block of the audio signal including a first number of samples. For each sample of the first number of samples, the apparatus may slice a portion of the audio signal corresponding to the sample into a particular number of sub-samples. The apparatus may resample the data block of the audio signal into a second number of samples based on the first number of samples and the particular number of sub-samples associated with each sample of the first number of samples. The apparatus may play back the resampled data block of the audio signal via an electroacoustic device.

Abstract: An information processing device including a sound output control unit that performs control related to sound output, in a case where an image captured at a first frame rate is subjected to display reproduction at a second frame rate lower than the first frame rate, on the basis of at least one of an input image signal, an input sound signal, reproduction speed information indicating a ratio between the first frame rate and the second frame rate, or user input information, in which the control related to the sound output performed by the sound output control unit includes switching control that selects one sound output method from a plurality of sound output methods and performs switching, or mixing control that performs mixing of sound signals obtained by the plurality of sound output methods.

Abstract: An improved integrator for use in physical analog-computing systems is disclosed, featuring real-time dynamic amplitude scaling schemas that make use of an injected correction factor responsive to a contemporaneous change in an input dynamic-amplitude-scaling compensation factor. The injected correction factor is designed to reduce or eliminate transient output perturbations due to the amplitude scaling change. The disclosures discussed have real-world applications for physical analog computers and hybrid computers used to control and manage many types of industrial-control systems.

Abstract: A digital-to-analog conversion device and a digital-to-analog conversion system with multiple digital-to-analog conversion cores is provided. At least some of the multiple digital-to-analog conversion cores may be operated with different clock signals, especially with clock signals of different clock frequencies. For this purpose, each digital-to-analog conversion stage is provided with multiple different clock signals and each stage individually selects one of the multiple clock signals.

Abstract: A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors

Abstract: Communication bus enable devices to communicate and exchange information and control signals. There is a growing concern over the security of such types of buses. Since any device can transmit any message, and device on the bus which can be compromised poses a threat for the bus. Described is a system to authenticate the source of messages from various devices on a communication bus.

Abstract: Communication bus enables devices to communicate and exchange information and control signals. There is a growing concern over the security of such types of buses. Since any device can transmit any message, and device on the bus which can be compromised poses a threat for the bus. Described is a system to authenticate the source of messages from various devices on a communication bus.

Abstract: In a fault waveform recording device, a first storage stores data detected in a power system, the data being up-to-date and indicating an electrical quantity during a first period, and halts the updating of the data stored in the first storage after a second period has elapsed since an abnormality detection time at which an abnormality in the power system is detected. The second period is shorter than the first period. First operation unit stores data in a first interval as is into a second storage, among the data of the first period stored in the first storage after the updating of the data stored in the first storage is halted, the first interval including the abnormality detection time, and decimates data in a second interval different from the first interval.

Abstract: An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.

Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

Abstract: A signal processing apparatus is provided which can suppress external noise without degrading an audio characteristic.

Abstract: A global navigation satellite system (GNSS) signal tracking system (GNSSSTS), deployed in a tracking channel of a GNSS baseband engine, includes a piecewise down sampling module for generating code bit accumulated values (CBAVs) at different time instants at a reduced rate from samples of intermediate frequency data received at a high rate, and a pseudo random noise (PRN) code generation module for generating a PRN code bit sequence (PRNCBS) corresponding to a GNSS signal and storing arms of the PRNCBS. The GNSSSTS includes a primary mixer for generating a despread value for a selected arm of the PRNCBS and a phase component generation module (PCGM) for generating inphase and quadrature phase correlation components of the despread value for storage in a storage array. The primary mixer, the PCGM, and the storage array perform their functions continuously for each CBAV generated at a corresponding time instant in a time multiplexed manner.

Abstract: Disclosed herein is a method and apparatus for converting a stream of samples at a first sampling rate to a stream of samples at a second sampling rate. An exemplary method includes measuring the first sampling rate; determining a first upsampling factor from a basis including: the measured first sampling rate, the target value of the second sampling rate, and a resynchronisation error factor, the first upsampling factor being constrained to be an integer power of a predetermined integer value; and deriving, from a reference set of filter coefficients and from a ratio of the first upsampling factor to a reference upsampling factor, a first set of filter coefficients for use in a first interpolation filter, the reference set of filter coefficients being for a reference upsampling factor that is an integer power of the predetermined integer value.

Abstract: A controller for use in a power converter includes a comparator configured to compare a sense signal representative of an amount of energy delivered to an output of the power converter, to a target value. An update clock generator configured to receive the sense signal and to generate a clock signal having a clock frequency in response to the sense signal. A request control coupled to the comparator and to the update clock generator, the request control configured to generate a request signal having a request frequency that is responsive to an output of the comparator and that controls an operational state of a power switch of the power converter. The request control further configured to update a rate at which the request frequency of the request signal is responsive to the clock frequency of the clock signal.

Abstract: A context information processor for a communication network, comprising a determination unit configured to determine a context information of a user, an evaluation unit configured to evaluate whether the context information of the user complies with an active behavior profile of the user, and a transmitter configured to transmit the context information if the context information does not comply with the active behavior profile.

Abstract: The present disclosure provides a resampling apparatus and a resampling method. The resampling apparatus includes a control unit, a memory device, a resolution identifier, a phase rate generator, a coefficient generator, and a resample filter. The control unit controls reading and writing operations of the resampling apparatus according to a control signal. The memory device transmits the control signal to the control unit. The resolution identifier sets a resolution bandwidth identity according to an interpolation/decimation (I/D) value of the control signal. The phase rate generator generates a phase select signal and a counter enable signal according to the resolution bandwidth identity. The coefficient generator generates a coefficient select signal according to the resolution bandwidth identity. The resample filter generates a resampled output data according to the phase select signal, the coefficient select signal, and an input data.

Abstract: In an aspect, an apparatus receives content to be transmitted and generates a first turbo encoded codeword from the content through use of a first turbo encoder. The apparatus is further configured to generate an interleaved codeword based on the first turbo encoded codeword through use of an interleaver, generate a second turbo encoded codeword from the interleaved codeword through use of a second turbo encoder, and transmit at least a portion of the second turbo encoded codeword. In another aspect, an apparatus receives data including outer turbo encoded, interleaved, inner turbo encoded content. The apparatus generates a first decoded instance of the data, generates a de-interleaved instance of the data based on the first decoded instance of the data, generates a second decoded instance of the data from the de-interleaved instance of the data, and performs a CRC on the second decoded instance of the data.

Abstract: A signal protector utilizes a variable latency station to provide error correction.

Abstract: A method of generating asynchronous feedback information for asynchronous, isochronous audio communication may include determining a relative change of stored samples in a device and generating the asynchronous feedback information provided to a host from the device based on the relative change. A method of generating asynchronous feedback information for asynchronous, isochronous audio communication may include determining a relative phase of a host clock for a host and a device clock for a device and generating the asynchronous feedback information provided to the host from the device based on the relative phase.

Abstract: A fill level control apparatus configured to control the average fill level of an asynchronous first-in-first-out, FIFO, the fill level control apparatus comprising an offset calculation unit adapted to or configured to calculate the offset between a programmable target average fill level and the current average fill level of the FIFO and an adjustment unit adapted to or configured to adjust continuously the empty rate of the FIFO in response to the calculated offset to keep the average fill level of the FIFO constant.

Abstract: A signal analyzing circuit is described, with at least a first channel, the first channel comprising a digitizer configured to digitize an input signal into a time-and-value-discrete signal; a switching unit coupled to the digitizer, the switching unit being adapted to receive the time-and-value-discrete signal and an acquisition memory coupled to the switching unit. The switching unit is adapted to selectively activate a decimator unit in a time-domain operation mode, the decimator unit decimating the time-and-vale-discrete signal to a decimated time-and-value-discrete signal or a digital down converter unit in a spectrum view operation mode, the digital down converter unit down-converting the time-and-value-discrete signal to a down-converted time-and-value-discrete signal.

Abstract: Apparatus and methods related to multipath bandpass filters with passband notches are provided herein. In certain configurations, a multipath bandpass filter includes multiple filter circuit branches or paths that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a downconverter that downconverts the input signal to generate a downconverted signal, a filter network that generates a filtered signal by filtering the downconverted signal, and an upconverter that upconverts the filtered signal to generate a branch output signal. The filter network includes at least one low pass filter and at least one notch filter to provide a passband with in-band notches. The branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Abstract: A signal analyzing circuit is described, with at least a first channel, the first channel comprising a digitizer configured to digitize an input signal into a time-and-value-discrete signal; a switching unit coupled to the digitizer, the switching unit being adapted to receive the time-and-value-discrete signal and an acquisition memory coupled to the switching unit. The switching unit is adapted to selectively activate a decimator unit in a time-domain operation mode, the decimator unit decimating the time-and-vale-discrete signal to a decimated time-and-value-discrete signal or a digital down converter unit in a spectrum view operation mode, the digital down converter unit down-converting the time-and-value-discrete signal to a down-converted time-and-value-discrete signal.

Abstract: An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.

Abstract: An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.

Abstract: A digital pre distortion (DPD) calibration coefficient control method and apparatus are applied to a microwave communications device that includes an analog device and a digital device, and can ensure a DPD calibration effect, where the method includes determining, by interpolation and according to DPD calibration coefficients corresponding to at least 2N typical working states of the analog device obtained in advance, a specified DPD calibration coefficient corresponding to a specified working state of the analog device, where N is a quantity of parameters representing a working state of the analog device, and controlling a DPD calibration coefficient according to the determined specified DPD calibration coefficient corresponding to the specified working state of the analog device.

Abstract: Systems and methods relating to a transceiver architecture that maintains legacy timing by inserting and removing a cyclic prefix at a legacy sampling rate are disclosed. In some embodiments, a system for a receiver comprises an upsampling subsystem, a cyclic prefix removal unit, and a downsampling subsystem. The upsampling subsystem is operable to process a first baseband receive signal that is at a first sampling rate to generate an upsampled baseband receive signal at a second sampling rate that is greater than the first sampling rate. The cyclic prefix removal unit is operable to remove a cyclic prefix from the upsampled baseband receive signal to provide a second baseband receive signal at the second sampling rate. The downsampling subsystem is operable to process the second baseband receive signal to generate a downsampled baseband receive signal at the first sampling rate. In this manner, complexity and power consumption are reduced.

Abstract: A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors

Abstract: A first stage of a digital filter received input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and (2) the first clock pulse of the first clock.

Abstract: The subject disclosure is directed towards dynamically computing anti-aliasing filter coefficients for sample rate conversion in digital audio. In one aspect, for each input-to-output sampling rate ratio (pitch) obtained, anti-aliasing filter coefficients are interpolated based upon the pitch (e.g., using the fractional part of the ratio) from two filters (coefficient sets) selected based upon the pitch (e.g., using the integer part of the ratio). The interpolation provides for fine-grained cutoff frequencies, and by re-computation for each pitch, smooth anti-aliasing with dynamically changing ratios.

Abstract: Embodiments include methods and devices for processing a digital composite signal generated at a first sampling rate. The signal includes at least first and second carrier-bands arranged to define a first inner gap between the carrier-bands. The first inner gap includes at least a first gap between the highest frequency of the first carrier-band and the lowest frequency of the second carrier-band. The digital composite signal has a predetermined instantaneous bandwidth that is lower than a sampling bandwidth. An outer gap located outside the instantaneous bandwidth and within the sampling bandwidth is determined. The first inner gap is reduced to define a second inner gap, where a width of the second inner gap is related to a width of the outer gap. The resulting folded digital composite signal is decimated to a second sampling rate lower than the first sampling rate thereby creating a decimated folded digital composite signal.

Abstract: A system may include an interpolator circuit configured to receive a first signal with a first rate and to generate an interpolated signal with a second rate. The system may include a cancellation circuit configured to determine an interference component signal based on the interpolated signal. The system may further comprise an adder configured to receive a second signal with the second rate and to cancel interference in the second signal using the interference component signal to generate a cleaned signal.

Abstract: A digital measurement input for an electric automation device has a receiving device configured to receive digital input measurement values generated by sampling an analog measurement signal at a first sampling rate, and a signal converting device configured to generate digital output measurement values from the digital input measurement values and to provide digital output measurement values. The sampling rate and sampling times of each digital output measurement value is adapted to a specified sampling rate and/or specified sampling time. The signal converting device has a digital encoder filter on the input side and a digital decoder filter on the output side, between which an interpolator is provided. The encoder filter, the interpolator, and the decoder filter are matched to one another so as to adapt the sampling rate and/or sampling time of the digital input measurement values.

Abstract: The invention relates to a wind power plant control system arranged for controlling one or more wind turbine generators in a wind power plant, wherein the wind power plant control system comprises a power plant controller and a modeling unit, the modeling unit being operatively coupled to the power plant controller. The modeling unit is arranged to calculate estimated values of electrical output parameters from the one or more wind turbine generators, and to output said estimated values to the power plant controller. The power plant controller is arranged for determining reference signals for dispatching to the one or more wind turbine generators, wherein the estimated values of said electrical output parameters are used by the power plant controller in the determination of said reference signals. The invention also relates to a corresponding method of controlling a wind power plant.

Abstract: Imager arrays, array camera modules, and array cameras in accordance with embodiments of the invention utilize pixel apertures to control the amount of aliasing present in captured images of a scene. One embodiment includes a plurality of focal planes, control circuitry configured to control the capture of image information by the pixels within the focal planes, and sampling circuitry configured to convert pixel outputs into digital pixel data. In addition, the pixels in the plurality of focal planes include a pixel stack including a microlens and an active area, where light incident on the surface of the microlens is focused onto the active area by the microlens and the active area samples the incident light to capture image information, and the pixel stack defines a pixel area and includes a pixel aperture, where the size of the pixel apertures is smaller than the pixel area.

Abstract: A signal interface unit in a radio system includes an external device interface configured to receive a downlink asynchronous radio carrier signal for a radio frequency carrier from an external device; a clock conversion unit communicatively coupled to the external device interface and configured to re-clock the downlink asynchronous radio carrier signal to a master clock of the radio system from the clock of the external device; and an antenna side interface configured to communicate at least one of the re-clocked downlink asynchronous radio carrier signal and a downlink digitized radio frequency signal based on the re-clocked downlink asynchronous radio carrier signal to an antenna unit.

Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

Abstract: System and methods are provided for tracking baseline signals for touch detection. The system includes: a comparison network configured to determine whether an input baseline signal is within a tracking range; a filter network configured to generate an output baseline signal for touch detection based at least in part on the input baseline signal according to one or more filter parameters; and a signal processing component configured to update the one or more filter parameters based at least in part on the determination of whether the input baseline signal is within the tracking range.