Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: A source sampling rate is associated with first or second groups of sampling rates. A playback rate is determined by: (a) selecting the source sampling rate if the source sampling rate is supported by a playback environment; (b) otherwise if there is a highest first rate from the first or second groups of playback sampling rates which is supported by the playback environment and is lower than the source sampling rate, selecting the first rate; (c) otherwise if there is a slowest second rate from the group that the source sampling rate is associated with that is supported by the playback environment and is higher than the source sampling rate, selecting the second rate; (d) otherwise selecting the slowest sampling rate supported by the playback environment from the group that the source sampling rate is not associated with as the playback rate.

Abstract: Techniques of this disclosure provide for adjustment of a conversion rate of a sampling rate converter (SRC) in real-time. The SRC determines relative timing of generated output samples based on non-approximated integer components that are recursively updated. The SRC may further base relative timing of output samples on a value of one or more step size components associated with the integer components. Also according to techniques of this disclosure, a conversion rate of an SRC may be adjusted in real-time based on a detected mismatch between a source clock of a digital input signal and a local clock.

Abstract: A sample rate converter includes a digital filter and control logic coupled to the digital filter. The digital filter is configured to receive an input data stream and to up convert the input data stream to produce an output data stream having a fixed data rate. The control logic configured to dynamically select a set of coefficients for taps in the digital filter during each clock cycle corresponding to the fixed data rate. The set of coefficients selected for each clock cycle is in accordance with a phase of the input data stream.

Abstract: Method and apparatus for generating a target frequency having an over-sampled data rate using a system clock having a different frequency are disclosed. In one aspect of the present disclosure, the circuit includes, a digital phase locked loop coupled to the system clock. The digital phase locked loop including an oscillator output and an oscillator input. The circuit further comprises an extra pulse eliminator coupled to the oscillator output. The extra pulse eliminator includes an extra pulse eliminator output. One or more frequency dividers may be coupled to an extra pulse eliminator output.

Abstract: An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

Abstract: A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.

Abstract: A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value.

Abstract: A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency.

Abstract: A first data buffer stores LEVEL representing the size of a non-zero coefficient value of the variable length coded/run length coded data input from the outside. A write controller writes the LEVEL to the first data buffer in decoded order. An initial address calculator calculates the initial address of the LEVEL from the TotalCoeff and the number of zero coefficients of the total_zeros. An address holder determines and holds the address of the LEVEL corresponding to data based on the initial address and the number of zero coefficients by the run_before. A read controller reads the LEVEL from the first data buffer based on the address information. A selector selects the data of either the LEVEL stored in the first data buffer or the zero coefficients based on the address information. A post-stage processor post-stage processes the data selected by the selector.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: An audio codec in a baseband processor may be utilized for mixing audio signals received at a plurality of data sampling rates. The mixed audio signals may be up sampled to a very large sampling rate, and then down sampled to a specified sampling rate that is compatible with a Bluetooth-enabled device by utilizing an interpolator in the audio codec. The down-sampled signals may be communicated to Bluetooth-enabled devices, such as Bluetooth headsets, or Bluetooth-enabled devices with a USB interface. The interpolator may be a linear interpolator for which the audio codec may enable generation of triggering and/or coefficient signals based on the specified output sampling rate. An interpolation coefficient may be generated based on a base value associated with the specified output sampling rate. The audio codec may enable selecting the specified output sampling rate from a plurality of rates.

Abstract: Disclosed is an apparatus in which there are provided a first storage unit for storing signals to which indexes are given in order to distinguish each of a plurality of signals that are to be coded; a first index computing unit for computing first indexes of non-zero signals among the signals stored in the first storage unit; a second index computing unit for computing second indexes from a base index and the first indexes; a second index storage position search unit for searching for a storage position in a second storage unit in which the second indexes are to be stored based on values of the indexes stored in the second storage unit; a second index preserving unit for preserving the second index in the second storage unit based on a storage position searched for by the second index storage position search unit; and a control unit for giving the base index to the second index computing unit and for controlling operation of the first index computing unit, the second index computing unit the second index stor

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for encoding and decoding information. In one aspect, methods of encoding information in an encoder include the actions of receiving a signal representing information using a collection of discrete digits, converting, by an encoder, the received signal into a time-based code, and outputting the time-based code. The time-based code is divided into time intervals. Each of the time intervals of the time-based code corresponds to a digit in the received signal. Each digit of a first state of the received signal is expressed as a event occurring at a first time within the corresponding time interval of the time-based code. Each digit of a second state of the received signal is expressed as a event occurring at a second time within the corresponding time intervals of the time-based code, the first time is distinguishable from the second time.

Abstract: A method for decoding a message is disclosed. The method is used for an electronic system for displaying messages. The method comprises the following steps: a processing module decoding an un-decoded string of a message received from a message transferring terminal, acquiring a first word group and saving the first word group to a word group handling buffer, and recording a repetition value of the first word group; the processing module decoding an un-decoded string of a message received from the message transferring terminal, acquiring a second word group from the un-decoded string, and saving the second word group to a word group decoding buffer; the processing module comparing the first word group and the second word group to determine whether the first word group and the second word group are the same; and if yes, increasing the repetition value of the first word group.

Abstract: A sample rate converter in which filtering is decomposed into phases as permitted by zero padding is described. The outputs of the phases are issued in the correct sequence to provide the resampled sequence.

Abstract: A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: A system and method for decimating a digital signal is disclosed. The system includes an input to receive digital data, a control input to receive a desired decimation rate, and an integrator stage responsive to the input. The system also includes a variable rate down sampling module responsive to the integrator stage and a differentiator stage responsive to the variable rate down sampling module. The down sampling module has a decimation rate that is dynamically adjustable based on the desired decimation rate.

Abstract: One or more circuits in a mobile phone may be utilized for up sampling two or more audio signals to a same data sampling rate. Each audio signal, such as digital audio, voice, and polyringer, for example, may be received at one of a plurality of data sampling rates and one or more of the following wireless standards: WCDMA, HSDPA, GSM, GPRS, EDGE, and/or Bluetooth. Audio signals may be equalized and/or compensated with an FIR filter before up sampling or with an IIR filter to reduce overall processing latency. Multiple half-band interpolation operations may perform the up sampling. The first half-band filter may be replaced by an IIR filter to reduce overall processing latency. A gain of the up-sampled data may be adjusted to reduce noise effects. The channels of the up-sampled audio signals may be mixed and later further up sampled for subsequent communication to an output device.

Abstract: A waveform compression and display technique saves both a peak detected version (background version) and a decimated/lowpass filtered version (foreground version) of a sampled electrical signal. The two versions are displayed simultaneously overlaid together in a contrasting manner so as not to obscure information contained in either of them. The lowpass filtered version uses a series of simple lowpass filters with decimation to produce a single data stream from a plurality of data streams derived from the sampled electrical signal. The single data stream may then be subjected to additional filtering, such as a cascaded integrator-comb filter, to obtain a desired frequency bandwidth. When displayed, the peak detect pixels adjacent the decimated/lowpass filtered pixels may be adjusted in intensity so that the low frequency information of the lowpass filtered waveform is not lost, while the peak detect pixels further from the lowpass filtered pixels are intensified to highlight the high frequency information.

Abstract: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include symbol recognition logic to determine a symbol using a difference between a nearest predetermined phase value to a sample and a nearest predetermined phase value to a prior sample.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: Techniques for minimizing signal loss in transit are described. Data signals lose their strengths while traveling across conductive passages such as cooper wire, cooper strip, Printed Circuit Board (PCB), etc. There are two major factors that affect the signal loss: the distance and the speed. To minimize signal loss while maintaining higher rate data signals for I/O, substantially lower rate data signals are used in transit between two interfaces over a signal path.

Abstract: An encoder encodes data into parallel codewords. Each codeword is expressed as a set of logic 0s and a set of logic 1s on two sets of output nodes. The encoder selects a current codeword which differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. The current codeword is selected such that the first and second sets of nodes are different than additional nodes that contain transitions between the immediately preceding codeword and a bi-preceding codeword, and that logic values on additional nodes are unchanged between immediately preceding codeword and current codeword. A decoder decodes the codewords by comparing symbols on node pairs other than those for which transitions were expressed in the preceding code word, and decoding the results of those comparisons.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: Control of signal compression is coordinated by selectively modifying control parameters affecting the bit rate, sample rate, dynamic range and compression operations. Selected control parameters are modified according to a control function. The control function can include a ratio parameter that indicates the relative or proportional amounts of change to the control parameters. Alternatively, the control function can be represented in a lookup table with values for the selected control parameters related by the control function. Downsampling the input signal samples according to a sample rate control parameter is followed by upsampling to the original sample rate. Errors are calculated between the upsampled and original signal samples. Encoding of the downsampled signal samples and the error samples is performed in accordance with a compression control parameter. The sample rate control parameter and compression control parameter are determined based on the control function.

Abstract: Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.

Abstract: A digital-to-analog converting system with sampling rate conversions includes an interpolator, S orders of operating and filtering units, an up-converting and down-converting circuit, and a signal processing circuit. The interpolator performs an N-times interpolation on a first digital input signal to generate a second digital input signal. Each order of the operating and filtering unit includes a K-times zero-padding circuit and a filtering circuit. The filtering circuit performs a filtering operation to generate a filtered digital input signal. The up-converting and down-converting circuit performs a B-times up-conversion and an A-times down-conversion on the filtered digital input signal to generate a fourth digital input signal. The signal processing circuit generates an analog output signal according to the fourth digital input signal.

Abstract: A sampling frequency conversion apparatus having sampling frequency conversion circuits for a plurality of channels includes a detector detecting phase information of digital signals inputted to the conversion circuit for each channel, and an input section inputting setting information for the conversion circuits for two or more channels to be phase-synchronized. The apparatus further includes a phase information supplier supplying the phase information for the conversion circuit for a specific channel designated by the setting information inputted into the input section to the conversion circuits for the remaining channels of those for two or more channels other than the conversion circuit for the specific channel, and a sampling frequency converter performing sampling frequency conversion on the phase information of the conversion circuits for the remaining channels in synchronization with the phase information for the specific channel supplied from the phase information supplier.

Abstract: A special data including communication wire continuous dominant levels of a number of N more than the transceiving bit number of n of communication wire continuous dominant levels, set in a character as one unit of communication data, can be transceived by a widely-used serial communication interface such that a predetermined transmission rate is changed to n/N times the transmission rate only when the special data is transmitted, whereby the special data can be easily transceived at a low cost.

Abstract: Systems and methods for ensuring proper phase alignment of audio signals which are processed by separate hardware channels in an audio amplification system. In one embodiment, the phase alignment is controlled by determining the number of audio data samples which are stored in the input buffers of multiple audio amplification units and controlling reads from the input buffers to minimize the difference between an actual read-write pointer differential and a target differential. In a master unit, the target differential is a predetermined target value corresponding to a desired delay in the buffer. The actual pointer differential of the master unit is passed to one or more slave units. The actual pointer differential of the master unit is used as the target differential of the slave units. The pointer differentials of the slave units are thereby driven to track the pointer differential of the master unit, keeping the units synchronized.

Abstract: An audio processor is disclosed and includes a sample rate converter and a digital phase-locked-loop module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of filters.

Abstract: A methods and devices for polyphase resampling are presented which may comprise a coefficient generator which provides a plurality of coefficients and an interpolation arrangement used to carry out the resampling by means of the coefficients applied to input data provided for resampling in order to provide output data. In one possible implementation the coefficient generator is constructed and/or controlled so as to provide the coefficients for the resampling in the form of linearly interpolated coefficients. In another alternative implementation, a plurality of at least two data interpolation filters are provided for the interpolation of a corresponding number of parallel input data, wherein the coefficients are input to each of the data interpolation filters.

Abstract: The present invention is related to a circuit for converting the sample rate of a digital signal, comprising an input for applying the digital signal, a conversion filter having either a symmetrical or anti-symmetrical impulse response and implemented as a plurality of subfilters in parallel, each subfilter having a symmetrical or anti-symmetrical response derived from components of a polyphase decomposition of said impulse response, combining means for deriving from said applied digital signal input signals of said plurality of subfilters or for combining output signals of said plurality of subfilters into a digital signal with converted sample rate, an output for outputting said digital signal with converted sample rate.

Abstract: The invention allows the interpolation factor, a critical parameter in sample rate conversion systems, to be computed in a real-time system where there is a complex relationship between a DSP clock and the data clocks. Typically, two or three of the clocks in such a system will have simple relationships (such as CLOCK1=2*CLOCK2). This relationship leads to degenerate cases where, in fact, there are only one or two clocks to consider rather than three. Furthermore, the invention allows for input data rates that are higher than the DSP clock rate. The invention also provides for an arbitrary time delay to be applied to the output signal.

Abstract: An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.

Abstract: A transcoder calculates a reference conversion factor on the basis of a ratio between a total target bit rate of a whole second stream and an total input bit rate of a whole first stream and calculates a coefficient of variation from the total target bit rate of the whole second stream and an average output bit rate of a converted second stream in the N period. Next, a quantization step conversion factor in the next (N+1) period is calculated by adding the coefficient of variation to the reference conversion factor. Then, a quantization step value of a second stream in the (N+1) period is calculated by multiplying a quantization step value of a first stream in the (N+1) period by the quantization step conversion factor.

Abstract: A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

Abstract: Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value ?? based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset ? as necessary.

Abstract: An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

Abstract: Asynchronous sample rate conversion for use in a digital audio receiver is disclosed. Different algorithms are applied for the upsampling and downsampling cases. In the upsampling case, the input signal is upsampled and filtered, before the application of a finite impulse response (FIR) filter. In the downsampling case, the input signal is filtered by an FIR filter, and then filtered and downsampled. The FIR coefficients of the fractional delay FIR filter are calculated by evaluation of polynomial expressions over intervals of the filter impulse response, at times corresponding to the input sample points.

Abstract: Methods for performing cardiac signal analysis in an implanted medical device, and devices configured to perform illustrative methods of cardiac signal analysis. A cardiac signal is captured by an implanted device using implanted electrodes and, during at least certain conditions, the cardiac signal undergoes heuristic filtering. In some embodiments, heuristic filtering is achieved by modifying a signal or value that is used as an indicator of received signal amplitude. In an illustrative example, the heuristic filtering includes periodically incrementing or decrementing the signal or value toward a desired quiescent point, where the heuristic filter period is significantly longer than the sampling period for the signal itself. In another illustrative example, the heuristic filter frequency can be adjusted dynamically to keep the signal average near the desired quiescent point.

Abstract: The sample rate of a digital signal is converted by a digital simulation of an analog filter. The simulation can update the states of complex poles in the analog filter at arbitrary times using different techniques. One technique updates the states at variable rates. Other techniques update the states at a fixed rate in response to values of input or output samples that are modified to account for offsets between the times of the samples and the times the states are updated. The states may be updated by using interpolations of complex exponential functions. Values of the complex exponential functions may be obtained from a product of values obtained from multiple lookup tables.

Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.

Abstract: The invention relates to a method and a device for polyphase resampling, having a coefficient generator (11) which provides a plurality of coefficients (C0, C1, . . . C5) and an interpolation arrangement used to carry out the resampling by means of the coefficients (C0-C5) applied to input data provided for resampling (Din; Yin, Uin, Vin) in order to provide output data (Dout; Yout, Uout, Vout). In this case it is preferred when the coefficient generator (11) is constructed and/or controlled so as to provide the coefficients (C0-C5) for the resampling in the form of linearly interpolated coefficients. It is in particular advantageous when a plurality of at least two data interpolation filters are provided for the interpolation of a corresponding number of parallel input data (Yin, Uin, Vin), wherein the coefficients (C0-C5) are input to each of the data interpolation filters.

Abstract: A digital up-sampling converter (DUSC) employs a signal input provided by a digital signal process (DSP) at a first rate feeding a Square Root Raised Cosine (SRRC) filter which provides for table look up of filter coefficients for a multiple symbol span and provides a sampling output at a second rate which is a multiple M of the first rate. A digital to analog converter (DAC) receives the sampling output at the second rate for conversion to an analog signal and a low pass analog filter processes the analog signal for delivery to an RF transmitter.

Abstract: One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.

Abstract: A sample rate converter includes an upsampling module, a low pass filter, and a linear sample rate conversion module. The upsampling module is operably coupled up-sample a digital input signal having a first rate to produce a digitally up-sampled signal. The low pass filter is operably coupled to low pass filter the digitally up-sampled signal to produce a digitally filtered signal at an up-sampled rate. The linear sample rate conversion module is operably coupled to convert the digitally up-sampled signal into a sample rate adjusted digital signal having a second rate based on an control feedback signal and a linear function, wherein a relationship between the first rate and the second rate is a non-power of two.

Abstract: A sample rate converter includes a multiplexer to select either one of an input signal and a first feedback signal, and to obtain a selected input signal, a decimator performing decimation on an Nth-order integration signal to generate an output signal, an interpolator performing interpolation on the output signal to generate a second feedback signal, a multiplier which multiplies the second feedback signal by a coefficient to generate a multiplication signal, a subtractor which subtracts the multiplication signal from the selected input signal to generate a residual signal, an adder which adds the residual signal to a third feedback signal to sequentially generate 1st-order to Nth-order integration signals, a register circuit configured to hold the integration signals, a multiplexer to select the first feedback signal from the integration signals that the register hold, and a multiplexer to select the third feedback signal from the integration signals that the register hold.