Abstract: System and methods are provided for tracking baseline signals for touch detection. The system includes: a comparison network configured to determine whether an input baseline signal is within a tracking range; a filter network configured to generate an output baseline signal for touch detection based at least in part on the input baseline signal according to one or more filter parameters; and a signal processing component configured to update the one or more filter parameters based at least in part on the determination of whether the input baseline signal is within the tracking range.

Abstract: A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors

Abstract: One or more transformation functions can be used in connection or together with one or more compression/decompression techniques. A transformation function can transform data (e.g., a data object) into a form more suitable for compression and/or decompression. As a result, data can be compressed and/or decompressed more effectively. In addition, multiple data objects can be associated with various transformation functions and/or compression/decompression techniques. As a result, different approaches can be taken with respect to compression and decompression of data objects in an effort to find an optimum approach for compression of data objects that may vary significantly from each other and change over time. It will be appreciated that the objects can be associated with transformation functions in a dynamic manner to accommodate changes to data. Also, an extendible and/or extensible system can allow for growth and adaption of new data in forms not currently present or expected.

Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may have a transmitter coupled to a modulator that modulates the first signal. The second semiconductor die may have a receiver having a counter and a control circuit. The control circuit may be adapted to determine an indication of the first signal by using the counter. In addition, an isolation system and a DC-DC feedback regulation control system having such control circuit are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise counting a received signal based on internal clock and determining an indication of the first signal from the counter's count value.

Abstract: In an example aspects of this disclosure generally relate to a method of coding video data that includes determining a first bit depth for outputting video data and a second bit depth for coding the video data, wherein the first bit depth is less than the second bit depth. The method also includes determining whether the video data will be used as reference data when coding other video data. The method also includes storing, based on the determination, the video data at the first bit depth when the video data is not used as reference data, and the video data at the second bit depth when the video data is used as reference data.

Abstract: An audio mixing device includes: an adder that adds a plurality of PDM signals each converted from a plurality of digital audio signals; a D/A converter that performs D/A conversion on a digital audio signal outputted from the adder and outputs an analog audio signal; and a synchronization device that is provided prior to the adder, and that synchronizes each of a plurality of digital signals with one another by use of the same predetermined synchronization timing signal and outputs each of them to the adder.

Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels.

Abstract: A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.

Abstract: In one example, a video coder, such as a video encoder or a video decoder, is configured to code a value for a layer identifier in a slice header for a current slice in a current layer of multi-layer video data, and, when the value for the layer identifier is not equal to zero, code a first set of syntax elements in accordance with a base video coding standard, and code a second set of one or more syntax elements in accordance with an extension to the base video coding standard. The second set of syntax elements may include a syntax element representative of a position for an identifier of an inter-layer reference picture of a reference layer in a reference picture list, and the video coder may construct the reference picture list such that the identifier of the inter-layer reference picture is located in the determined position.

Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to maintain cache coherency among multiple storage nodes. It can also be employed to avoid sending the data to a network node over a network if it already has the data.

Abstract: The disclosure provides a probe and a method for calculating statistic data of traffic flows. The probe comprises at least one link processor (LP) and a correlation processor (CP). Each LP includes two buffers, receives packets from directional traffic flows, generates information of bi-directional traffic flows based on the received packets, stores the generated information in one buffer within a reporting period and, reports the stored information to CP when the reporting period boundary is reached. The information of each bi-directional traffic flow includes the relevant identification information and statistic data. The CP calculates statistic data of a particular group of traffic flows with a predetermined characteristic based on the reported information, and the other buffer stores information of bi-directional traffic flows to be generated within a next reporting period and the stored information is to be reported to the correlation processor when the next reporting period boundary is reached.

Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.

Abstract: Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes a power demand determination unit upstream of a command execution circuit. The power demand determination unit is configured to determine, before command execution, an expected power demand of the IC chip for executing a command that is input to the command execution circuit.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.

Abstract: A method for waveform analysis and compression includes determining harmonic components of a waveform, subtracting the harmonic components from the waveform, leaving a residual waveform, and compressing the residual waveform. Information about the harmonic components and the compressed residual transform can be transmitted across a network for analysis or reconstruction of the waveform in another device. The method is used in a low cost power quality meter, which can form part of a smart metering scheme.

Abstract: A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

Abstract: A microelectronic system comprises at least one circuit block that performs certain signal processing functions and at least one clock generation circuit that produces at least one Time-Average-Frequency clock signal which comprises clock pulses of at least two different lengths. The said lengths are measured in time. The arithmetic mean of the lengths of all the pulses that exist in a time frame of one second is calculated. The Time-Average-Frequency clock pulse train is made in such way that the arithmetic inversion of the said arithmetic mean equals to a predetermined value that is the clock frequency of the Time-Average-Frequency clock signal. At least one said circuit block in the said microelectronic system is driven by the said Time-Average-Frequency clock signal. The said circuit block is setup-constrained using the minimum pulse length found among the lengths of all the pulses in the Time-Average-Frequency clock signal.

Abstract: Communication systems in which a fixed size information block is transmitted to one or multiple receivers, such as the long term evolution (LTE) of the 3rd Generation Partnership Projection (3GPP), may benefit from a structure, in which a downlink control information (DCI) format, or more generally the fixed sized information block, can be extended by a small number of bits and still be backwards compatible with older terminals, which do not need the extra bits or may not even be aware of this extension. A method for providing this extension can include preparing a first codeword for transmission. The method can also include preparing a second codeword for transmission. The second codeword can have a code rate that is configured to be less than the code rate of the first codeword. The method can further include initiating simultaneous transmission of the first codeword and the second codeword.

Abstract: The present disclosure discloses a device, system and method for bi-phase modulation decoding. The bi-phase modulation decoding device includes a sliding-window module and a determination module. The sliding-window module is configured to receive a baseband signal corresponding to a bi-phase modulated signal, and generate a filtered data packet by filtering the baseband signal using sliding-window digital filtering, wherein the filtered data packet comprises a series of sliding-window output values. The determination module configured to determine a bitstream corresponding to the bi-phase modulated signal based on the filtered data packet. The determination module determines a bit value of a first bit cycle of the bi-phase modulated signal based on a sign of a sliding-window output value of the first bit cycle and a sign of a sliding-window output value of a next bit cycle.

Abstract: There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.

Abstract: An arbitrary waveform generator (AWG) comprises a real-time digital signal processor (DSP) configured to process a stream of waveform data based on current values of processing parameters, a DSP memory configured to store information related to the processing parameters, and an update component configured to update in real-time the current values of the processing parameters based on the information stored in the DSP memory.

Abstract: A method for marking a signal edge, which has been removed from at least one decimated binary signal after the decimation of an associated binary signal, within the decimated binary signal, establishes successive signal portions of the respective binary signal, in each case with a number of sampled values corresponding to a decimation factor of the decimation. It detects a signal edge removed through decimation from each signal portion if the number of signal edges determined in each signal portion of the respective binary signal is greater than one. Then, the sampled values of the respective decimated binary signal are determined through decimation of the sampled values of the associated binary signal with the decimation factor, and the removed signal edge at the sampling time of the decimated binary signal which corresponds to the signal portion of the associated binary signal with the signal edge removed through decimation is marked.

Abstract: A method begins by processing module in response to a read command, issuing at least a read threshold number of read requests regarding a set of encoded data slices and receiving at least the read threshold number of encoded data slices. The method continues where the processing module selects a unique combination of encoded data slices and decodes the unique combination to produce a recovered data segment. The method continues where the processing module verifies an integrity value for the recovered data segment and indicates whether the unique combination is valid. The method continues where the processing module selects other combinations producing more recovered data segments for further validity verification. The method continues where the processing module utilizes a verified recovered data segment as a response to the read command and identifies a compromised encoded data slice.

Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Abstract: A method of filtering an input sample stream having a downsampling rate is disclosed to generate an output sample stream having an upsampling rate that is less than the downsampling rate. The input sample stream is input to a rate change filter having multiple filter branches. The input sample stream is filtered at each of the multiple filter branches to output filtered sample substreams. Each of the multiple filter branches have filter coefficients corresponding to a different phase of the filter response. The filtered sample substreams are stored in a memory and the stored filtered sample substreams are combined to generate the output sample stream.

Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.

Abstract: A multichannel radio receiver may include a radio frequency (RF) subsystem and a digital subsystem. The RF subsystem may be configured to provide analog information associated with a radio band to an analog to digital converter (ADC). The ADC samples the analog input and sends digital output to the digital subsystem. The digital subsystem may be configured with one or more channelizers and one or more decoders. A channelizer within the digital subsystem may filter and re-sample the digital output to result in a channel plan having a desired bandwidth and a desired sample rate. The sample rate may be selected for compatibility with a decoder. The decoder may have design specifications based in part on a modulation scheme to be decoded. The design specifications may indicate the desired sample rate to be provided by the channelizer.

Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.

Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.

Abstract: Provided is a transmitter for transmitting signals by means of the STBC method or the DSTBC method, wherein communication is carried out effectively. The transmitter for transmitting signals by means of the STBC method or the DSTBC method has the following configuration. A frame in which synchronization words are arranged at specified positions is used. An encoding means in the transmitter encodes the entire frame to be transmitted including the synchronization words, by means of the STBC method or the DSTBC method. It is also possible to implement a communication system and a communication method for communicating signals by means of the STBC method or the DSTBC method.

Abstract: Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter.

Abstract: Systems and methods for sample rate tracking are provided. An example method includes computing an actual latency associated with an output sample from an output sample stream. The actual latency is calculated using a phase and a phase increment (conversion rate ratio). A measured latency is determined using an internal clock using a presentation time of the output sample, or an input sample from an input sample stream, or both. The measured latency is compared to the actual latency to generate a latency error. A successive phase increment can be determined based on the latency error by using a low-pass or adaptive filter to adjust the latency error.

Abstract: In accordance with the present invention is provided a system and method for improving a timestamp precision in a precision timestamp protocol (PTP) device. The present invention provides for dynamic adjustment of otherwise uncertainty of the latency of a connection between two devices connected together through a gearbox and/or a block sync circuit. The dynamic adjustment is accomplished by identifying the alignment of data within the gearbox and block sync and adjusting the timestamp assigned to the data based upon the identified alignment to remove the jitter associated with the gearbox and the block sync, thereby improving the timestamp precision in the PTP device. In a particular embodiment, the invention is employed in a serial-deserializer (SERDES) device.

Abstract: A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient.

Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.

Abstract: An apparatus detects, from symbol data of a predetermined communication scheme that is input via a common public radio interface (CPRI) at a first rate indicating a chip rate for the CPRI, a timing at which a clock phase matches between the first rate and a second rate indicating a symbol rate for the predetermined communication scheme, where the CPRI is an internal interface for a radio communication apparatus. The apparatus changes, at the timing, a clock rate for transmitting the symbol data, from the first rate to the second rate.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: Systems and methods for transmitting data having a rate indicated by an associated clock signal, using a fixed rate transmission system are disclosed. One embodiment of the invention includes an unknown rate to fixed rate transmitter configured to receive unknown rate data and a clock signal that indicates the rate of the unknown rate data, and to transmit data at a fixed rate over a fixed rate link, a fixed rate to unknown rate receiver configured to receive fixed rate data including the unknown rate data via the fixed rate link, and to transmit the unknown rate data, and a recovered clock signal.

Abstract: An asynchronous sample rate converter and method for converting an input signal to a resampled output signal is disclosed. An efficient and cost-effective sample rate converter for converting an input signal of arbitrary sample rate to a resampled output signal of a second sample rate is disclosed. A hardware-efficient sample-rate converter for resampling an audio input signal with an arbitrary sample rate to an output audio signal with a known sample rate for use in an audio processor is disclosed.

Abstract: An asynchronous sampling frequency conversion device includes: a storage unit configured to store input digital signals; a data specifying unit configured to specify first data and second data based on a ratio of a sampling frequency of the input digital signal to a sampling frequency of an output digital signal, the first data being sampled at a sampling timing immediately before an ith (where i is a natural number) sampling timing of the output digital signal among the input digital signals stored in the storage unit, the second data being sampled at the sampling timing immediately after the ith sampling timing of the output digital signal; and an output data value calculator configured to calculate a value of ith data of the output digital signal based on the first data and the second data specified by the data specifying unit and the ratio.

Abstract: There is described a method of making a linear periodically time varying system shift-invariant, comprising the following steps implemented for each input signal the sampling rate of which has to be converted: —generating a set of polyphase components based on the input signal, —feeding the generated set of polyphase components to the system, and —generating an output signal by performing interleaving, shifting and addition on signals output by the system corresponding to the generated set of polyphase components processed by the system.

Abstract: A rebinning device includes a rebinning engine that transforms signal data from a first format to a second format with vectorized binning. Moreover, a data storage operably coupled to the rebinning engine stores the signal data in the second format. The rebinning device may optionally includes a capturing engine that captures the signal data in the first format and a rendering engine that renders the signal data in the second format.

Abstract: Embodiments of the invention provide a pulsed signal detection system with reduced noise bandwidth in the frontend. Analog to digital conversion speed is decoupled from the pulsed duty cycle timing. This in turn reduces the power consumption of the ADC and the front end while providing a high dynamic range. The ADC may be a continuous time sigma delta converter to reduce the drive requirements of the front end.

Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.

Abstract: Methods and systems of operating an audio receiver may include a reference module configured to determine an input number of clocks per number of frames for an audio signal based on a reference clock and a specified number of frames. The audio receiver can also include a conversion module configured to re-sample the audio signal based on the input number of clocks per number of frames, the specified number of frames, and a specified number of clocks per number of frames.

Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Abstract: A device that supports communication over parallel serial lanes may include an analog circuit domain, a digital circuit domain, a buffer between the analog domain and the digital domain, and an alignment circuit. The buffer may receive data from the digital domain according to a write clock and send out the received data to the analog domain according to a read clock. The alignment circuit may generate control signals to initiate reading from the buffer when the read clock and write clocks are aligned. In one embodiment, the device may be an analog-to-digital converter (ADC) integrated circuit (IC) chip and the buffer may be a FIFO.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.