Abstract: A method for accelerating a pseudo-random input bit flow (PRBS(T1)), generated at a first relatively low dock frequency (f1), into an identical output bit flow (PRBS(T0)) at a second relatively high dock frequency (f0), comprising: collecting the output bit flow, delaying the collected flow by a predetermined value (?); and combining the delayed flow with the input bit flow.

Abstract: A method and apparatus of mobile phone using a semiconductor device includes a first converter, a second converter, a first digital processing circuit, and a second digital processing circuit. The first converter converts a first digital audio signal sampled with a predetermined audio sampling frequency into a second digital audio signal sampled with a predetermined voice sampling frequency. The second converter converts a first digital voice signal sampled with the predetermined voice sampling frequency into a second digital voice signal sampled with the predetermined audio sampling frequency. The first digital processing circuit performs a predetermined digital computation on the second digital audio signal sampled with the predetermined voice sampling frequency and a third digital voice signal.

Abstract: Various embodiments perform sample rate conversion of a sample series at an input rate to an output rate. A version of the sample series is corrected with timing error information generated by a digital loop. The digital loop is locked to a first rate and clocked at a second rate.

Abstract: A method and an encoder (1001) are disclosed for encoding an input bitstream derived from a block of coefficients relating to video data. Leading zeros and tailing zeros are determined and removed (4050, 4070) from the input bitstream. Parity bits are generated (60) for bits remaining in the input bitstream. An encoded bitstream (1032) is then generated, where the encoded bitstream (1032) comprises the number of leading zeros, the number of tailing zeros, and the parity bits.

Abstract: An approach is provided for encoding information bits to output a coded signal using turbo code encoding with a low code rate.

Abstract: A transmitter and method is provided for digitally upconverting a baseband digital signal to a modulated intermediate frequency (IF) digital signal and sigma-delta modulating the IF digital signal. The baseband digital signal is split into N phases, as can be accomplished using a polyphase interpolation technique (polyphase filter), and modulated. The modulated N phases are not recombined and each phase is further modulated, as can be accomplished using a digital-to-digital sigma-delta modulator that generates digital output signals at the same rate. A high speed digital multiplexer multiplexes the digital output signals into a single bit stream at a higher rate for subsequent power amplification and RF transmission.

Abstract: A system and method of transcoding video data for distribution over a variety of media. A digital data stream is decoded and optionals down sampled to reduce the bit rate of the original stream. The decoded stream is further encoded to further reduce the bit rate of the data stream to be consistent with the reliable delivery capabilities of the media over which the data stream is to be transmitted and/or the display on which display is to occur.

Abstract: Aspects of a sampling rate converter with no timing drift and with bounded amplitude error are presented. Aspects of the method may include computing an intermediate sum by adding a numerator portion of a fractional conversion ratio to an accumulated time value upon receipt of an input data sample. A time instant for generating an output data sample may be determined by computing a modulus value for the intermediate sum, wherein a base for the modulus value computing may be a denominator portion of the fractional conversion ratio.

Abstract: The architecture for a combined universal sample rate converter and a sample clock synchronizer is presented. The universal sample rate converter can be applied, for example, to audio samples created or mixed using any of the standard audio frequencies in the set H={8, 11.025, 22.05, 44.1, 48, 96, and 192} kHz and played back using any other frequency from the set H. The synchronizer can be used where audio data are streamed or otherwise broadcast from, for example, the Internet, along with a system timestamp, and where this timestamp needs to be matched to the local audio clock for proper play-back. The same synchronizer can also be used for audio/video or video only synchronization.

Abstract: A sampling rate converting circuit receives plural pieces of input data having different sampling frequencies. A plurality of FIR circuits is shared to reduce a circuit area, and, in a case where a magnification ratio of an input frequency and an output frequency is not an integer, signal deterioration due to resampling is solved. An oversampling component performs oversampling on input data Fs1 and outputs output data Fs?. An input timing timer calculates an input/input time based on an input timing signal CK1. An output timing timer and an accumulator calculate an input/output time based on an output timing signal CK? and the input timing signal CK1 and multiplies the input/output time by an oversampling multiple W to obtain a multiplied result. A divider divides the multiplied result by the input/input time to obtain a sampling position. A coefficient generator generates a filter coefficient based on the sampling position and supplies the filter coefficient to a multiplier.

Abstract: Methods and apparatus are provided for decimated interpolated clock/data recovery (ICDR) to perform asynchronous sampling of a received signal. A received signal is converted to a plurality of digital samples at a downsampled rate that is lower than a rate of the received signal. The plurality of digital samples are interpolated using a plurality of parallel interpolation filters operating at the downsampled rate. An output of each parallel interpolation filter is applied to a corresponding data detector operating at the downsampled rate to generate digital data. An estimate of a timing error is generated based on the digital data. The timing error values are processed to generate an interpolation phase value that is applied to the parallel interpolation filters. A recovered clock is optionally generated, having edges corresponding to a desired synchronous sampling period.

Abstract: A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.

Abstract: An electronic apparatus reads a digital data stream including a video signal and/or an audio signal outputted from an external apparatus according to a transmission clock different from a clock for the data stream, and outputs the video signal and/or audio signal without causing any discontinuity. The electronic apparatus includes a sample rate converter that rate-converts a predetermined volume of the audio signal in synchronization with a constant sampling clock, and changes a number of samples to be outputted, based on a data volume of an audio signal outputted by the electronic apparatus and a data volume of an audio signal transmitted from the external apparatus or transmittable from the external apparatus to the electronic apparatus.

Abstract: A mechanism for use with a bus provided from parallel, capacitively-coupled bus lines to restrict a number of possible transitions on the bus to a number that is smaller than the maximum number of possible transitions so that data transmissions on the bus occur at a transmission rate which is higher than the transmission rate allowable if the number of transitions had not been restricted.

Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.

Abstract: An enhancement that reduces the digital interface rate of analog-to-digital (A/D) and digital-to-analog (D/A) converters through the use of compression and decompression is described. Improved A/D converters compressing a sampled version of an A/D converter's analog input signal in real time, thereby significantly decreasing the required bit rate of the A/D converter's digital interface. Similarly, improved D/A converters decrease the required bit rate of the D/A converter's digital interface. D/A converters include a decompressor that decompresses the D/A converter's compressed digital input in real time, prior to conversion to an analog output signal.

Abstract: Providing interpolated signals with enhanced signal-to-noise-ratio (SNR). In an embodiment, for each digital sample (of an analog signal) having strength Dn, N values are inserted, with the kth inserted value having a strength of Dn(1+/?Dk), wherein Dk is selected randomly from within a range set according to quantization noise. The received digital samples along with inserted digital values are provided as the interpolated signal corresponding to the input signal represented by the received digital samples.

Abstract: Aspects of a sampling rate converter with no timing drift and with bounded amplitude error are presented. Aspects of the method may include computing an intermediate sum by adding a numerator portion of a fractional conversion ratio to an accumulated time value upon receipt of an input data sample. A time instant for generating an output data sample may be determined by computing a modulus value for the intermediate sum, wherein a base for the modulus value computing may be a denominator portion of the fractional conversion ratio.

Abstract: Methods and systems for audio CODEC voice ADC processing are disclosed. Aspects of one method may include using a decimating filter that may be enabled to generate 13 MHz, 9-level digital output signal from a 26 MHz, 3-level digital input signal. The 13 MHz, 9-level digital output signal may be processed for RF transmission, for audio output to an output device, and/or utilized for testing by a test fixture, for example. The 13 MHz, 9-level digital output signal may be further processed to generate a 6.5 MHz, 33-level digital signal. The 6.5 MHz, 33-level digital signal may be converted to an analog signal, and processed for audio output and/or testing. The 13 MHz, 9-level digital output signal may also be processed to generate a 40 KHz, 17-bit digital signal, which may be communicated to a test equipment or further processed for RF transmission.

Abstract: In one or more embodiments, an over-sampling method and corresponding over-sampling circuit efficiently generate an over-sampled signal by determining sampling phases in the over-sampled signal that are unused by downstream processing of the over-sampled signal, and skipping the generation of output values for the over-sampled signal that correspond to the unused sampling phases. In a communication receiver embodiment, determining the unused sampling phases comprises, with respect to currently estimated multipath delays of a received communication signal from which the over-sampled signal is derived, determining which sampling phases in the over-sampled signal will not be used by a downstream processing circuit having known processing delay assignment constraints. The known delay assignment constraints comprise Rake finger placement constraints or channel equalizer tap placement constraints, for example.

Abstract: A low-complexity sampling rate conversion (SRC) method and apparatus for the processing of digital audio signals. A first stage upsamples an input audio signal to generate an upsampled audio signal. For example, the first stage may perform 1:2 upsampling using a halfband filter. A second stage re-samples the upsampled audio signal from the first stage at a target sampling rate. For example, re-sampling may be achieved using linear interpolation.

Abstract: There provided is a low-cost, high performance sampling rate conversion calculating apparatus which achieves both a low delay characteristic required for conversational voice data and high quality required for audio data in a concurrent manner. A first digital signal processing section outputs conversational voice data, which requires the low delay characteristic, in accordance with a sampling frequency of an output terminal (111). A second digital signal processing section outputs audio data, which requires the high quality, rather than the low density characteristic, in accordance with the sampling frequency of the output terminal (111). An adder section (107) adds the conversational voice data outputted from the first digital signal processing section and the audio data outputted from the second digital signal processing section and outputs the added data from the output terminal (111).

Abstract: A network transmitter and an associated transmitting method are disclosed. The network transmitter includes a signal converter and a signal driver. The former can convert an input signal into a current signal, and the latter can output a differential transmission signal according to the current signal. The signal driver includes a feedback network which can switch between a first configuration and a second configuration.

Abstract: Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value ?? based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset ? as necessary.

Abstract: Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop.

Abstract: A self-contained DAC that is especially suitable for use as an IP core, particularly for SOC (System on Chip) implementation. Techniques are applied to employ certain circuits (such as arithmetic element 302) to perform multiple functions in the DAC, thereby resulting in space saving. Techniques are also applied to employ fewer circuits per functional block to achieve further space saving. By employing multiple clock domains and turning on selective circuits on an as-needed basis, power saving is also realized.

Abstract: A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.

Abstract: Asynchronous sampling rate converter with input/output frequency ratio estimation and polyphase filtering uses FIFO level feedback to adaptively control frequency ratio estimation.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: A system including a buffer, a feedback loop configured to generate a fractional delay from a ratio of a first number of samples written into the buffer to a second number of samples read from the buffer, and a variable fractional delay filter configured to generate an output sample using a plurality of input samples and the fractional delay is provided.

Abstract: An asynchronous sample rate converter including a feedback loop configured to generate a control signal corresponding to an output sample rate that is synchronous with an output clock signal and a normalized time distance value corresponding to a plurality of input samples and an interpolator configured to generate an output sample in response to receiving the control signal using the normalized time distance value and outputs of at least two polyphase filter components that are generated from at least the plurality of input samples is provided.

Abstract: Sample rate converters (12) for converting input sample rates (F81) of signals into output sample rates (Fs4) are provided with sample rate adapters (3,6) for adapting (basic idea) intermediate sample rates (Fs2) such that output sample rates (Fs4) are larger (upsampling) or smaller (downsampling) than input sample rates (F81), to reduce their complexity and to avoid bookkeeping and structure switching problems. Sample rate adapters (3,6) in the form of variable sample rate decreasers (3) allow the sample rate converters (12) to be used in video applications requiring DC-out being equal to DC-in. Sample rate adapters (3,6) in the form of variable sample rate increasers (6) allow the sample rate converters (12) to be used in audio applications.

Abstract: The present invention relates to a data processing apparatus, a method and apparatus for encoding, a method and apparatus for decoding, and a program, that allow a reduction in an algorithm delay. An interpolator 51 produces interpolated PCM data by performing R-times oversampling on original PCM data. A frame encoder 54 fetches a predetermined number of samples of the oversampled data as one frame, encodes the oversampled data on a frame-by-frame basis, and outputs resultant encoded data. A frame decoder 55 decodes the encoded data on a frame-by-frame basis at a rate R times higher than a predetermined normal rate. A decimator 56 decimates data obtained as a result of the decoding such that the number of samples is reduced to 1/R of the number of sampled included in the original data. The present invention is applicable, for example, to an IP telephone system.

Abstract: A circuit is provided to correct a sample rate by way of time domain interpolation having a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive the output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter and a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back an output signal from the modulator to an input of the adder.

Abstract: A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134).

Abstract: The invention relates to a method for synchronizing a plurality of digital input signals which are formed by sampling with the aid of a dedicated operating clock in each case. In order to be able to carry out such a method reliably with a relatively low outlay, according to the invention digital auxiliary signals (xd(nk+j), (yd(nk+j)) are formed by sampling the digital input signals (x(k)) with the aid of a common postprocessing clock, use being made of a postprocessing clock which is at least twice as fast as the fastest operating clock; synchronized digital output signals (x(m), y(m)) which correspond to the digital input signals (x(k)) are formed by means of interpolating each digital auxiliary signal (xd(nk+j), yd(nk+j)).

Abstract: A high frequency compensator configured to compensate high frequency component of a digital audio signal comprising a down sampler configured to perform ½ down-sampling for the digital audio signal. An up sampler is configured to perform double up-sampling for an output signal of the down-sampler. A digital low-pass filter is configured to filter an output signal of the up sampler, and to output the filtered digital audio signal.

Abstract: A non-integer CIC interpolation filter is provided for use in sigma-delta digital-to-analog systems, which realizes non-integer interpolation but eliminates the need for coupling of the integrators in the output domain. The present non-integer interpolation filter provides for more attenuation to all of the aliases of the input signal and has eliminated the need of complex computations.

Abstract: A data conversion system acquires samples of low frequency signal components of an applied analog signal at a first data conversion rate and samples of high frequency signal components of the applied analog signal at a second data conversion rate that is higher than the first data conversion rate. The data conversion system applies a first correction filter to the acquired samples of the low frequency signal components to provide a first filtered signal and applies a second correction filter to the acquired samples of the high frequency signal components to provide a second filtered signal. The data conversion system interpolates the first filtered signal to provide an interpolated signal, and sums the interpolated signal with the second filtered signal to provide an output signal.

Abstract: A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.

Abstract: A method and apparatus for converting the sampling rate of digital signals including a decimating comprising a low pass filter (122) and a downsampler (124), wherein the input signal is decimated a number of times based on a ratio of an input sampling rate to an output sampling rate. The exemplary apparatus also includes an upsampler (130) and another decimator (140) wherein the signal is upsampled after decimating if a ratio of the input sampling rate to an output sampling rate is not a power of an integer number.

Abstract: In general, this disclosure describes techniques for changing a sampling frequency of a digital signal. In particular, the techniques provide a more accurate way to determining a relative timing between a desired output sample and a corresponding input sample using a non-approximated integer representation of the relative timing. The relative timing between the desired output sample and corresponding input sample may be represented using a first component that identifies a latest input sample of the digital signal used to generate intermediate samples, a second component that identifies an intermediate sample, and a third component that identifies a timing difference between the desired output sample and the intermediate sample. Each of the components may be recursively updated using non-approximated integer values.

Abstract: Described herein is a method and system for sampling rate conversion. A clamped cubic spline interpolator (CCSI) may be utilized to interpolate or decimate a source signal to provide samples at times based on a sink rate. The source clock and sink clock may be driven by independent oscillators, and may therefore drift independently. A rate tracking algorithm may monitor the relative drift and adjust the conversion of the source signal to track the sink rate.

Abstract: A real-time sample rate converter having a non-polynomial convolution kernel provides reduction in die area and power for performing sample rate conversion in real-time. A non-polynomial convolution kernel, which may be a gaussian operator, is used to determine output sample values from values of an incoming stream of values. If the input sample rate is higher than the output sample rate, the input sample stream is convolved with the gaussian kernel and then decimated to yield the output stream. If the input sample rate is lower than the output sample rate, the input stream is resampled to a small multiple of the output sample rate and convolved with the gaussian kernel to produce the output sample stream directly.

Abstract: A method and a computer program product for sample rate conversion that features distributive or hybrid filtering to reduce unwanted artifacts, such as aliasing and the computational requirements to avoid the aforementioned artifacts. The method includes receiving, at a first sample rate, a plurality of data points, associated with a first signal, operating on the plurality of data points to associate the signal with a predetermined set of parameters, with the set of parameters including a first transition band having an image associated therewith; and varying the sample rate associated with the first signal by interpolation with an interpolator having associated therewith a second transition band, with the width associated with the second transition band being a function of a spectral separation between the first transition band and its image, wherein a second signal is produced having a sequence of data samples approximating the first signal.

Abstract: A resampling detection apparatus for receiving a plurality of input signals composing a digital signal, and detecting whether the digital signal is a resampled signal, includes an estimation section that estimates a signal before resampling for the digital signal from one or more input signals, and a detecting section detects whether the digital signal is a resampled signal, using the estimated signal and one or more input signals.

Abstract: Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. Input data samples provided at a first sample rate are converted to output data samples at a second sample rate unequal to the first sample rate. An Infinite Impulse Response filter having internal states are updated at the first sample rate filters the input data samples in, to produce filtered data samples at the first sample rate. Output data samples are output at the second sample rate, where each output data sample is created as the sum of at least two intermediate products, a first intermediate product and a second intermediate product.

Abstract: Huffman encoding, particularly from a packed data format, is simplified by using two different table formats depending on code length. Huffman tables are also reduced in size thereby. Decoding is performed in reduced time by testing for the length of valid Huffman codes in a compressed data stream and using an offset corresponding to a test criterion yielding a particular test result to provide a direct index into Huffman table symbol values while greatly reducing the size of look-up tables used for such a purpose.

Abstract: A method and apparatus for receiving a plurality of component parts of a hypodermic syringe, at least some of which are elongated with one enlarged end, from a plurality of molding machines and for conveying such parts in a programmed manner to a plurality of assembly machines including a plurality of coneyors each having a primary conveyor paths for feeding parts from a molding machine and a plurality of secondary conveyor paths for feeding parts from a primary conveyor path to the assembly machines; diverter means between the primary conveyor path and secondary conveyor path for directing parts to a preselected one of the secondary conveyors and to a preselected assembly machine; isolator means on a primary conveyor path to separate a predetermined number of parts from all other parts and to allow such separated parts to be fed as a group to the diverter means; and orienting means associated with at least some of the primary conveyor path to move elongated parts in a hopper to a position at the input end of