Byte Length Changed Patents (Class 341/95)
  • Patent number: 11966740
    Abstract: A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Graphcore Limited
    Inventors: Mrudula Gore, Alan Alexander
  • Patent number: 11783852
    Abstract: An information processing device selects, in a case where a plurality of pieces of data are collected and transmitted to a tape drive to be recorded on a magnetic tape, one mode of a first mode of transmitting a data group obtained by collecting the plurality of pieces of data without compression, to the tape drive, a second mode of transmitting a compressed data group in which the data group obtained by collecting the plurality of pieces of data is compressed, to the tape drive, or a third mode of transmitting a data group obtained by collecting a part of the plurality of pieces of data and remaining data, in which the part of the plurality of pieces of data is compressed and the remaining data is not compressed, to the tape drive, and transmits a data group generated in accordance with the selected mode, to the tape drive.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 10, 2023
    Assignee: FUJIFILM CORPORATION
    Inventors: Michitaka Kondo, Yutaka Oishi, Takashi Miyamoto, Terue Watanabe, Koji Matsumura, Yuko Uno
  • Patent number: 11762800
    Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Kunihiko Yamagishi, Toshitada Saito
  • Patent number: 11747983
    Abstract: In various embodiments, a write state application generates a snapshot that includes one or more data values associated with a source dataset. In operation, the write state application performs one or more compression operations on the source dataset to generate a first compressed record. The write state application then serializes the first compressed record and a second compressed record to generate a first compressed record list. Finally, the write state application generates the snapshot based on the first compressed record list. When the data values are accessed from the first snapshot, the size of the snapshot is maintained. Advantageously, because the size of the snapshot is smaller than the size of the source dataset, some consumers that are unable to store the entire source dataset in random access memory (RAM) are able to store the entire snapshot in RAM.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 5, 2023
    Assignee: NETFLIX, INC.
    Inventor: John Andrew Koszewnik
  • Patent number: 11675545
    Abstract: One or a plurality of physical storage devices that provide a physical storage area are connected to first and second computers. The computer updates metadata indicating the address correspondence relationship between the logical address of the volume and the physical address of the physical storage area in the write processing performed based on a write request designating the volume. The first computer copies the metadata to the second computer while receiving the write request. When the address correspondence relationship indicated by the copied metadata portion is changed during copying of the metadata, the first computer updates the metadata portion and copies the metadata portion to the second computer.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: June 13, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Shugo Ogawa, Akira Yamamoto, Yoshinori Ohira, Ryosuke Tatsumi, Junji Ogawa, Hiroto Ebara
  • Patent number: 11275165
    Abstract: According to a first aspect, a pulsed radar comprises a transmitter; wherein the pulsed radar is arranged to generate a string of binary values; wherein the transmitter comprises a pulse generator arranged to generate a pulse signal comprising a series of transmit pulses with polarities determined in accordance with the string of binary values; wherein a first substring comprises a first series of values; wherein a second substring comprises a second series of values; wherein the second substring is different from the first substring; and wherein each value in the second series of values is either the same as or different from the corresponding value in the first series of values according to a repeating pattern; and wherein the string of binary values comprises at least the first substring and the second substring concatenated together and each optionally being reversed before concatenation.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: March 15, 2022
    Assignee: Novelda AS
    Inventor: Håkon André Hjortland
  • Patent number: 11226987
    Abstract: In accordance with an embodiment, described herein is a system and method for use with a multidimensional database computing environment. Particularly, a system and method are described for performing in-place data writes to a data storage medium associated with the multidimensional database computing environment. For example, when multiple data updates from calculation scripts are associated with a same set of blocks, the in-place data enable the system to reduce fragmentation of the data storage medium, and also to reduce contention due to index updates.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 18, 2022
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Kumar Ramaiyer, Young Joon Kim, Haritha Gongalore, Vilas Ketkar, Shubhagam Gupta
  • Patent number: 11003845
    Abstract: A method and associated apparatus provide for accessing contents of a worksheet file comprising a worksheet structure file and a shared strings table file. The method comprises processing the shared strings table file by opening the shared strings table file, and identifying a plurality of shared strings within the opened shared strings table file, and, for each shared string, creating an access record in an access table comprising a shared string identifier, a starting offset into a shared string text file, and a length, and retrieving data for a requested cell by obtaining a requested cell shared string identifier from the worksheet structure file, locating a requested cell access record in the access table, retrieving a requested cell string from the shared string text file at a position indicated by the starting offset and for a length indicated by the record length, and outputting the retrieved string.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 11, 2021
    Assignee: ServiceNow, Inc.
    Inventor: Azfar Kazmi
  • Patent number: 10984841
    Abstract: A length of a longest element can be determined in a memory device. An example method includes determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array. The determination of the length of the longest element can include performing a number of AND operations, shift operations, and invert operations.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Tiwari, Kyle B. Wheeler
  • Patent number: 10574260
    Abstract: Aspects for converting floating-point numbers in a processor are described herein. As an example, the aspects may include receiving, by a floating-point number converter, an exponent bit length, a base value, and one or more first floating-point numbers of a first bit length. Further, the aspects may include calculating, by the floating-point number converter, one or more second floating-point numbers of a second bit length based on the exponent bit length and the base value, the one or more second floating-point numbers respectively corresponding to the one or more first floating-point numbers.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 25, 2020
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Zhen Li, Shaoli Liu, Tianshi Chen, Yunji Chen
  • Patent number: 10558739
    Abstract: The Prefix Burrows-Wheeler Transform (“PWBT”) is described to provide data operations on data sets even if the data set has been compressed. Techniques to set up a PWBT, including an offset table and a prefix table, and techniques to apply data operations on data sets transformed by PWBT are also described. Data operations include k-Mer substring search. General applications of techniques using PWBT, such as plagiarism searches and open source clearance, are described. Bioinformatics applications of the PWBT, such as genomic analysis and genomic tagging, are also described.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: February 11, 2020
    Assignee: SPIRAL GENETICS, INC.
    Inventor: Jeremy Bruestle
  • Patent number: 10180819
    Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 15, 2019
    Assignee: Oracle International Corporation
    Inventors: Jeffrey S. Brooks, Christopher H. Olson, Eugene Karichkin
  • Patent number: 10108578
    Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 23, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Ravishankar S. Ayyagari, Supreet Joshi, Bharath Patil, Madhav Tejaswi Boddhapu
  • Patent number: 10067833
    Abstract: A storage system according to the present invention comprises a controller and multiple storage devices, constitutes a RAID group from (n+m) number of storage devices, wherein the storage system stores write data from a host computer to n number of storage devices, and stores redundant data generated from the n number of data to m number of storage devices. When failure occurs to at least one storage device, the controller reads data in a compressed state and redundant data from each of the storage devices where failure has not occurred in the storage devices constituting the RAID group, and transmits the read data in the compressed state to the storage device which is a data recovery destination.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: September 4, 2018
    Assignee: Hitachi, Ltd.
    Inventor: Akira Matsui
  • Patent number: 10042774
    Abstract: A method and apparatus for transmitting data includes determining whether to apply a mask to a cache line that includes a first type of data and a second type of data for transmission based upon a first criteria. The second type of data is filtered from the cache line, and the first type of data along with an identifier of the applied mask is transmitted. The first type of data and the identifier is received, and the second type of data is combined with the first type of data to recreate the cache line based upon the received identifier.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: August 7, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shuai Che, Jieming Yin
  • Patent number: 10032493
    Abstract: Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Tiwari, Kyle B. Wheeler
  • Patent number: 9971704
    Abstract: Methods, apparatus and design structures are provided for improving resource utilization by data compression accelerators. An exemplary apparatus for compressing data comprises a plurality of hardware data compression accelerators and a hash table shared by the plurality of hardware data compression accelerators. Each of the plurality of hardware data compression accelerators optionally comprises a first-in-first-out buffer that stores one or more input phrases. The hash table optionally records a location in the first-in-first-out buffers where a previous instance of an input phrase is stored. The plurality of hardware data compression accelerators can simultaneously access the hash table. For example, the hash table optionally comprises a plurality of input ports for simultaneous access of the hash table by the plurality of hardware data compression accelerators. A design structure for a data compression accelerator system is also disclosed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, Bartholomew Blaner, Balaram Sinharoy
  • Patent number: 9965448
    Abstract: A non-transitory computer-readable recording medium stores an encoding program that causes a computer to execute a process. The process includes first encoding a first character string in input data to a first code, when the first character string being registered in a first dictionary, the first code being associated with the first character string in the first dictionary; second encoding a second character string in input data to a second code and registering the second character string to a dynamic dictionary, when the second character string being not registered in the first dictionary, the second code being associated with the second character string and preliminary information in the dynamic dictionary; and generating encoded data including the encoded input data and the dynamic dictionary.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 8, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Kataoka, Yasuhiro Suzuki, Tatsuhiro Sato
  • Patent number: 9600599
    Abstract: The Prefix Burrows-Wheeler Transform (“PWBT”) is described to provide data operations on data sets even if the data set has been compressed. Techniques to set up a PWBT, including an offset table and a prefix table, and techniques to apply data operations on data sets transformed by PWBT are also described. Data operations include k-Mer substring search. General applications of techniques using PWBT, such as plagiarism searches and open source clearance, are described. Bioinformatics applications of the PWBT, such as genomic analysis and genomic tagging, are also described.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: March 21, 2017
    Assignee: Spiral Genetics, Inc.
    Inventor: Jeremy Bruestle
  • Patent number: 9565424
    Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 7, 2017
    Assignee: SONY CORPORATION
    Inventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
  • Patent number: 9362962
    Abstract: In a high-impedance communications interface, driver energy consumption is proportional to the number of signal transitions. For signals having three or more distinct levels, it is possible for a signal driver to salvage energy from some downward signal transitions and reuse it on some subsequent upward signal transitions. To facilitate this energy-conserving behavior, communication is performed using group signaling over sets of wires using a vector signaling code, with the design and use of the vector signaling code insuring that energy availability is balanced with energy demand.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 7, 2016
    Assignee: KANDOU LABS, S.A.
    Inventors: Richard Simpson, Andrew Kevin John Stewart, Brian Holden, Amin Shokrollahi
  • Patent number: 9337871
    Abstract: Embodiments of the present invention provide a method and an apparatus for processing data. The method includes: performing code block segmentation on a data block to obtain multiple first blocks, wherein a difference between numbers of bits of any two first blocks in the multiple first blocks is not more than 1 bit; determining multiple second blocks according to a padding bit and the multiple first blocks, wherein a value of the padding bit is a preset value; adding consecutive N?K fixed bits to each of the multiple second blocks to obtain multiple third blocks, wherein a value of the fixed bit is a preset value, and N?K?0; and performing polar encoding according to the multiple third blocks.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: May 10, 2016
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bin Li, Hui Shen
  • Patent number: 9246511
    Abstract: A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 26, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Alon Kipnis, Itai Dror
  • Patent number: 9231800
    Abstract: A method for transmitting data between two devices, in which data frames of the data are temporally adjusted in such a way that a constant number of flanks is used for the data frames. In addition, a related system, computer program, and computer program product are also described.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: January 5, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventor: Michael Hadeler
  • Patent number: 9215033
    Abstract: Some demonstrative embodiments include devices, systems and/or methods of communicating data over wireless communication symbols with check-code. For example, a wireless communication unit may communicate a sequence of wireless communication symbols representing transmitted data bits, wherein a symbol of the symbols includes at least one data block, which includes a set of data bits and a set of repetition bits, the set of data bits including a first number of the transmitted data bits, and the set of repetition bits including a second number of bits, which are identical to at least a subset of the set of data bits, and wherein the symbol includes at least one plurality of check-code bits corresponding to the at least one data block.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 15, 2015
    Assignee: INTEL CORPORATION
    Inventor: Assaf Kasher
  • Patent number: 9131189
    Abstract: Broadcast server and method for transmitting electronic program guide data to set top boxes via a broadcast network. The broadcast server is arranged to prepare a list of unique entries and associated identifications of the text items received, and to provide a compressed list to the plurality of set top boxes. The broadcast server repeats the following steps for each text item in the list: determining whether a next text item has a number of shared consecutive characters at the start in common with a compressed text item from the compressed list, identifying said compressed text item as a source of shared consecutive characters and determining the number of shared consecutive characters; storing for the next text item an identification, a reference to the source of shared consecutive characters, the number of shared consecutive characters, and the remaining non-shared text in the compressed list.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 8, 2015
    Assignee: LIBERTY GLOBAL EUROPE HOLDING B.V.
    Inventors: Nicholas Green, Simon Elliott
  • Patent number: 9019135
    Abstract: A method for efficiently computing a hash value for a string is disclosed. In one embodiment, such a method includes receiving an original string comprising multiple characters. The method computes an original hash value for the original string. The method produces an updated string by performing at least one of the following updates on the original string: adding leading/trailing characters to the original string; removing leading/trailing characters from the original string, and modifying characters of the original string while preserving the length of the original string. The method then computes an updated hash value for the updated string by performing at least one operation on the original hash value, wherein the at least one operation takes into account the updates that were made to the original string. A corresponding apparatus and computer program product are also disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Peter Douglas Bain, Peter Wiebe Burka, Charles Robert Gracie
  • Patent number: 8811467
    Abstract: A finite sequence of code values is formed, and can be used for example in communications or remote sensing. A code value in said finite sequence of code values has a validity period specific to that code value. There are code values of different validity periods in said finite sequence of code values. Each of said validity periods is longer than or equal to a predetermined minimum baud length.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 19, 2014
    Assignee: Fracticode Ltd.
    Inventor: Juha Vierinen
  • Patent number: 8797193
    Abstract: A parallel test payload includes a bit sequence configured to be segmented into a plurality of sub-sequences having variable bit length carriers. Respective carriers are represented uniformly in each one of the plurality of sub-sequences.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 5, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert Alan Ulichney, Steven J. Simske, Matthew D. Gaubatz
  • Patent number: 8724243
    Abstract: Systems and methods relating generally to processing information, and more particularly without limitation to systems and methods for encoding data sets.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 13, 2014
    Assignee: LSI Corporation
    Inventors: Razmik Karabed, Shaohua Yang, Wu Chang, Victor A. Krachkovsky
  • Patent number: 8682364
    Abstract: A system and method for sending binary data via a short message service (SMS) over a wireless communication system. The method provides the capability to send and receive binary data to a vehicle telematics unit using a text SMS message. The binary data is converted to encoded text according to an encoding scheme supported by a wireless communication system. Then, the encoded text is sent as an SMS message over the wireless communication system. Once, the SMS message containing the encoded text is received at its destination, it is converted back to binary data.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 25, 2014
    Assignee: General Motors LLC
    Inventors: Jin Tang, Ki Hak Yi, Sethu K. Madhavan
  • Patent number: 8543736
    Abstract: A data processing circuit is disclosed in the present invention. The data processing circuit includes a decoder and a number of N-stage circuits. The circuits receive input data from at least a memory and separate the input data into N stages. The circuit process and store the N input data simultaneously to decrease the time of data processing in the data processing circuit.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: September 24, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Chien-Chou Chen, Ming-Sung Huang, Wen Min Lu
  • Publication number: 20130069806
    Abstract: The present invention relates to a method and apparatus for encoding and decoding data, and more particularly, to a method and apparatus for encoding and decoding structured data. A method of encoding structured data according to the present invention includes fragmenting the structured data into fragments according to a configuration of the structured data; and encoding the fragments to generate encoded fragments using a string table including strings contained in the structured data.
    Type: Application
    Filed: August 10, 2012
    Publication date: March 21, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Bong Jin OH, Eui Hyun PAIK
  • Patent number: 8280936
    Abstract: An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventor: Hong Jiang
  • Patent number: 8166217
    Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
  • Patent number: 8156432
    Abstract: Provided are printers and other electronic devices, systems, methods, and computer program products that automatically detect and determine UTF-16 encoding schemes and endiannesss thereof in an incoming XML data steam for XML declarations without a UTF-16 byte-order mark (BOM) or encoding declaration. This allows for the automatic and unambiguous accurate detection of UTF-16 encoded XML data within a mixed encoding environment, such as from multiple sources using more than one encoding scheme, even when XML data does not start with a BOM or encoding declaration.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: April 10, 2012
    Assignee: ZIH Corp.
    Inventors: Ferdinand C. Susi, III, Jessica S. Wettstein
  • Patent number: 7978099
    Abstract: A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is further to code 17B to 20B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17B block and the second blocks of the 20B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: July 12, 2011
    Assignee: Silicon Image, Inc.
    Inventors: Seung-Jong Lee, Daeyun Shim
  • Publication number: 20110128170
    Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
    Type: Application
    Filed: October 12, 2010
    Publication date: June 2, 2011
    Inventors: Seung-Jun Bae, Seong-Jin Jang, Kwang-Il Park, Woo-Jin Lee
  • Patent number: 7949052
    Abstract: A method and apparatus to compress a DVB-ASI bit stream including accepting the stream containing packets of compressed media, sync words, and stuffing words, identifying starts of packets, identifying and discarding stuffing words; and adding information to form a compressed stream, added information sufficient to reconstruct a reconstructed stream from the compressed stream, with the relative locations of starts of packets in the reconstructed bit stream matching the relative locations of starts of corresponding packets in the accepted stream. Also a method recover the timing of MPEG packets including accepting a serial bit stream containing packets of compressed media streams, and ascertaining if the stream includes information indicating that the bit stream has a DVB-ASI form with stuffing words discarded and with indicating information added.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: May 24, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Fang Wu, Wen-hsiung Chen, Gregory D. Pelton, Joseph C. Gehman
  • Patent number: 7928866
    Abstract: An apparatus for enhancing packet communication is disclosed. In one embodiment, the apparatus includes an encoder configured to convert input data to a binary coded base system of an augmented code employing a base of an original code used for coding the input data, wherein the augmented code employs more symbols for coding than the original code, the encoder including: (1) an adder configured to add the input data to a multiplication product to generate a base sum that is binary-coded in the augmented code, (2) a multiplier configured to multiply an accumulated value by a base of the original code to provide the multiplication product that is binary-coded in the augmented code, and (3) an accumulator configured to employ the base sum to provide an accumulated value as an output for the encoder, wherein the accumulated value is binary-coded in the augmented code to represent the input data.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: April 19, 2011
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Glenn M. Boles, Ilija Hadzic, Edward Stanley Szurkowski
  • Patent number: 7859437
    Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: December 28, 2010
    Assignee: Broadcom Corporation
    Inventor: Howard A. Baumer
  • Patent number: 7843365
    Abstract: A data encoding method is provided. The data has several bytes, and each byte has n bits. The data encoding method includes the following steps. First, a specific value is defined. Next, the data is divided into one or several data blocks each having m bytes, wherein m?2n?2. Following that, a replacing value, not appearing in the m bytes of the data block, is obtained from each data block respectively, wherein the replacing value is not equal to the specific value. Then, the values of the bytes being the specific value are replaced to the replacing value in the m bytes of each data bock respectively. Afterwards, a starting byte is allocated at the start of each data block, and the replacing value is stored to the starting byte so as to obtain the data block being encoded respectively. Each data block being encoded has m+1 bytes.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: November 30, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yun-Ter Su, Yen-Chen Liu
  • Publication number: 20100295711
    Abstract: A method, apparatus and system employing a 17 B/20 B coder is disclosed. The 17 B/20 B coder to receive an incoming stream including a 17 B block and a 20 B block, and partition the 17 B block into first blocks, and partitioning the 20 B into second blocks. The coder is further to code 17 B to 20 B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17 B block and the second blocks of the 20 B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.
    Type: Application
    Filed: July 30, 2010
    Publication date: November 25, 2010
    Inventors: Seung-Jong LEE, Daeyun SHIM
  • Patent number: 7839309
    Abstract: A physical layer device includes a converter module to convert input data having a first predetermined number of bits into output data having a second predetermined number of bits. A scrambler module is operable to be activated and deactivated. The scrambler module receives the output data having the second predetermined number of bits. An encoding module modulates the output of the scrambler module in accordance with one of a plurality of modulation types and generates an encoded output signal having an output level. The encoding module is operable to vary the output levels of the encoded output signal.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: November 23, 2010
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Xiaopeng Chen
  • Patent number: 7796061
    Abstract: Provided is a distributed decoding device using a multi-core processor, including a multi-core processor that includes a plurality of cores which process data as threads; an MPEG division module that receives MPEG data, extracts decoding information from the MPEG data, divides the MPEG data into individual slices, and generates and provides a single-slice decoding function, which separately decodes one slice, such that threads which decode the divided slices allocated thereto are distributed to the cores within the multi-core processor; a memory that includes a plurality of buffers which receive the slices from the MPEG data division module to store therein and provide the stored slices to the cores of the multi-core processor; and a merging module that merges the data decoded through the cores of the multi-core processor.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: September 14, 2010
    Assignees: DVICO Inc.
    Inventor: Chang-Seo Kee
  • Patent number: 7777652
    Abstract: A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: August 17, 2010
    Assignee: Silicon Image, Inc.
    Inventors: Seung-Jong Lee, Daeyun Shim
  • Patent number: 7746115
    Abstract: A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: June 29, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Chung-Chi Huang, Guang-Dong Yuan, Jian-Chun Pan, De-Jun Zeng, Wei-Min Zhang
  • Patent number: 7719442
    Abstract: A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: May 18, 2010
    Assignee: National Chiao Tung University
    Inventors: Chih-Hao Liu, Chien-Ching Lin, Chen-Yi Lee, Hsie-Chia Chang, Yarsun Hsu
  • Patent number: 7652598
    Abstract: A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: January 26, 2010
    Assignee: Tektronix, Inc.
    Inventors: Shane A. Hazzard, Que Thuy Tran, Kayla R. Klingman, David L. Kelly, Patrick A. Smith, Daniel G. Knierim
  • Patent number: RE41152
    Abstract: An adaptive compression technique which is an improvement to Lempel-Ziv (LZ) compression techniques, both as applied for purposes of reducing required storage space and for reducing the transmission time associated with transferring data from point to point. Pre-filled compression dictionaries are utilized to address the problem with prior Lempel-Ziv techniques in which the compression software starts with an empty compression dictionary, whereby little compression is achieved until the dictionary has been filled with sequences common in the data being compressed. In accordance with the invention, the compression dictionary is pre-filled, prior to the beginning of the data compression, with letter sequences, words and/or phrases frequent in the domain from which the data being compressed is drawn. The letter sequences, words, and/or phrases used in the pre-filled compression dictionary may be determined by statistically sampling text data from the same genre of text.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: February 23, 2010
    Assignee: Pinpoint Incorporated
    Inventors: Jeffrey C. Reynar, Fred Herz, Jason Eisner, Lyle Ungar