Abstract: A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling system. Such a method comprises determining a coding gain for each of a plurality of transition-limiting codes, and selecting one of the plurality of transition-limiting codes having a largest coding gain for use in the multi-level signaling system.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: A data encoding and decoding method capable of lowering signal power spectral density for a binary data transmission system is disclosed. The data encoding method includes receiving binary data, performing adaptive mode tracking encoding for the binary data to generate a first encoding result, performing bit stuffing encoding for the first encoding result to generate a second encoding result, performing bit stationary state resuming encoding for the second encoding result to generate a third encoding result, and outputting the third encoding result.

Abstract: The invention provides a method of encoding a binary data message for transmission over a data network. The method comprises allocating consecutive six bit sequences from the binary data message to consecutive respective bytes of an encoded data message; adding a predetermined bias value to some or all of the byte values of the encoded data message; and replacing respective selected data byte values in the encoded data message with one or more corresponding replacement data byte values. The invention further provides a method that comprises forming two or more message fragments from the binary message, each message fragment comprising respective bit sequences of the binary message; encoding each message fragment by the method outlined above to form two or more encoded message fragments; and adding a header to each encoded message fragment. The invention further provides an encoding engine for encoding a binary data message for transmission over a data network.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: A method of securely storing a data item including obtaining the data item; translating the data item into a first plurality of data blocks using an erasure code associated with a rate; and storing at least a subset of the first plurality of data blocks, where a size of the subset exceeds a product of the rate and a size of the first plurality of data blocks.

Abstract: An apparatus, system, and method are disclosed for communicating binary data using a self-descriptive binary data structure. The binary data structure also may be referred to as a microcode reconstruct and boot (MRB) image. The binary data structure includes a plurality of data segments, a target data set, and a data structure descriptor. Each of the data segments has a data segment header and data field. The target data set is stored within the data field and may be an executable. The data structure descriptor is descriptive of the binary data structure and identifies the location of the target data set within the data field. The binary data structure is self-descriptive in that the location of an individual target data set may be identified by the data structure descriptor.

Abstract: A technique for incorporating binary formatting into a tag-based description language, such as XML, is provided. The binary formatting is achieved by tokenizing the tag and attribute names into variable sized numeric tokens, thereby obviating the need for repetitive or redundant storage of lengthy unicode words, etc. The binary formatting minimizes parsing time and the generation of overhead incident to the formatting and parsing of data. Parsing time is thereby substantially decreased and generally, the size of the resulting file decreases too.

Abstract: It is an object of the present invention to provide coding techniques which allow for higher efficiency and easier synchronization with coded data. In order to attain the object, a coding device according to the present invention converts 2-bit informational data into 4-bit coded data according to a predetermined coding rule. According to the coding rule employed in the coding device, one of four possible kinds of bit strings of informational data is converted into alternately a bit string of four bits in which each of values of two successive bits is “1” and a bit string of four bits in which each of values of all bits is “0”. Then, the other kinds of bit strings are converted into bit strings of four bits which differ from one another, in each of which a value of only one bit is “1”.

Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

Abstract: A string matching system includes a text string, a plurality of patterns, an m-byte search window and a plurality of Bloom filters, wherein the m-byte search window stands for an m-byte sub-string in the text string under inspection. Every Bloom filter comprises sub-strings of a plurality of patterns. These Bloom filters are queried for membership of the rightmost block in the search window to determine the shift length. The acceleration efficiency of matching many bytes can be achieved simultaneously by shifting the search window for many bytes. Meanwhile, the patterns are stored into an embedded memory through a memory-efficient mechanism —the Bloom filter.

Abstract: A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code.

Abstract: The system, apparatus and method of the present invention provides a single carrier block transmission with guard interval as a means of communications over multi-path channels that enables frequency domain equalization, and therefore, has many of the advantages of OFDM, but does not have some of the drawbacks such as high PAPR and the need for high resolution ADCs. While the use of guard intervals in single carrier communications enables low complexity detection of the signal, it reduces bandwidth efficiency. The present invention improves the bandwidth efficiency by adjusting the length of the guard interval adaptively. Also, by allowing both time-domain and frequency domain equalizations, besides improving bandwidth efficiency, the inventions allows for great flexibility in receiver design.

Abstract: A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: Under block-aware encoding, a bitmap represented by atoms comprises a series of bitmaps for each data block in a database. Each bitmap in the series is referred to herein as a block bitmap. Each block bitmap may have a different number of bytes or bits. Gaps are represented in atoms using a pair of numbers referred to as a gap code. A gap code includes a block-skip code and slot-skip code. A block-skip code represents how many block bitmaps to advance to reach a subsequent block bitmap; a slot-skip code represents how many bytes to advance within the block bitmap to reach a byte with at least one bit set. A gap code is represented by bit positions within a byte, with some bit positions allocated to represent the block-skip code and some to represent the slot-skip code. The allocation is adjusted dynamically during encoding and decoding.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: Data is compared with a reference data, which is accessible at a source. The data is then separated into a static part and a dynamic part, wherein the static part is common with the reference data and the dynamic part is not common with the reference data. The dynamic part is transmitted to a destination. At the destination, the dynamic part is merged with the static part, which is obtained from a copy of the data accessible at destination.

Abstract: Information, such as ticket information is encoded, for transmission of the encoded information to a device that can display the encoded information as visible alphanumeric characters. Original information is converted into a binary format then separated into x bit binary words, where x is the same as a maximum number of bits data required by every data character in a pre-determined data character map. The binary words are formed into a sequence of characters using a data character map. Special marker characters are inserted into the sequence. The special characters demarcate the sequence into sets of characters separated by one or more special marker characters. Line feed command characters are also inserted. The encoded information is transmitted to a client device that displays it as a rectangular array of characters bounded by the special marker characters.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: The present invention concerns a method for transcoding a N bits word into a M bits word with M<N. The invention is applicable in various fields and more particularly in the display field. The method comprises the following steps:-breaking down the N bits word into an exponent part and a mantissa part having each a size which varies according to the value of said N bits word, the size of the mantissa part increasing with the value of said N bits word, and -encoding the exponent part of the N bits word into a variable number of bits A and removing, if need be, least significant bits of the mantissa part in order to obtain a mantissa with a variable number of bits B, with A+B=M.

Abstract: Disclosed is a method of digital data conversion. The method includes binding input digital data into unit blocks constituted by a plurality of bytes, modulation-coding each byte of the input data blocks by using a code conversion table, and allocating a merging bit in block unit for the modulation-coded input data in block unit.

Abstract: We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.

Abstract: Methods and systems for generating 10-bit control codes for use in 8-bit to 10-bit encoding are disclosed. Such control codes can have low subblock disparity (where subblocks include 6-bit and 4-bit blocks), limited run lengths when concatenated, limited run lengths within sub-blocks, meet minimal allowable cumulative disparity values at predetermined bit locations (not violate a transition matrix), and not form an aliased comma character sequence within a code, or when codes are concatenated with other codes or encoded data values. Preferably, new codes are added to existing 8B10B schemes with less than sixteen control codes to arrive at a control code set of at least sixteen.

Abstract: A data encoding apparatus extracts valid data to be encoded from received data and encodes the data, and realigns the encoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width. A data decoding apparatus extracts valid data to be decoded from received data and realigns the decoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width.

Abstract: According to one embodiment, when transferring compressed data having information indicating decoding starting time and frame size attached thereto for each frame which is a decoding unit to a decoding processing section, a compressed data transfer apparatus calculates data size which can be transferred to the decoding processing section within time corresponding to a difference between decoding starting time attached to a specified frame and decoding starting time attached to a frame following the specified frame according to the difference between the decoding starting times, performs the control operation to set frame size of the specified frame equal to the calculated data size and rewrites information indicating frame size attached to the specified frame according to data size when the data size is changed.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: Received data is compressed according to an algorithm, which is a modification of the conventional LZW algorithm. A limited number of hash values are formed, and a code memory is searched at locations corresponding to the hash values. If all of the locations contains a valid code, but none of them contains a valid code corresponding to a potential new code, a dummy code is created, and a counter, which indicates the number of codes created, is incremented. The algorithm can be implemented in parallel in hardware.

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract: The method and apparatus use two inequalities to determine whether an estimated value obtained from conventional method and a correct value obtained from ideal conversion is identical. When those values are the same, the estimated value is not corrected; otherwise, according to the difference between those values, one is added or subtracted from the estimated value to obtain the correct result.

Abstract: In accordance with the present invention a method and system for transmitting multibyte characters in a network comprises the steps, performed by a processor, of receiving a set of fixed-length characters; converting each fixed-length character into a multibyte character to determine a length corresponding to the multibyte characters; and transmitting the length and the multibyte characters.

Abstract: How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: Data in a data structure is compressed by exploiting prior knowledge of the format of the data structure. A portion of the data structure is captured. A metadata component is selected for the portion. A data buffer is updated by using the selected metadata component and the captured portion. This compression technique achieves real-time data compression suitable for use with data structures used for the synchronization of the state of communication entities. The compression technique reduces the volume of data to be communicated for the synchronization of the state of communication entities and, therefore, provides faster synchronization. The present technique is suitable for use in redundant systems.

Abstract: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

Abstract: Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.

Abstract: Disclosed is a turbo channel encoding and decoding device for a CDMA communication system. When the input data frames are very short, the device assembles input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding and decoding, the frames are reassembled into the original input frames.

Abstract: A turbo channel encoding/decoding device for a CDMA communication system. The device segments an input frame into multiple sub frames of an appropriate length when the input data frame is very long, and then encodes and decodes the sub frames. Otherwise, when the input data frames are very short, the device composes input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding/decoding, the frames are recomposed into the original input frames.

Abstract: An encoder for enabling selection of output bits that reduce run-length includes classification circuitry, a disparity control circuit, encoding circuitry, and a run-length control circuit. The classification circuitry is configured to receive data in a first bitwidth. An output of the classification circuitry is in communication with the disparity control circuit. The encoding circuitry is configured to encode the data received in the first bitwidth into a second bitwidth. The run-length control circuit is included in the encoding circuit and is selectively triggered in one coding scheme when a contiguous portion of the data of the first bitwidth is of a particular sequence, e.g., all logic ones, to generate a control signal. The run-length control circuit receives as additional inputs outputs of a portion of the encoding circuitry and a disparity signal from the current encoding cycle. The control signal, when generated, reduces run-length of the second bitwidth.

Abstract: Data compression and reconstruction methods and apparatuses for a hard copy device are provided. The data compression method of compressing source image data, which is used for hard copying a bilevel screened image and stored in a memory in units of bytes, for a hard copy device, includes the steps of transposing bytes at each column to bytes at each row in the source image data; and entropy encoding sequential chains, which include a current chain to be compressed and a chain or chains succeeding the current chain, or the current chain depending on whether a chain having the same value as that of the current chain exists in a dictionary composed of previous chains compressed before, and determining the result of the entropy encoding as the result of the compression. Neighboring bytes at each row have neighboring memory addresses. The offset of neighboring bytes at each column corresponds to the row width of the source image data.

Abstract: An apparatus accepts randomly arriving blacks of parallel digital data of varying bit lengths termed datum segments that may have been generated by stripping leading zeros from bytes of a fixed size, each having associated therewith a bit count code that expresses the bit length of each datum segment in the form nnnnndddd . . . , the “n” being the bits of the bit count code in such number as to encompass the memory capacity of a receiving device to which the datum segments are to be sent, and the “d” representing the actual datum segment bits. The apparatus concatenates the nnnnndddd . . . expressions to form a continuous bit sequence that is saved so that each nnnnndddd . . . expression is accessible thereafter through the computer address therefor, such use preferably being by a circuit of matching bit length, the format, however, allowing the original form of the data to be recovered if desired.

Abstract: A picture-encoding apparatus provided by the present invention includes a wavelet transformation unit for carrying out wavelet transformation on an input picture to generate wavelet-transformation coefficients, a bit-plane encoding-pass-generating unit for spreading the wavelet-transformation coefficients over bit-planes, an arithmetic encoding unit for carrying out an arithmetic encoding process in an encoding pass, a rate control unit for controlling an encoded-data quantity of the generated arithmetic code so as to achieve a target encoded-data quantity, a header-generating unit for generating a header, a packet-generating unit for generating a packet by addition of the header to the arithmetic code experiencing control of the encoded-data quantity executed by the rate control unit, and an encoded-code-stream-truncating means for truncating an encoded-code stream completing processing through all the encoding passes by discarding a rear portion of the stream so as to make an encoded-data quantity of the st

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode of data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: The Word-Aligned Hybrid (WAH) bitmap compression method and data structure is a relatively efficient method for searching and performing logical, counting, and pattern location operations upon large datasets. The technique is comprised of a data structure and methods that are optimized for computational efficiency by using the WAH compression method, which typically takes advantage of the target computing system's native word length. WAH is particularly apropos to infrequently varying databases, including those found in the on-line analytical processing (OLAP) industry, due to the increased computational efficiency of the WAH compressed bitmap index. Some commercial database products already include some version of a bitmap index, which could possibly be replaced by the WAH bitmap compression techniques for potentially increased operation speed, as well as increased efficiencies in constructing compressed bitmaps.

Abstract: 8b/10b encoding begins when an input running disparity is received. The processing then continues by receiving an 8-bit digital input that includes a 5-bit digital input portion and a 3-bit digital input portion. The processing then continues by determining, in parallel, a 6-bit running disparity and a 4-bit running disparity. The processing then continues by determining a 6-bit digital output based on the 6-bit running disparity and the 5-bit digital input portion. The processing then continues by determining a 4-bit digital output based on the 4-bit running disparity and the 3-bit digital input portion. The resulting 10-bit encoded digital output is the combination of the 6-bit digital output and the 4-bit digital output.

Abstract: The arrangement has circuits (308) for forming a quantization window to a word, the quantization window being determined to be shorter that the word length, circuits (308) for reducing the word length by cutting the bits remaining outside the quantization window from the word circuits, (312) for determining the amount of saturation caused by the reduction of the word length, and circuits (316) for adjusting the position of the quantization window in the word to be reduced as a function of saturation.

Abstract: Managing a primary bit stream involves converting a qB/rB encoded bit stream to an xB/yB encoded bit stream and multiplexing an additional bit stream with the xB/yB encoded bit stream at a transmission side of a link. The additional bit stream is then demultiplexed from the xB/yB encoded bit stream and the xB/yB encoded bit stream is converted back to the qB/rB encoded bit stream at the receiver side of the link. The qB/rB encoded bit stream is converted to and from the xB/yB encoded bit stream so that the additional bit stream can be multiplexed with the qB/rB encoded bit stream using multiplexing/demultiplexing systems that are compatible with the xB/yB multiplexing system. In an application, a 4B/5B encoded bit stream is converted to an 8B/10B encoded bit stream and an additional bit stream is multiplexed with the 10B code-words of the 8B/10B encoded bit stream using code-word manipulation.