Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Disclosed is a method of processing a digital representation comprising a plurality of cells having respective cell values and being arranged in a regular grid. The method comprises performing at least one cell data reordering operation and performing at least one arithmetic operation for computing at least a first cell value of a first cell from one or more cell values of respective cells of the digital representation, each arithmetic operation including at least one multiplication. The method comprises performing the at least one reordering operation and the at least one arithmetic operation as at least two concurrent processes, each of the concurrent processes reading respective parts of the digital representation from respective memory buffers of a shared memory.

Abstract: A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: A re-fetching cache memory improves efficiency of a system, for example by advantageously sharing the cache memory and/or by increasing performance. When some or all of the cache memory is temporarily used for another purpose, some or all of a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, some or all of the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the temporary use completes, optionally and/or selectively, at least some of the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: In one embodiment, a texture identification method and system are disclosed that uniquely identifies textures as they are used by the application and associates collected, inferred, or user-specified data with objects not owned by the library. In various embodiments, textures may be identified in various scenarios such as when textures are loaded, deleted, relocated, reloaded, and the like.

Abstract: An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: This invention discloses a method and system for implementing transparent multi-buffering in multi-GPU graphics subsystems. The purpose of multi-buffering is to reduce GPU idle time. In one example, after rendering a first image by a first GPU in a back buffer, the first image is displayed by flipping to the back buffer. After that, the front buffer and back buffer are exchanged, and then shifting the back buffer and internal buffers in a predetermined sequence. A second image is rendered to current back buffer by a second GPU. The second image is displayed by flipping to a current back buffer. After that, the front buffer and back buffer are exchanged again, and shifting the back buffer and internal buffers again.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: Method for reversing a video signal having sequences of n elements comprises the steps of writing the n elements of a first sequence into memory locations of a memory in a non-reversed order and reading out the memory locations in a reversed order, and in a subsequent step, writing the n elements of a second sequence into the memory locations in a reversed order and reading out the memory locations in a non-reversed order. The memory locations are readout from the memory in particular one element ahead of the write locations of the memory. A method of this kind can be used in particular in a television camera comprising a lens unit, which is designed for film applications.

Abstract: One embodiment of the invention is a method of accessing a bindable uniform variable bound to a buffer object that includes the steps of creating a linked program object comprising one or more shader programs, where each shader program includes instructions written in a high-level shader language, and where the linked program object includes a reference to a bindable uniform variable and indicates which shader programs use the bindable uniform variable. The method also includes determining a memory size to support the bindable uniform variable, allocating a buffer object having the memory size, binding the buffer object to the bindable uniform variable, populating the buffer object with values for the bindable uniform variable, and accessing the values of the bindable uniform with one or more of the shader programs in the linked program object.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: One embodiment of the invention is a method for accessing and updating data in a buffer object during the execution of a shader program. The method includes loading a plurality of data portions in the buffer object, initiating a first execution of a shader program that accesses a first portion of data in the buffer object, receiving a request to update the first portion of data in the buffer object; updating a version of the first portion of data in the buffer object to reflect the update, initiating a second execution of a shader program that accesses the updated version of the first portion of data in the buffer object, wherein the second execution of the shader program occurs without waiting for the execution of the first shader program to complete.

Abstract: Three dimensional scenes may be managed between a central processing unit and a graphics processing unit using shared and unified graphics processing unit memory. A shared bus memory may be synchronized between the central processing unit and the graphics processing unit. The shared bus memory may be used for more often updated components and other memory may be used for less often updated components. In some embodiments, if the graphics processor and the central processor use a common processor instruction set architecture, data can be sent from the central processor to the graphics processor without serializing the data.

Abstract: An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.

Abstract: An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit.

Abstract: In each odd-numbered frame, a game image generated by a three-dimensional image processing unit 31 is supplied to a first LCD 11, and then a game image identical to the generated game image is stored in a first VRAM 21a. Also, a two-dimensional image processing unit 37 supplies the game image stored in the immediately-preceding even-numbered frame in a second VRAM 21b to a second LCD 12. On the other hand, in each even-numbered frame, a game image generated by the three-dimensional image processing unit 31 is supplied to the first LCD 12, and then a game image identical to the generated game image is stored in the second VRAM 21b. Also, the two-dimensional image processing unit 37 supplies the game image stored in the immediately-preceding odd-numbered frame in the first VRAM 21a to the first LCD 11.

Abstract: A data processing system may include a display, the display having a display surface, and logic to modify the address signals of a graphics processing unit (GPU) if the address signals do not fall within a two-dimensional range of authorized pixel locations corresponding to a subset of the display surface, and to propagate the address signals unmodified to a display memory otherwise.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A motion desktop, including a moving image, may be presented on a display screen of a processing device. Foreground items such as, for example, icons and associated text, or other information, may appear on a surface of the motion desktop. In embodiments consistent with the subject matter of this disclosure, foreground content may be rendered to a composing surface, which may be an alpha-enabled surface capable of presenting translucent items. A motion desktop module may render content for at least a portion of a background of the motion desktop to a respective shared memory, shared with a composer. The composer may periodically copy the rendered content from the shared memory to the composing surface, where the composer may compose and blend a scene from background and foreground content. The composed scene may then be presented as the motion desktop.

Abstract: Methods, apparatuses, and systems are presented for performing multiple concurrent accesses in a shared memory resource comprising storing a first group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the first group being stored in a data entry in a first bank; skipping at least one data entry in at least one bank after storing a last data element of the first group, to introduce an offset; following the offset, storing a second group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the second group being stored in a data entry in a second bank different from the first bank; and concurrently accessing the first data element of the first group from the first bank and the first data element of the second group from the second bank.

Abstract: A system and method for facilitating access to graphics memory wherein the graphics memory can be shared between a graphics processor and general system application. The method includes detecting an idle state of a graphics processing unit (GPU). The GPU uses graphics memory operable for storing graphics data. The method further includes determining an amount of available memory of the graphics memory of the GPU and signaling an operating system regarding the available memory. Memory data transfers are then received to store data into the available memory of the graphics memory wherein the data is related to general system application. Memory accesses to the available memory of the GPU are translated into a suitable format and executed so that the graphics memory is shared between the GPU and the operating system.

Abstract: In one embodiment of the present invention, a system for displaying images in at least one display window on a display unit includes a display processor configured to generate graphics commands from a received input. A graphics processing unit is coupled to the display processor and includes rendering engine configured to generate graphic data from the graphics commands, an internal memory coupled to the rendering engine, and a general purpose I/O coupled to the rendering engine and configured to transmit messages from the graphics processing unit. A graphics logic device is coupled to the graphics processing unit. The graphics logic device is configured to initiate a transfer of graphic data for an update of a display window from the internal memory to the display unit upon receipt of a message indicative of an available update to the display window.

Abstract: An image forming apparatus includes a plurality of hardware resources provided to carry out image formation. A plurality of application programs perform respective processing of the plurality of hardware resources related to the image formation. A storage device stores rewritable shared data which is used by the application programs in common. A shared-data control unit suspends one of a write-lock request or a read-lock request that is received from one of the application programs when acquisition and/or updating of the shared data is inhibited, and after the acquisition and/or updating of the shared data is allowed, inhibits the acquisition and/or updating of the shared data by other application programs in accordance with the suspended request for the one of the plurality of application programs.

Abstract: A method for recording a plurality of graphic objects is disclosed. Each graphic object includes at least one common parameter and at least one object data. The method includes recording the at least one common parameter corresponding to the plurality of graphic objects in a common parameter section; and respectively recording the at least one object data of the plurality of graphic objects in corresponding object sections; wherein the at least one common parameter and the at least one object data are utilized to describe characteristics of the graphic objects.

Abstract: A data processing system can establish or maintain data coherency by issuing a data flush operation. The data processing system can be configured as a host executing one or more independent processes using one or more lower level devices. The lower level devices can be viewed as peer devices. Any of the host or the plurality of peer devices can be configured to initiate the flush operation. A device can determine whether the initiator of a flush operation is the host or a peer device. The device can perform a flush limited to local memory, or a subset of all available memory, if a peer device initiates the flush operation.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

Abstract: The present invention provides an improved technique for communicating between a central processing unit and a graphics processing unit of a data processing apparatus. Shared memory is provided which is accessible by the central processing unit and the graphics processing unit, and via which data structures are shareable between the central processing unit and the graphics processing unit. A bus is also provided via which the central processing unit, graphics processing unit and shared memory communicate. In accordance with a first mechanism of controlling the graphics processing unit, the central processing unit routes control signals via the bus. However, in addition, an interface is provided between the central processing unit and the graphics processing unit, and in accordance with an additional mechanism for controlling the graphics processing unit, the central processing unit provides control signals over the interface.

Abstract: A system and method to manage data processing stages of a logical graphics pipeline comprises a number of execution blocks coupled together and to a global spreader that assigns graphics data entities for execution to the execution blocks. Each execution block has an entity descriptor table containing information about an assigned graphics data entity corresponding to allocation of the entity and a current processing stage associated with the entity. Each execution block includes a stage parser configured to establish pointers for the assigned graphics data entity to be processed on a next processing stage. A numerical processing unit is included and configured to execute floating point and integer instructions in association with the assigned graphics data entity. The execution blocks include a data move unit for data loads and moves within the execution block, with the global spreader, and with other execution blocks of the plurality of execution blocks.

Abstract: A method is provided for producing three-dimensional (3D) models. The invention will take any sculpture, character, or model from artwork, still life models, images of human beings, characters from a computer game, or any other 3D digital image or model that is scanned, and turn the digital image into 3D models. The method is comprised of the following steps: creating a user account in a computer storage area; storing 3D images under the user account; allowing the user to select the 3D image(s) he or she wants to create as 3D models; manufacturing the 3D models; and delivering the models to the user or to a specified third-party. An online storefront and/or auction system may allow each user the opportunity to sell their 3D models or purchase other users' 3D models. The system may also create 3D models for a mobile phone and portable media player while transferring the models to either of these devices.

Abstract: A display of CPU utilization in a multiprocessor system is provided. This feature illustrates processor utilization and application group assignments to CPUs and clusters of CPUs. Various graphic indicator are described that can be used to display processor utilization and indicate processors that have no application group assignments. For example, bar graphs as well as gauge displays can be used to visually convey processor utilization. As a result, a user can visually determine the processor utilization and application group assignments across a multiprocessor system. Additionally, various colors and shadings can be used to visually convey application group assignments.

Abstract: The client terminal according to the present invention is connected to a server and comprises a display unit and an input unit of a virtual computer executed by software on the server, includes a storage unit which stores dump data of the client terminal, an information acquisition unit which acquires network information on transmission and reception between the server and the client terminal and stores it in the storage unit, and a dump control unit which instructs the server to acquire dump data of the virtual computer in response to a predetermined operation to the input unit, and transmits the dump data and the network information that are stored in the storage unit to the server.

Abstract: A method of managing multiple contexts for a single mode display includes receiving a plurality of tasks from one or more applications and determining respective contexts for each task, each context having a range of memory addresses. The method also includes selecting one context for output to the single mode display and loading the selected context into a graphics processor for the display.

Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Abstract: A monitor having multiple displays within the same housing. The displays may be, for example, separate LCD panels that are placed in close proximity to one another so as to give the appearance of a single, large display. At least two of the displays may be treated by a computer connected to the monitor as a single display. A display controller divides a single frame of information that is provided by a display adapter of the computer into display information for multiple displays. By using the multiple display controller, the multiple display monitor may have more displays or panels than the number of cables linking the monitor to a computer. The special display controller also does not require a graphics card for each display. A three panel or display monitor is provided in which a central, centered work area display is framed by two side panels or displays.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: A system and method for efficiently linking together replicas of a storage object. The location of a first replica of the storage object may be stored on a node in a network. When new replicas of the storage object are created, the node that stores the new replica may efficiently lookup the location of the first replica and utilize the location information to perform an efficient process to link the new replica to the first replica and any other existing replicas by causing routing information to be created on various nodes.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A multiprocessor system in which a CPU (100) and a GPU (200) are interconnected via an IOIF (110) is provided. A main memory (120) is installed on the CPU (100) side and a local memory (220) is installed in the GPU (200) side. The CPU (100) queues a graphics command generated with a graphics library (300) by an application (310) to a command buffer (10) in the main memory (120). The GPU (200) reads and executes the graphics command stored in the command buffer (10). The area of the main memory (120) is memory-mapped in an I/O address space. The GPU (200) reads data memory-mapped in the I/O address space via the IOIF (110) and uses it for graphics operation.

Abstract: A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: An image forming apparatus and a method of acquiring a memory area are disclosed for preventing a problem that image data cannot be converted due to failure of memory acquisition. The image forming apparatus includes an image data conversion part, a resource management part and an image data management part. The image data conversion part has at least one conversion function to convert a format of image data. The resource management part determines a memory size required for a conversion function to convert the format of the image data. The image data management part acquires a memory area corresponding to the determined memory size.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

Abstract: Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.

Abstract: Some embodiments of the invention provide a method for presenting computer-generated characters. The method defines several frames for a character and sequentially presents the frames. Each frame depicts a particular representation of the character. Also, at least two of the frames provide different representations of the character. Some embodiments provide a method for applying effects to computer-generated characters. This method applies an effect to the computer-generated characters by first generating an effect script. It then selects the generated effect script to apply to the computer-generated characters.

Abstract: A device for processing video and graphics data includes a component and a main random access memory containing video and graphics data. The component includes a processing unit, and a two-dimensional acceleration unit cooperating with the processing unit and the main random access memory to compose in real time images. The images include at least one video plane and at least one graphics plane, and are stored in the main random access memory. An output interface extracts the image data thus composed from the main random access memory for delivery to an image display.