Abstract: A method and an apparatus for updating graphics resource usage according to a stream of graphics commands atomically submitted to a graphics processing unit (GPU) are described. The stream of graphics commands may be received from a plurality of graphics APIs (application programming interfaces) by a graphics driver. Availability of graphics resources of the GPU may be monitored by the graphics driver for submitting the stream of graphics commands. A single notification from the GPU may indicate that all graphics commands submitted to the GPU have been executed for updating a usage of graphics resources associated with the executed graphics commands.

Abstract: A computing device has a graphics hardware device employed to display graphics on a display, and is partitioned to include a video services partition (VSP) instantiated at least in part to provide graphics capabilities, and also to include a video client partition (VCP) instantiated at least in part to consume such graphics capabilities. The graphics hardware device is assigned to and controlled by the VSP. A shared video memory module is shared by the VCP and the VSP such that graphics information placed in the pages shared by the video memory module by the VCP is directly available to the VSP for further action such that graphics commands from the VCP are shunted by way of the pages shared by the video memory module across partitions from the VCP to the VSP to be acted upon by the graphics hardware device as controlled by the VSP.

Abstract: A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.

Abstract: First and second areas are designated in a source picture. A start picture is generated from a portion of the source picture which extends in the first area. An end picture is generated from a portion of the source picture which extends in the second area. At least one third area is designated in the source picture. The third area extends between the first and second areas. An intermediate picture is generated from a portion of the source picture which extends in the third area. An image file of a prescribed format is generated which contains data representative of animation pictures including the start picture, the intermediate picture, and the end picture. The image file is related with an audio file containing data representative of audio information. A file group including the image file and the audio file is generated. The file group is recorded on a recording medium.

Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

Abstract: An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first, second and third internal memory communicating with the first, second and third data port interface. A first and second memory management unit for communicating data and to control access to and from the second internal memory, are also provided. A communication channel is provided for communicating data and messaging information.

Abstract: A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Abstract: The present invention relates to a device for digital display of a video image using time-division modulation. This device is intended to display a video image during a video frame comprising a plurality of consecutive subfields distributed within at least two separate identical time segments. According to the invention, the pixels of the video image change state at most once during each time segment and the video image to be displayed is saved in the image memory in the form of information identifying, for each subfield, the pixels changing state.

Abstract: A system and method for cache optimized data formatting is presented. A processor generates images by calculating a plurality of image point values using height data, color data, and normal data. Normal data is computed for a particular image point using pixel data adjacent to the image point. The computed normalized data, along with corresponding height data and color data, are included in a limited space data stream and sent to a processor to generate an image. The normalized data may be computed using adjacent pixel data at any time prior to inserting the normalized data in the limited space data stream.

Abstract: When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.

Abstract: A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory. A central processing unit (CPU) receives a first graphics program module that outputs a first parameter referenced by a first graphics program module identifier, a second graphics program module that inputs the first parameter by referencing the first graphics program module identifier, and a first data structure that includes, in a pre-defined order, a list of first data structure identifiers. The CPU identifies a memory location in the shared memory, based on the pre-defined order of the first data structure identifiers, for one of the first data structure identifiers that is the same as the first graphics program module identifier. The CPU modifies the first and second graphics program modules to reference the first parameter by the identified memory location in the shared memory.

Abstract: A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles.

Abstract: A method, data processing system, and computer instructions for simulating direct frame buffer access. A request for access to a frame buffer memory is received from an application. A portion of system memory is allocated for use as the frame buffer memory in response to receiving the request. A pointer to the portion of system memory is returned to the application. The application writes data to the portion of system memory, treating the portion of system memory like the frame buffer memory.

Abstract: Apparatus, system, and method for delivering data to multiple memory clients are described. In one embodiment, a graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the set of memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a unitary buffer and a buffer controller connected to the unitary buffer. The buffer controller is configured to coordinate storage of the data in the unitary buffer, and the buffer controller is configured to coordinate delivery of the data from the unitary buffer to respective ones of the set of memory clients.

Abstract: A controller-driver, a method of driving the controller-driver, and a method of processing image data enabling scroll or other various functions without adding a storage capacity of a display memory nor increasing power consumption. A built-in display memory having a capacity of one frame (H pixels×V pixels×the number of bits) is partitioned into a plurality of memories according to an image type. High order bits are then stored in a first display memory 7a and high order bits of the next frame or low order bits are stored in a second display memory 7b by using a first selector 8 to a third selector 10 controlled by a memory control circuit 6 before they are read out. Thereby, high-level image data of one frame can be displayed when the scroll function is not used and image data of a plurality of frames can be displayed without accessing an image drawing unit 1 when the scroll function is used, thereby reducing power consumption.

Abstract: Some embodiments of the invention provide a method for presenting computer-generated characters. The method defines several frames for a character and sequentially presents the frames. Each frame depicts a particular representation of the character. Also, at least two of the frames provide different representations of the character. Some embodiments provide a method for applying effects to computer-generated characters. This method applies an effect to the computer-generated characters by first generating an effect script. It then selects the generated effect script to apply to the computer-generated characters.

Abstract: In accordance with the invention, a video source is received by a first video adapter. The video source is captured in the video memory associated with the first VGA. The stored video source is associated with a window of an existing application. When the window location of the existing application is shifted to coincide with the video memory of a second graphics adapter, a data transfer occurs to the appropriate video memory location of the second graphics adapter to allow the rendering of that portion of the video now residing on a second monitor.

Abstract: A method and apparatus for eliminating artifacts in images formed using more than one image segment. A buffer region associated with two adjacent image segments is defined wherein the intensity levels of the pixels are attenuated. When image segments substantially overlap in the buffer region, the intensity in the buffer region substantially sums to full scale. The intensity of the pixels in the buffer region is preferably attenuated using a device to modulate the intensity of the source of radiation.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: Local memory associated with one or more companion devices within a system is mapped into a system memory for use by an application processor.

Abstract: The invention includes a parallel processor. The parallel processor includes a plurality of non-volatile memory cells. The parallel processor additionally includes a plurality of processor elements. At least one non-volatile memory cell corresponds with each of the processor elements. The processor elements each access data from at least one corresponding non-volatile memory cell. The processor elements perform processing on the data. The non-volatile memory cells can include magnetic memory cells.

Abstract: A memory model for a run-time environment is disclosed that includes a process-specific area of memory where objects in call-specific area of memory and session-specific area of memory can be migrated to at the end of a database call. User-specific objects can be then migrated to the session-specific area of memory. In one embodiment, the process-specific area of memory can be saved in a disk file and used to hot start another instance of an application server.

Abstract: A visualization console acquires a 3D data set representing a 3D scene. The visualization console then transfers at least some of the 3D objects within the 3D scene to a pool of workstations. The collection of workstations associates an identifier with each of the 3D objects, and manages the storage of these 3D objects. Sometime later, the visualization console sends a request to the pool of workstations for the data needed to render a 3D object contained in the workstation. The workstations perform multiresolution modeling computation and create a different set of models with the appropriate level of detail for the 3D object identified by the request. The workstations then send the mesh representation of the 3D objects requested to the visualization console for display. The visualization console will thus be able to render these models more efficiently than prior systems that either render the complete 3D scene or perform multiresolution computation by themselves.

Abstract: A content recording apparatus that writes, when a recording instruction is issued, into a first area of a recording medium predetermined information indicating a predetermined value, records into a plurality of partial areas sporadically distributing in a second area of the recording medium a content to which a plurality of markers are assigned in a predetermined manner, and after completing recording the content, writes into a third area of the recording medium link information indicative of a link state among partial areas in which the content is recorded, and updates a value indicated by the predetermined information written in the first area, includes: a predetermined information detector for detecting the latest predetermined information out of the predetermined information written in the first area when a driving power is input; an area detector for detecting from the second area partial areas in a non-link state based on the link information written in the third area when the predetermined information

Abstract: A communication method apparatus are disclosed, including a common bus; a plurality of multiplexers that communicate with the common bus; a plurality of memories, each in communication with a separate one of the plurality of multiplexers and each having a different storage capacity, that together form a hierarchical storage structure; a bus arbiter that controls access to the common bus; a first interface that communicates information with the common bus; and a second interface that communicates information with the common bus.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: In general, and in a form of the present invention, a method is provided for reducing execution time of a program executed on a digital system by improving hit rate in a cache of the digital system. This is done by determining cache performance during execution of the program over a period of time as a function of address locality, and then identifying occurrences of cache conflict between two program modules. One of the conflicting program modules is then relocated so that cache conflict is eliminated or at least reduced. In one embodiment of the invention, a 2D plot of cache operation is provided as a function of address versus time for the period of time. A set of cache misses having temporal locality and spatial locality is identified as a horizontally arranged grouping of pixels at a certain address locality having a selected color indicative of a cache miss.

Abstract: An overdrive system for driving a display device. A host machine includes a display interface for connecting with the display device. The display interface includes a display chip and a video memory. The overdrive system includes a frame buffer for holding the display data of the previous frame. The frame buffer uses a portion of the video memory space. The overdrive system also includes an overdrive look-up table coupled to the display chip to provide a correspondence between the overdrive display data, the display data of the previous frame and the display data of the present frame. The display chip retrieves overdrive display data from the overdrive look-up table according to the display data of the previous frame obtained from the frame buffer and the display data of the present frame and transmits the overdrive display data to the display device so that an image is formed on the display panel.

Abstract: A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.

Abstract: A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.

Abstract: A method and system according to the present invention provide for sharing memory between applications running on one or more CPUs, and acceleration co-processors, such as graphics processors, of a computer system in which the memory may retain its optimal caching and access attributes favorable to the maximum performance of both CPU and graphics processor. The method involves a division of ownership within which the shared memory is made coherent with respect to the previous owner, prior to handing placing the shared memory in the view the next owner. This arbitration may involve interfaces within which ownership is transitioned from one client to another. Within such transition of ownership the memory may be changed from one view to another by actively altering the processor caching attributes of the shared memory as well as via the use of processor low-level cache control instructions, and/or graphics processor render flush algorithms which serve to enforce data coherency.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: Disclosed is an image signal processor for use in an image processing system. The image signal processor includes a local memory to store data and a memory command handler having a plurality of memory address generators. Each memory address generator generates a memory address to the local memory and interprets a command to perform an operation on the data of the local memory located at the memory address to aid in image processing tasks.

Abstract: A broadcast video signal of a broadcast program is stored. A predetermined feature portion of each of frames in a broadcast video signal of a music program is detected from the stored broadcast video signal. A frame section serving as a music section in which a display mode of the predetermined feature portion is stable and music is continuously included, is detected from the broadcast video signal in the music program as a performance scene. A video signal representing an image concerning the detected performance scene is created and output as the menu.

Abstract: A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: Processing video data with a combination of one or more operations, such as special effects, on a general-purpose computer may be improved by enabling one or more operations to access and process multiple samples of video data from other operations that introduce latencies for each request for data. Operations that introduce latencies include, for example, hardware for decompression and compression, network interfaces, and file systems. Because a computer program to implement the operations may be executed on several different general-purpose platforms, exact specifications of available hardware are not known in advance. For each operation, a computer program determines the available system memory and an amount of data that can be processed by each operation used in a composition or portion of a composition while sharing the available memory with other operations. Available system memory is allocated among the operations being used.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.

Abstract: A internal data display apparatus for a machine tool is provided, which includes a computerized numerical controller (CNC ) being provided with an internal common memory in which internal data is stored; a shared-memory routine module configured to share said internal common memory of said CNC and to receive data from said internal common memory; a hot-link routine module configured to receive data from said shared-memory routine module and to process said received data; a data-view routine module configured to receive data from said hot-link routine module and to display said processed data; a shared-memory data-view file including information on a common memory from which the internal data will be read; and a display data-view file including information on which data of data stored in said shared memory is displayed.