Abstract: An image processing apparatus is composed of a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on the predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts, each of the data holding parts holding a predetermined amount of data transmitted with each of the plurality of function processing units, wherein the data transfer part controls the bus connecting the CPU and the shared memory based on requirement sent from each of the function processing units, and each of the plurality of function processing units transmits data with the data control unit separately from the others of the plurality of function proces

Abstract: A method for accessing image data is used in a computer system. The computer system includes a core logic unit, a system memory, a graphics accelerator, and an image data outputting device in communication with a south bridge chip of the core logic unit. The method comprises the following steps. Firstly, image data are received from the image data outputting device by the core logic unit. Then, the image data are written into an AGP memory block of the system memory. Afterwards, the image data are accessed in the AGP memory block by the graphics accelerator.

Abstract: A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory management process can be locked down.

Abstract: A computer system which includes at least one host CPU; at least two separate rasterizer units, interconnected to process at least some graphics rendering tasks jointly; and a shared graphics memory manager which sends requested data to both said rasterizers simultaneously.

Abstract: An image forming apparatus, which reads an image of a document and forms the same image, including a display, a input means to be receive an input data, a ROM to store initial display data of the input means and compressed programs, a power source detecting circuit to detect that the power is ON and a CPU to read initial display data of the input means stored in a ROM and control the display of initial display data on the display of the control panel.

Abstract: A method and system according to the present invention provide for sharing memory between applications running on one or more CPUs, and acceleration co-processors, such as graphics processors, of a computer system in which the memory may retain its optimal caching and access attributes favorable to the maximum performance of both CPU and graphics processor. The method involves a division of ownership within which the shared memory is made coherent with respect to the previous owner, prior to handing placing the shared memory in the view the next owner. This arbitration may involve interfaces within which ownership is transitioned from one client to another. Within such transition of ownership the memory may be changed from one view to another by actively altering the processor caching attributes of the shared memory as well as via the use of processor low-level cache control instructions, and/or graphics processor render flush algorithms which serve to enforce data coherency.

Abstract: A system and method for asynchronously processing video images are provided. A video processing computing device includes one or more video capture boards in communication with a number of image capture devices, such as video cameras. The video image processing computing device includes a video collection application that is operable to instruct the video capture board to acquire video data and store the data in a shared memory area. The video processing computing device also includes a video processing application that is operable to acquire the stored video from the shared memory area and process the video data. By utilizing a shared memory area, the video collection application and the video processing application can process data asynchronously.

Abstract: A method for displaying color values in a plurality of images on a display screen in a computer graphics system, wherein the images correspond to a plurality of applications. The graphics system includes a primary frame buffer for pixel values to be displayed in the images, and a plurality of colormap tables related to the images for providing color values to be displayed in the images. A pseudo frame buffer is provided for the applications to store source pixel values for display in the corresponding images. To display the source pixel values in the pseudo frame buffer, for each source pixel the graphics system performs the steps of: identifying the image corresponding to the source pixel value; selecting a colormap table corresponding to the identified image; using the source pixel value as an index to select a color value from the selected colormap table; and storing the selected color value as a pixel value in the primary frame buffer to be displayed.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: A hardware-based graphics controller for processing video data in a computer system. Such graphics controller may include a video capture engine which captures fields of video data from a video source for storage in video buffers in sequential order, and generates video capture parameters from the video data for determining proper flipping operations of display contents of one image to another on a display monitor; and a video overlay engine coupled to the video capture engine, which determines proper flipping operations of display contents of one image to another from the video buffers and adjusts display settings of the display contents for a visual display on the display monitor based on the video capture parameters from the video capture engine.

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: A method and system for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, in a 3D graphics system having privatized formats with privatized drivers used to increase the efficiency of display, existing problems are eliminated that are associated with multiple redundant copies of the publicly formatted graphics data made in host system memory pursuant to various graphics operations e.g., lock and unlock operations. The ability to make a system copy of publicly formatted data is exposed to the developer, eliminating the creation of unnecessary, and redundant copies. Efficient switching between the privatized and public format remains hidden from the developers so that applications execute efficiently while removing consideration thereof from the developers. Thus, developers are free to consider other tasks.

Abstract: A computer system having a graphics display with texture management employs a graphics adapter with texture memory. The graphics adapter is ‘virtualized’ by the operating system. When making a graphics context switch, the state of the graphics adapter including texture memory is saved. Threads are used to allow rapid and frequent context switches. A graphics process that will use texture memory in the adapter reserves a thread, for use during a graphics context switch. The thread calls into the operating system where it is blocked until a graphics context switch is initiated. At that time, the thread is unblocked to do texture management, such as saving of texture memory. During the save portion of the graphics context switch the graphics driver saves the current hardware state of the adapter, and the special purpose texture thread is unblocked to allow texture memory to be processed, and saves texture memory and calls back into the driver where it is blocked.

Abstract: An image processing apparatus is composed of a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on the predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts, each of the data holding parts holding a predetermined amount of data transmitted with each of the plurality of function processing units, wherein the data transfer part controls the bus connecting the CPU and the shared memory based on requirement sent from each of the function processing units, and each of the plurality of function processing units transmits data with the data control unit separately from the others of the plurality of function proces

Abstract: A system for connecting a video object to various multimedia objects to enable an object-oriented simulation of a multimedia presentation using a computer with a storage and a display. A plurality of multimedia objects are created on the display including at least one connection object and at least one video object in the storage. Multimedia objects are displayed on the display, including at least one video object. The multimedia object and the video object are connected, and information is routed via the connection between the multimedia object and the video object to create a multimedia presentation.

Abstract: A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits.

Abstract: A low cost high performance three dimensional (3D) graphics system can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation for example) on the screen of a color television set. The richly featured high performance low cost system gives consumers the chance to interact in real time inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU, the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU bus which is held by the memory. When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller.

Abstract: A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors.

Abstract: A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits. Alternatively, the address control can reflect the different processing priority of different types of data. The processing circuits may be image data I/O means, audio data processing means, encoding/decoding means, error correction means and encoded data I/O means.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: Single Logical Screen and Direct Hardware Access in a 3D environment are combined by passing a single stream of protocol to the X Server, which in turn passes the information to multiple 3D rendering processes for display on individual screens (monitors). Multiple instances of a single daemon implement the rendering processes. The X Server communicates with an instance of the daemon functioning as a master daemon, which in turn controls the remaining instances functioning as slave daemons. All daemons communicate through common shared memory segments. This achieves both efficiency and performance, since duplicated distribution of commands and data is avoided. Each of the daemons is driven by the contents of the shared memory segments. To facilitate this, an X Client, the X Server and the daemons are all interconnected with separate control and data paths.