Abstract: Read completion buffer space is allocated in accordance with a preset limit. When a read request is received from a client, the sum of a current allocation of the read completion buffer space and a new allocation of the read completion buffer space required by the read request is compared with the preset limit. If the preset limit is not exceeded, read completion buffer space is allocated to the read request. If the preset limit is exceeded, the read request is suspended until sufficient data is read out from the read completion buffer.

Abstract: A memory management system for managing memory of a processing device and a corresponding method thereof. The system comprises a memory manager and a garbage collector. The memory manager is configured to allocate memory after dividing discrete units of memory into smaller units. The garbage collector is configured to organize a memory availability collection of free units of memory in the memory manager. The collection is ordered based on at least one of the amount of each of the discrete units available and the allocation age of the discrete units.

Abstract: A memory allocation method and terminal for supporting Direct Memory Access (DMA) are provided. The terminal includes a memory for storing data used for operations of the terminal, a plurality of devices for executing applications for specific functions, a control unit for defining, when the terminal boots up, a virtual zone dedicated for the DMA in the memory, and a DMA unit for controlling the DMA of the devices.

Abstract: An interface apparatus and a method of writing an extended display identification data (EDID) are provided. The interface apparatus includes a data processing unit, a memory unit and a switching unit. The memory unit is coupled to a connector corresponding to the memory unit and the data processing unit via the switching unit. When the interface apparatus is being initialized, the data processing unit detects whether or not the EDID stored in the memory unit is correct. If the EDID stored in the memory unit is incorrect, the data processing unit rewrites the EDID to the memory unit.

Abstract: A self-emission type display device is disclosed. A current comparator circuit (47) in a data line drive circuit having a current compensating function (2) detects only the result of size comparison between the current amount due to the degeneration of a self-emission element and a reference value. The reduction of the current amount below the reference value is stored by being added to the least significant bits of a display data storage circuit (30). In accordance with the display data read from the storage circuit (30), a D/A conversion circuit (41) generates a write signal voltage.

Abstract: An image processing apparatus processes compression encoded data of a moving picture and outputs image data divided into a plurality of frames for displaying of the moving picture on a display device. A host CPU outputs a decoding command and a drawing command separately from each other. The decoding process on the compression encoded data can be performed in an independent manner from the drawing process of reflecting the image data, which are the decoding results, on the display object. At this time, a display control section executes the drawing process based on the image data stored in a ring buffer in accordance with the drawing command. Therefore, the host CPU can freely control timings at which the moving pictures are displayed on the display device.

Abstract: In general, aspects of this disclosure describe example techniques for efficient storage of data of various data types for graphics processing. In some examples, a processing unit may assign first and second contiguous range of addresses for a first and second data type, respectively. The processing unit may store at least one of graphics data of the first or second data type or addresses of the graphics data of the first or second data type within blocks whose addresses are within the first and second contiguous range of addresses, respectively. The processing unit may store, in cache lines of a cache, the graphics data of the first data type, and the graphics data of the second data type.

Abstract: Methods and systems are provided for geometry-based virtual memory management. The methods and systems use Boolean space algebra operations to manage allocation and deallocation of tiled virtual memory pages in a tiled virtual memory provided by a tiled virtual memory subsystem. A region quadtree may be maintained representing a current allocation state of tiled virtual memory pages within a container. The region quadtree may be used to locate a rectangle or two dimensional (2D) array of unallocated tiled virtual memory pages, and physical memory pages may be mapped to tiled virtual memory pages in the rectangle by updating a lookup table used to translate tiled virtual memory page addresses to physical memory page addresses. A union or intersection of region quadtrees may be performed to generate a new region quadtree representing a new current allocation state of the tiled virtual memory pages.

Abstract: Disclosed is an edge management unit of accessing a memory including a first memory area and a second memory area. The edge management unit comprises an edge write controller writing bucket information corresponding to input edge data in the first memory area and the edge data at a location of the second memory area appointed by the bucket information; and an edge read controller responding to a scan line signal to read the bucket information from the first memory area and the edge data from a location of the second memory area appointed by the read bucket information.

Abstract: A method and an apparatus for maintaining separate information for graphics commands that have been sent to a graphics processing unit (GPU) and for graphics commands that have been processed by the GPU are described. The graphics commands may be associated with graphics resources. A manner to respond to a request for updating the graphics resources may be determined based on examining the separate information maintained for the graphics commands. The request may be received from a graphics API (application programming interface). Responding to the request may include at least one of notifying the graphics API regarding a status of the graphics resources and updating the graphics resources identified by the request.

Abstract: Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.

Abstract: A non-volatile storage medium storing a control program readable by a computer of a portable device including a sensor to output detected information indicative of at least one of a movement and an attitude of the portable device, a data memory portion to store image data, and a display portion to display an image on the basis of the image data, wherein the control program enables the computer to function as: a partial area specifying portion to specify, as a partial image area, an area of a partial image that is a portion of the image represented by the image data, on the basis of at least one of the movement and attitude of the portable device indicated by the detected information; and a display control portion to display the partial image in the partial image area specified by the partial area specifying portion, on the display portion.

Abstract: It is determined whether the rasterization result of a rendering object is cashed. If it is determined that the rasterization result of the rendering object is not cashed, an image and a mask for the image are generated from the rendering object. The generated image and the generated mask are stored in a cache. If it is determined that the rasterization result of the rendering object is cached, an image and a mask are extracted from the cache. The extracted image is rendered on a portion of the extracted mask so that a background image remains on a portion other than the portion of the extracted mask.

Abstract: A system for dynamically binding and unbinding of graphics processing unit GPU applications, the system includes a memory management for tracking memory of a GPU used by an application, and a source-to-source compiler for identifying nested structures allocated on the GPU so that the virtual memory management can track these nested structures, and identifying all instances where nested structures on the GPU are modified inside kernels.

Abstract: An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.

Abstract: A system and method for remapping and redirecting accesses to a memory space shared between graphics devices permits a single device driver to interface between an application program and multiple graphics devices. Each graphics device provides configuration information to the BIOS (basic input/output system), particularly memory space requirements for prefetchable and non-prefetchable memory spaces. A memory space allocation for the graphics devices is determined based on the configuration information. A switch device, interfacing between a host processor and each graphics device, is programmed to redirect accesses to a portion of the allocated memory space to only one of the graphics devices. Accesses to another portion of the allocated memory space may be remapped to all of the graphics devices or a subset of the graphics devices.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: A computer system that initializes a fraction of the computer system's memory for execution of video during booting of the computer system is provided. The computer system can include a first portion of BIOS code on a ROM device, wherein the first portion includes instructions for initializing the fraction. The computer system further can include a second portion of BIOS code that copies itself to the fraction upon completion of initialization of the fraction, wherein the second portion executes on the fraction and wherein the second portion initializes system memory and initializes a video buffer. The computer system further can include a copy of the second portion located on the ROM device, wherein the copy of the second portion executes until video buffer initialization is completed but before all of the system memory is initialized. Further, the video buffer displays video before all of the computer system's memory is initialized.

Abstract: A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.

Abstract: Among other disclosure, a computer-implemented method for retaining a surface detail includes identifying a surface that is to be used for generating an image in a rendering process. The surface includes polygons to be changed from an initial size to a larger size as the surface is changed to a lower resolution as part of tessellating the surface. The surface includes at least one surface detail smaller than the larger polygon size. The method includes storing information corresponding to at least a portion of the surface that includes polygons forming the surface detail. The method includes tesselating the surface, wherein the surface assumes the lower resolution. The method includes determining, while the image is at the lower resolution and using the stored information, a shading sample for at least one of the polygons of the larger size that includes the surface detail. The method includes storing the shading sample.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

Abstract: This is a computer-readable portable storage medium which is used by a computer managing a plurality of frame buffers and which stores a program enabling the computer to execute a process, and the process comprises preparing an area in which data of a valid chain indicating a connection among frame buffers storing valid image data of the plurality of frame buffers and data of a vacant chain indicating a connection among frame buffers storing no valid image data, is stored, on memory and generating/updating data of the valid chain and the vacant chain when valid image data is stored in one of the plurality of frame buffers and storing it in the memory.

Abstract: Techniques and technologies are provided for binding resources to particular slots associated with shaders in a graphics pipeline. Resource dependencies between resources being utilized by each shader can be determined, and, based on these resource dependencies, common resource/slot associations can be computed. Each common resource/slot association identifies a particular one of the resources to be associated with a particular one of the slots.

Abstract: One embodiment of the present invention sets forth a technique for performing dual depth peeling, which is useful for order-independent transparency blending. Multiple rendering passes are performed on a graphics scene. After each rendering pass, the front-most and back-most layer of pixels are peeled away by computing a reference window. In subsequent rendering passes, only pixels within the reference window survive depth sorting. In each subsequent rendering pass, the reference window is narrowed by the front most and back most surviving pixels. By performing depth peeling in two directions simultaneously, the number of rendering passes needed to generate a completed graphics image is reduced from L to 1+L/2, which results in improved rendering performance.

Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Abstract: The architecture implements A-buffer in hardware by extending hardware to efficiently store a variable amount of data for each pixel. In operation, a prepass is performed to generate the counts of the fragments per pixel in a count buffer, followed by a prefix sum pass on the generated count buffer to calculate locations in a fragment buffer in which to store all the fragments linearly. An index is generated for a given pixel in the prefix sum pass and stored in a location buffer. Access to the pixel fragments is then accomplished using the index. Linear storage of the data allows for a fast rendering pass that stores all the fragments to a memory buffer without needing to look at the contents of the fragments. This is then followed by a resolve pass on the fragment buffer to generate the final image.

Abstract: A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. Additionally, a partition swizzling operation is used to adjust the partition numbers associated with individual units of virtual memory allocation on particular virtual memory pages to achieve a selected partition interleaving pattern.

Abstract: A method and apparatus for dynamic bandwidth determination and processing task assignment is disclosed. Embodiments include a video driver/interface that communicates with a video processing application such as a video editor. The video driver/interface is configurable to determine a best configuration of the system in order optimally perform the chosen video processing task. Configuration of a system includes dividing the task into subtasks and assigning the subtasks to processors of the system, including central processing units (CPUs) and graphics processing units (GPUs). Configuration of the system also includes optimizing use of available memory of different kinds.

Abstract: Intermediate target(s) are utilized in connection with computer graphics in a computer system. In various embodiments, intermediate memory buffers in video memory are utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.

Abstract: A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.

Abstract: The present disclosure describes implementations for performing register accesses and operations in a graphics processing apparatus. In one implementation, a graphics processing apparatus comprises an execution unit for processing programmed shader operations, wherein the execution unit is configured for processing operations of a plurality of threads. The apparatus further comprises memory forming a register file that accommodates all register operations for all the threads executed by the execution unit, the memory being organized in a plurality of banks, with a first plurality of banks being allocated to a first plurality of the threads and a second plurality of banks being allocated to the remaining threads. In addition, the apparatus comprises address translation logic configured to translate logical register identifiers into physical register addresses.

Abstract: A generic NUMA-compliant memory selection technique is provided to enable a device capable of accessing memory anywhere in a system to select a near (potentially the nearest) memory for use with the device. For example, an AGP controller can access system memory anywhere within a multiprocessing node system, but will operate more efficiently, and interfere less with other data transactions, if it locates the closest memory, determines the memory addresses corresponding to the closest memory, and locks (or otherwise allocates) memory addresses for AGP functionality within the range of determined addresses in the near memory.

Abstract: There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.

Abstract: An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: A method and apparatus for managing memory usage for three-dimensional computer graphics systems are provided. A scene which is textured and shaded in the system is divided into a plurality of rectangular areas, each including a plurality of picture elements in the scene. For each rectangular area a list of objects which may be visible in the scene is derived. Objects which do not contribute to the final textured and shaded scene are then removed from each list and the rectangular area is then textured and shaded using reduced lists of objects.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.

Abstract: A method to separately assign and modify multiple attributes of information and structure to an individual block or to a larger unitary whole comprised of multiple blocks is disclosed. A number of block instances of a block is determined. Each block instance is associated with one or more structure attributes. A number of data elements is determined. Each data element is associated with one or more information attributes. The data elements are mapped to the block instances. The mapped block instances are displayed contiguously.

Abstract: A method comprises storing pixel data in a frame buffer, retrieving the pixel data from the frame buffer and processing at least one pixel value of the pixel data to generate an output pixel bit stream. The method further comprises storing pixel values in a first update buffer. The pixel values are derived from the output pixel bit stream. The method also comprises providing the pixel values from the first update buffer across a network to a remote graphics system.

Abstract: The present invention sets forth a method and system for communicating with an external device through a processing unit in a graphics system of a computing device. In one embodiment, the method comprises allocating a first set of memory buffers having a first memory buffer and a second memory buffer in the graphics system based on an identification information of the external device, and invoking a first thread processor of the processing unit of the graphics system to perform services associated with a physical layer according to the identification information of the external device by storing a first data stream received from the external device through an I/O interface of the processing unit of the graphics system in the first memory buffer and retrieving a second data stream from the second memory buffer for transmission to the external device through the I/O interface.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: One embodiment of the invention is a method for storing transformed vertex attributes that includes the steps of allocating memory space for a transform feedback buffer, selecting one or more transformed vertex attributes to store in the transform feedback buffer independently of any shader programs executing on any processing units in the graphics rendering pipeline, configuring the transform feedback buffer to store the one or more transformed vertex attributes, and initiating a processing mode wherein vertex data is processed in the graphics rendering pipeline to produce the transformed vertices, the attributes of which are then written to the transform feedback buffer. One advantage is that the transform feedback buffer can be used to store and access transformed vertices, without having to convert the vertex data to a pixel format, store the pixels in a frame buffer, and then convert the pixels back to a vertex format.

Abstract: A method and system for implementing transfers of texture data in a computer system. The method includes the step of accessing a first block of texture data in a low latency memory, the first block having a predetermined size and accessing a second block of texture data in high latency memory, the second block having the predetermined size. The first block of texture data is copied from the low latency memory to a transfer space in high latency memory having the predetermined size. The second block of texture data is written from the high latency memory to the low latency memory, wherein the second block overwrites the first block. What used to be the transfer space is now treated as the first block now placed in high latency memory, and what used to be the second block is now treated to be the new transfer space.

Abstract: Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system.

Abstract: A video processing device may comprise one or more processors and/or circuits for use in a video processing device, in which the one or more processors and/or circuits may comprise a video scaler, a memory, a scaler engine, a clock selection circuit. The one or more processors and/or circuits are operable to receive a video image and select a video input clock or a display output clock for upscaling the received video image, or select the video input clock or the display output clock for downscaling the received video image based on a determination of whether the video image is to be downscaled or upscaled. The one or more circuits may be operable to downscale the received video image to generate a first scaled video image, and/or upscale the received video image to generate a second scaled video image, based on the selection.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.