Abstract: A memory manager interfaces between a rendering application and the driver controlling one or more memories. A multi-level brick cache system caches bricks in a memory hierarchy to accelerate the rendering. One example memory hierarchy may include system memory, AGP memory, and graphics memory. The memory manager allows control of brick overwriting based on current or past rendering. Since different memories are typically available, one or more memory managers may control storage of bricks into different memories to optimize rendering. Management of different memory levels, overwriting based on current or previous rendering, and an interfacing memory manager may each be used alone or in any possible combination.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to images. The combined filter emerging from the combination spares the processor time and the creation of an entire intermediary image. The system further provides for application of these techniques in many contexts including where the operations are fragment programs in for a programmable GPU.

Abstract: According to one embodiment, an image receiving apparatus includes a communication module, a memory, a controller, and an update. The communication module is configured to receive first content based on a first address and second content based on a second address by communicating with an external server. The memory is configured to store the first content and the second content. The controller is configured to control a list display of a first image corresponding to the first content and a second image corresponding to the second content. The update module configured to reacquire the first content based on the first address and update the first image in the list display to a first reacquisition image corresponding to the first content reacquired.

Abstract: A method of remapping memory, which is suitable for a server without a video graphics array (VGA), is provided. In the invention, a video memory buffer block is set in a system memory. First, a power on self test (POST) is executed for initializing the system memory. Next, a remap function is enabled. Then, a base address and a size of the video memory buffer block are set into a remap register of a chipset. Finally, the video memory buffer block is remapped into a memory address space originally mapped with a system management mode block according to the remap register.

Abstract: A graphics processing unit is designed to have validation logic utilizing a reduced memory space shadow memory as a source of state information for performing validation of commands. A semantic analysis is performed to generate the validation logic such that the reduced memory space shadow memory has a size small than a memory size required to store a full representation of a set of state variables associated with a class of commands.

Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.

Abstract: A display device that comprises a flag memory containing state flags of pixel areas of the image is provided. The display device comprises a display screen and a graphical generation unit implementing at least three functions for displaying an image, i.e. a first data erasure function, a second function for generating an image comprised of pixels in a first memory, and a third function for displaying the image by reading the pixels in said memory and controlling the screen, in which an image is divided into a plurality of separate pixel areas and in that each area is addressed by a flag, wherein the display device further includes a memory that stores the flag states so that the graphical generation unit can execute the display function on the basis of the flag states. The generation of images having a predominantly uniform background can, in particular, be used for application in aeronautics.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image IS disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of non-contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of non-contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.

Abstract: Techniques for management of drawing resources are described. In an implementation, a reference count numeral may be associated with a drawing resource stored in cache memory. One may be added to the reference count numeral each time a new drawing resource is added to memory. In addition, one may be removed from the reference count each time an existing drawing resource is removed from the memory. Also, the drawing resource may be maintained in the cache memory when the reference count numeral is greater than zero.

Abstract: The invention concerns a method for displaying a document on a display screen capable of being subjected to a scroll procedure, involving the following steps: providing the document with an amount of graphic memory to create a buffer memory of the visible part of the document and zones nearest to said visible part; calculating and cutting out into pixmaps said memory; relatively positioning said pixmaps with respect to the entire document and its visible part; filling up the content of the pixmaps, when the document is subjected to a display or scroll procedure, recopying the pixmap content in the display window; and repeating the relative positioning of the pixmaps with respect to the document.

Abstract: In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. The clusters are dynamically created from a fragmented pool of physical addresses as new virtual address mappings are requested by consumers of the virtual memory space.

Abstract: An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit.

Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.

Abstract: A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display. The memory includes at least one portion allocated to each rectangular area and at least one portion allocated as a global list.

Abstract: Systems and methods for performing data array resizing using a graphics processor resize a source data array of any dimensions to produce a destination data array of other dimensions. A pixel shader program may be used to configure the graphics processor to sample and filter the source data array to produce the destination data array. One or more destination data arrays may be mip maps of the source data array. A box filter or other type of filter may be used to produce each destination data array. Each pixel in the destination data array is produced in isolation, i.e., independently, thereby permitting the use of parallel processing to produce each pixel in the destination data array.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A method of visualizing visualization object data by creating a visualized image, including setting a visualization requirement; determining each node from a root node to a leaf node as a selected node, and determining whether or not the selected node satisfies the visualization requirement; registering nodes in a selected-node list for creating a visualization image when the selected node is a leaf node or has been determined to satisfy the visualization requirement, while replacing the selected node with child nodes of the selected node, and by making the child nodes new candidates for the selected node when the selected node has been determined not to satisfy the visualization requirement; outputting the selected-node list when there are no selected nodes to be processed; and creating the visualized image based on the visualization object data and node coordinate data associated with the respective nodes registered in the selected-node list.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: Methods, apparatuses, and systems are presented for performing multiple concurrent accesses in a shared memory resource comprising storing a first group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the first group being stored in a data entry in a first bank; skipping at least one data entry in at least one bank after storing a last data element of the first group, to introduce an offset; following the offset, storing a second group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the second group being stored in a data entry in a second bank different from the first bank; and concurrently accessing the first data element of the first group from the first bank and the first data element of the second group from the second bank.

Abstract: A method for managing a frame memory includes: determining a frame memory structure with reference to memory configuration information and image processing information; configuring a frame memory such that a plurality of image signals are stored in each page according to the frame memory structure; and computing a signal storage address by combining image acquiring information by bits, and accessing a frame memory map to write or read an image signal by pages.

Abstract: A system and method for optimizing the performance of a graphics intensive software program for graphics acceleration hardware. This system and method encompasses a procedure that validates the different functions of a 3D acceleration capable video card, decides whether to use the acceleration hardware and optimizes the software application to selectively use the functions that work on the specific video acceleration card. Functions checked include sub-pixel positioning, opacity, color replacement and fog. If these tests are successful, then the graphics acceleration is used by the software application. However, if the tests are not successful the decision is made not to use graphics accelerator. Those with ordinary skill in the art will realize that it is not necessary to perform all of the tests in a specific order.

Abstract: An image forming apparatus includes a plurality of hardware resources provided to carry out image formation. A plurality of application programs perform respective processing of the plurality of hardware resources related to the image formation. A storage device stores rewritable shared data which is used by the application programs in common. A shared-data control unit suspends one of a write-lock request or a read-lock request that is received from one of the application programs when acquisition and/or updating of the shared data is inhibited, and after the acquisition and/or updating of the shared data is allowed, inhibits the acquisition and/or updating of the shared data by other application programs in accordance with the suspended request for the one of the plurality of application programs.

Abstract: The present invention provides a virtual machine system and a method of accessing a graphics card. The virtual machine system includes a VMM, an SOS and at least one GOS, and further includes a resource converting module for performing IO address converting on graphics card framebuffer accessing data from GOS(s) or mapping MMIO(s) to physical MMIO(s) of a graphics card based on a resource converting table, and sending the processed data to the graphics card; and a framebuffer allocating module for dividing a framebuffer resource of the graphics card into multiple blocks and allocating them respectively to corresponding GOS(s). The resource converting table(s) records correspondences between a resource allocation for the graphics card by SOS and a resource allocation for the graphics card by GOS(s). The framebuffer MMIO resource(s) allocated to the graphics card by GOS(s) is/are the framebuffer allocated to GOS(s) by the framebuffer allocating module.

Abstract: The present invention provides an image processing apparatus that can make effective use of a memory area.

Abstract: An image formation processing simulation apparatus includes: a receiving unit that receives image data to which image formation processing is applied in an image formation processing device; a performing unit that performs simulation of image formation processing applied to the image data in the image formation processing device using the image data; a memory management unit that allocates a memory area for the image formation processing before the simulation, monitors the memory size required for the image formation processing in the simulation, and compares between the required memory size and the size of the allocated memory area; and an output unit that outputs information concerning the comparison result.

Abstract: A 3-dimensional computer generated image is generated by subdividing the image into a plurality of rectangular areas. Object data for each rectangular area is loaded into a display list memory until that memory is substantially full. Image data and shading data for each picture element of each rectangular area are derived by an image synthesis processor from the object data. The image data is then stored in a local memory. Additional object data is loaded into the display list memory and replaces existing contents. Then, the stored image data and the shading data are retrieved, and additional image data and shading data are derived for each picture element by the image synthesis processor using the additional object data and the previously derived image and shading data. When there is no further object data to load to the display list memory, the shading data is provided for display for the rectangular areas by a frame buffer.

Abstract: Buffers may be shared between components in a system. The components may be loosely coupled, allowing the components to be assembled into various different configurations, and yet buffers may still be shared. A buffer requirements negotiator of the system analyzes the buffer requirements of each of the components and determines, if possible, a set of requirements that satisfies all of the components. Accordingly, savings may be achieved in buffer memory, as well as in copying and converting between unshared buffers. Further, the individual components may operate as efficiently as possible because the buffer requirements of the components in the system are all met. One implementation accesses a first component's buffer requirements and a second component's buffer requirements, determines a reconciled set of buffer requirements that satisfies the buffer requirements of both components, and provides the reconciled set of buffer requirements to one or more components.

Abstract: A method to separately assign and modify multiple attributes of information and structure to an individual block or to a larger unitary whole comprised of multiple blocks is disclosed. A number of block instances of a block is determined. Each block instance is associated with one or more structure attributes. A number of data elements is determined. Each data element is associated with one or more information attributes. The data elements are mapped to the block instances. The mapped block instances are displayed contiguously.

Abstract: Memory management techniques involve establishing a memory pool having an amount of sharable memory, and dynamically allocating the sharable memory to concurrently manage multiple sets of sequenced units of digital data. In an exemplary scenario, the sets of sequenced units of digital data are sets of time-ordered media samples forming clips of media content, and the techniques are applied when media samples from two or more clips are simultaneously presentable to a user as independently-controlled streams. Variable amounts of sharable memory are dynamically allocated for preparing upcoming media samples for presentation to the user. In one possible implementation, a ratio of average data rates of individual streams is calculated, and amounts of sharable memory are allocated to rendering each stream based on the ratio. Then, the sharable memory allocated to rendering individual streams is reserved as needed to prepare particular upcoming media samples for presentation to the user.

Abstract: A method for displaying thumbnails on a mobile device includes allocating at least two buffers in a storage system of the mobile device, where the at least two buffers comprise a displayed thumbnail buffer and a current thumbnail buffer. Indices of the thumbnails on are displayed on a display screen of the mobile device, and thumbnails from the displayed thumbnail buffer are read if the thumbnails correspond to the indices are found in the displayed thumbnail buffer. In addition, the method further includes reading the thumbnails from the current thumbnail and displaying the thumbnails on the display screen of the mobile device.

Abstract: A method and apparatus for comparing portions of data from a digital raster signal to a plurality of scan blocks of data, where each scan block in the plurality describes either a defined image area or entire image frame is disclosed. Included are a hashing function that calculates hash codes for spatially-defined segments of an incoming raster signal; a recent scan hash table containing hash codes for scan blocks received within a specified time period; a comparator for comparing calculated hash codes for the spatially-defined segments of the incoming raster signal with hash codes stored in the recent scan hash table; a pixel capture and timing module for capturing a digital raster signal; and an output selector for selecting for transmission a compressed form of a scan block, a hash code index, or no data if a scan block exists in a remote frame playout buffer.

Abstract: A memory includes at least one memory cell. The memory cell includes a first set of bits and a second set of bits for respectively storing first sub-pixel data and second sub-pixel data of pixel data. The first set of bits has a first fail bit. A least significant bit of the first sub-pixel data is stored at the first fail bit.

Abstract: Apparatus are provided, including an embedded display processor on a given chip. The apparatus may be an embedded device, for example, a mobile wireless communications device. More specifically, the apparatus may be a mobile phone, a portable gaming device, a video streaming device, or a GPS map drawing device. The display processor includes, on the same given chip, a rendering memory, from which pixels are rendered to a display device. The display processor further includes an image manipulation mechanism to manipulate pixels of a given image frame from source positions in a pre-manipulation buffer, to target positions in the rendering memory, the target positions corresponding to rendered positions in the given image frame.

Abstract: This disclosure describes a method for allowing multiple users to independently run graphical applications on a Windows computer at the same time by loading private instances of the graphics subsystem for each user at different virtual addresses within the kernel address space.

Abstract: A video data displaying device is disclosed. The video data displaying device is used to drive a displayer according to a first display data set to display a first picture, the displaying device comprises a memory for storing the first display data set, and a display engine which is electrically connected to the memory for storing a part of the first display data set stored in the memory, wherein the display engine selects a specific display data set from the first display data set according to a display area of the displayer, and the display engine does not output the specific display data to the displayer.

Abstract: A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.

Abstract: An operation displaying device including: an operation screen which receives an instruction for operation; a computing device which executes computation; and a performance monitoring unit which monitors a performance of an application software that executes display processing, wherein: when an operation mode of the operation displaying device is in a power saving mode and a remaining memory capacity of a memory, which is used as temporary storage by the computing device, is less than or equal to than a predetermined threshold, the performance monitoring unit restarts the application software which is running.

Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.

Abstract: Described herein is a system and method for facilitating large volume data processing and rendering. An exemplary system includes at least one processor coupled to a first memory, wherein the processor is configured to organize the large volume data in the first memory into one or more bricks. In addition, at least one graphics processing unit (GPU) is coupled to the processor and a second memory. The GPU is configured to process at least one or more bricks transferred from the first memory to the second memory to produce intermediate processing results, and to further render the intermediate processing results.

Abstract: An apparatus and method of displaying a first image on a display device with a plurality of pixels assigns one of a plurality of sample patterns to each pixel on the display device. Each pixel is assigned the one of a plurality of patterns based upon its unique location on the display device. Each sample pattern has at least one sample location. It then is determined if the first image intersects any of the sample locations on each pixel. Pixels determined to have at least one sample location that intersect the first image thus are illuminated.

Abstract: A graphic memory is space-divided into a first area and a second area. In the first area, a task corresponding to a predetermined application is executed regardless of which task is processed by a main processor. A switchable area is divided in time so that data related to tasks corresponding to a plurality of applications is sequentially stored in the switchable area in accordance with task switching in the main processor.

Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.

Abstract: Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method embodiment, among others, comprises responsive to a first shader operation, receiving at a constant buffer a first group of constants corresponding to a first rendering context, and responsive to a second shader operation, receiving at the constant buffer a second group of constants corresponding to a second context without flushing the first group.

Abstract: A method is provided for processing data in a mobile communication terminal including a first data memory for storing first data indicating user-stored information and a second data memory for storing second data indicating user-stored information. The method includes creating a first data list corresponding to the first data and a second data list corresponding to the second data and displaying items of the first data list and items of the second data list on a screen of the mobile communication terminal in response to a user's data movement request, selecting at least one item from one that is selected from the first data list and the second data list that are separately displayed based on user's selection information, and storing data of the selected item in the first data memory or the second data memory into the other memory if a predetermined key is input.