Abstract: A driving integrated circuit and methods thereof are provided. The driving IC includes a memory for driving a display panel and having a memory structure including at least one cell block, a scan register receiving data read from the memory, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block. One method includes performing a read operation to read data from a memory, the read operation including sensing and amplifying data stored within a memory cell, turning on a switch to increase a bit line voltage above a voltage threshold and latching the amplified data received through a line connected to the switch and transmitting the read data to the panel of the display device.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth.

Abstract: An image processing apparatus includes a storage unit storing the OSD image data corresponding to plural subframes; a load storage unit loading and storing the OSD image data corresponding to the plural subframes; a reading unit reading out plural subframes of the OSD image data in parallel; and a controlling unit controlling to load in parallel the plural sunframes of the OSD image data into the load storage unit and to read out in parallel from the load storage unit and transmits the OSD image data to a combining unit to combine the OSD image data with the corresponding image data.

Abstract: A method of processing an image includes traversing pixels of an image in a single pass over the image. An inverting function is applied to the pixels. A recursive filter is applied to the inverted pixel values. The filter has parameters which are derived from previously traversed pixel values of the image. A pixel value is combined with a filter parameter for the pixel to provide a processed pixel value for a processed image.

Abstract: The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for generating tile sizes associated with an image presented by a web based image system. An optimal threshold memory size for tiles associated with the image is identified. The image is then divided into tiles of equal physical dimensions and placed into a set of subdivided tiles. The memory size of each tile within the set of subdivided tiles is compared to the threshold memory size. Tiles having a memory size less than or equal to the threshold memory size are deleted from the set of subdivided tiles and stored. Tiles having a memory size greater than the threshold memory size are subdivided into tiles of smaller physical dimensions. The smaller tiles are placed back in the set of subdivided tiles. The process repeats until no tiles exist within the set of subdivided tiles.

Abstract: The invention described in this application is an image file system for the acquisition and storage of streaming digital image data onto persistent storage media in real time and for full-rate playback of streaming digital image data stored on persistent storage media. Input/output of non-streaming digital image data is processed in system memory with write/read operations buffered by native operating system input/output support. Input/output of streaming digital data is processed in high-speed streaming digital image data I/O memory with write/read operations buffered by a high-performance image buffer thread.

Abstract: A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. Additionally, a partition swizzling operation is used to adjust the partition numbers associated with individual units of virtual memory allocation on particular virtual memory pages to achieve a selected partition interleaving pattern.

Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: A drawing device that includes a triangle detecting unit specifying a triangle to be drawn and specifying a pixel block having a pixel of the triangle and includes a B-edge detecting unit judging whether or not the pixel block specified by the triangle detecting unit includes a pixel of a triangle that is connected to the triangle. The drawing device also includes a rasterizing unit that, when the B-edge detecting unit judges that the pixel block specified by the triangle detecting unit includes the pixel of the triangle, performs the rasterization processing on the pixel block so that pixel data is generated, includes a memory R/W unit writing the pixel data of the pixel block that is generated by the rasterizing unit into a memory, and includes a drawing engine controlling a display of an image in accordance with the pixel data written into the memory.

Abstract: A system-on-a-chip (SoC) to process digital audio-video content includes one or more input/output (I/O) interfaces to transmit the digital audio-video content to corresponding I/O devices coupled to the SoC and to receive the digital audio-video content from the corresponding I/O devices. The SoC also includes a cryptographic engine to encrypt the digital audio-video content being transmitted via the I/O interfaces to the corresponding I/O devices and to decrypt the digital audio-video content received via the I/O interfaces from the corresponding I/O devices.

Abstract: A graphics system has virtual memory and a partitioned graphics memory that supports having an non-power of two number of dynamic random access memories (DRAMs). The graphics system utilizes page table entries to support addressing Tag RAMs used to store tag bits indicative of a compression status.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for texture filtering within the graphics processing unit, partitioning the texture data into banks, performing a bank swizzle operation on the banks, and writing the banks of data to the L2 cache.

Abstract: A graphics system has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. In one implementation, the memory elements are dynamic random access memories (DRAMs) and the system supports having a non-power of two number of active DRAMs.

Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

Abstract: Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: A graphics system coalesces Z data and color data for a raster operations stage. The Z data and color data are stored in a memory aligned tile format. In one embodiment, rendering modes in which the tile does not have a data capacity corresponding to Z data or color data for a whole number of pixels have data for at least one pixel split across entries to improve packing efficiency. Rendering modes having a number of bits for Z data or color data that does not equal a power of two such as 24 bits, 48 bits, and 96 bits, may be implemented with a high packing efficiency in tile formats having a data capacity corresponding to a power of 2 bits.

Abstract: An image processing system includes a memory, a data slicer and an image processor. The data slicer divides each of current image data and adjacent image data into a first portion and a second portion to be stored into the memory. The image processor reads from the memory the first portion and the second portion of the current image data and the first portion of the adjacent image data for image processing.

Abstract: The number of crossbars in a graphics processing unit is reduced by assigning each of a plurality of pixels to one of a plurality of pixel shaders based at least in part on a location of each of the plurality of pixels within an image area, generating an attribute value for each of the plurality of pixels using the plurality of pixel shaders, mapping the attribute value of each of the plurality of pixels to one of a plurality of memory partitions, and storing the attribute values in the memory partitions according to the mapping. The attribute value generated by a particular one of the pixel shaders is mapped to the same one of the plurality of memory partitions.

Abstract: Embodiments of the invention provide methods and apparatus to improve the efficiency of a ray tracing image processing system. According to one embodiment of the invention, when building a spatial index the position of a splitting plane used to create a bounding volume may be jittered or moved along an axis to determine if a more efficient location for the splitting plane exists. After jittering the splitting plane a number of primitives intersected by the splitting plane may be calculated. The number of primitives intersected by the splitting plane for each location may be compared, and the location with the fewest intersected primitives may be chosen for the final position of the splitting plane. By choosing the location with the fewest intersected primitives the number of ray-primitive intersection tests necessary when performing ray tracing may be reduced. Consequently, the efficiency of the image processing system may be improved.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit.

Abstract: A method of remote displaying and processing based on Server/Client architecture adopts a technical scheme of specific inter-frame increment compression and data comparison compression of the adjacent area-bits of the inner-frame within the side of Server, thus removing the intricate computation mode in the traditional inter-frame compression scheme, and reducing the resource usage of a computer; the side of the client adopts an increment refreshing mode to display an image, only refreshes the changed part, if the part was changed, then the part was refreshed; so that the refreshing speed of the remote desktop is improved highly, while the system resource usage of the computer is reduced highly.

Abstract: A graphics adapter comprises a frame buffer operable to store graphics image data. The graphics adapter also comprises a network interface operable to receive at least a portion of the graphics image data, the network interface further operable to format the received graphics image data into a plurality of packets for transmission over a communication network.

Abstract: In a video application, a method and system provide different sizes of data-fetch where the data transfer rate between a decoder and an external memory (e.g., DDR memory) is extremely high, as for example in HDTV systems. The invention in one form divides a reference frame into different tiles where each tile is hierarchically divided into smaller tiles to a level where the minimum tile size is the same as the fixed burst size of the DDR memory. The method also provides for arranging the biggest tiles into different banks and pages so that even if the block to be fetched falls across tile boundaries, the latency penalty in the tile transition will be minimized. The invention provides advantages also for progressive and interlaced data fetch.

Abstract: Methods, apparatuses, and systems are presented for performing multiple concurrent accesses in a shared memory resource comprising storing a first group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the first group being stored in a data entry in a first bank; skipping at least one data entry in at least one bank after storing a last data element of the first group, to introduce an offset; following the offset, storing a second group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the second group being stored in a data entry in a second bank different from the first bank; and concurrently accessing the first data element of the first group from the first bank and the first data element of the second group from the second bank.

Abstract: The present invention provides an image processing apparatus that can make effective use of a memory area.

Abstract: A video signal processing apparatus includes two image display memory areas 22 and 24 which alternately repeat input and output operations by receiving a signal obtained by performing predetermined processing for an output image signal from an image sensor 12, an image display unit 28 for displaying an object image represented by image frames sequentially output from the two memory areas, a system controller 40 which, when an image frame is to be input to one of the two memory areas, causes the other one of the two memory areas to output a held image frame, and causes the two memory areas to alternately repeat the input and output operations, thereby switching inputting and outputting of the two memory areas, and a mode determination circuit 272 for determining whether the frame rate of the output image signal from the image sensor 12 is higher or lower than the image display rate of the image display unit 28.

Abstract: System and method for analyzing an image. A received image, comprising an object or objects, is optionally preprocessed. Invariant shape features of the object(s) are extracted using a generalized invariant feature descriptor. The generalized invariant feature descriptor may comprise a generalized invariant feature vector comprising components corresponding to attributes of each object, e.g., related to circularity, elongation, perimeter-ratio-based convexity, area-ratio-based convexity, hole-perimeter-ratio, hole-area-ratio, and/or functions of Hu Moment 1 and/or Hu Moment 2. Non-invariant features, e.g., scale and reflection, may be extracted to form corresponding feature vectors.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.

Abstract: Methods for texture image management are provided. An embodiment of a method for texture image management comprises the following steps. A texture image is acquired from a non-writable memory device. The received texture image is directly applied to a fragment.

Abstract: Apparatus are provided, including an embedded display processor on a given chip. The apparatus may be an embedded device, for example, a mobile wireless communications device. More specifically, the apparatus may be a mobile phone, a portable gaming device, a video streaming device, or a GPS map drawing device. The display processor includes, on the same given chip, a rendering memory, from which pixels are rendered to a display device. The display processor further includes an image manipulation mechanism to manipulate pixels of a given image frame from source positions in a pre-manipulation buffer, to target positions in the rendering memory, the target positions corresponding to rendered positions in the given image frame.

Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.

Abstract: Bursts of data are managed. Data is stored in a machine readable memory device a first time at a first memory address. The machine readable memory device has one or more burst boundaries. The first memory address has a first alignment with respect to the burst boundaries. The data is stored in the machine readable memory device a second time at a second memory address. The second memory address has a second alignment with respect to the burst boundaries.

Abstract: With the aid of a storage unit for storing EDID, a memory unit is merely provided power by a bus power while a related power source is turned off, and power leakage is prevented since possible paths of the power leakage are blocked by reverse biasing of related elements of the storage unit. A storage module including a plurality of the designed storage units have same operations and performance as those of the designed storage unit.

Abstract: Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modem graphics chips.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A display color buffer in a unified memory architecture is decoupled from main memory by partitioning the address space for the color buffer into a frame-preparation memory accessed by a graphics subsystem at a frame rate to prepare color data and a refresh memory that is accessed by a display device at a refresh rate to display the color data. The color data is periodically transferred between the frame-preparation memory and the refresh memory, or when a frame of color data is ready for display.

Abstract: Methods for analyzing a list of routine identifiers to optimize processing of routines identified in the list. Some embodiments execute a set of routines in multiple passes where each pass comprises each routine in the set processing a single band of its source. The band size of the sources of the set is related to the size of a cache used during execution of the set. A band size of sources of the set is determined so that all data processed by and produced by any routine in the set can be stored to the cache while the routine processes one band of its source. Some embodiments use the list to combine two or more routines into a single routine where the list is modified accordingly. Some embodiments use the list for grouping and re-ordering routines identified in the list to send particular routines to an alternative processor for processing.

Abstract: Presented herein is a system for storing macroblocks for concatenated frames. A decoder system comprises a frame buffer. The frame buffer comprises one or more rows. A particular one of the rows stores macroblocks from a plurality of frames.

Abstract: An image forming apparatus and a method of acquiring a memory area are disclosed for preventing a problem that image data cannot be converted due to failure of memory acquisition. The image forming apparatus includes an image data conversion part, a resource management part and an image data management part. The image data conversion part has at least one conversion function to convert a format of image data. The resource management part determines a memory size required for a conversion function to convert the format of the image data. The image data management part acquires a memory area corresponding to the determined memory size.

Abstract: The invention discloses a method for mapping picture addresses in a memory, such that decoded picture data can be mapped in corresponding address in a memory. The memory comprises at least two memory arrays, each of which comprises multiple memory rows. The mapping method comprises the following steps: dividing one picture frame into multiple rectangle macroblocks; providing a memory for storing picture data and setting integral neighbor macroblocks of an picture frame as one mapping unit; one by one, the mapping units of picture data are consecutively mapped into the memory in the order of left to right in horizontal directions and up to down in vertical directions; mapping at least one mapping unit of picture data into the same memory row of the same memory array until the said memory row is full; switching the memory array and mapping the adjacent next mapping unit of picture data. The above steps are repeated until completing the mapping of one picture frame.

Abstract: A graphics system coalesces Z data and color data for a raster operations stage. The Z data and color data are stored in a memory aligned tile format. In one embodiment, rendering modes in which the tile does not have a data capacity corresponding to Z data or color data for a whole number of pixels have data for at least one pixel split across entries to improve packing efficiency. Rendering modes having a number of bits for Z data or color data that does not equal a power of two such as 24 bits, 48 bits, and 96 bits, may be implemented with a high packing efficiency in tile formats having a data capacity corresponding to a power of 2 bits.

Abstract: A system and method is provided which enables pixel data stored in multiple memory pages to be combined in one data packet, thereby reducing the number of data packets needed to transfer a group of reference pixel data. In one embodiment for reducing the reference data fetch bandwidth, the method as applied to a real-time video decoding system optimally combines pixel data stored in different memory pages, and fits the pixel data into a predetermined number of data packets.

Abstract: A memory controller of an apparatus repeatedly retrieves a down-sampled file of a digitally captured image from a non-volatile memory for refresh of a raster display screen.