Abstract: A method for reading atoms positioned within a memory having a first memory portion and a second memory portions, comprising the steps of (a) positioning the atoms having memory addresses across the memory, (b) defining a strip across a portion of the atoms, (c) designating a first atom within the strip, (d) locating one or more second atoms to be paired with the first atom, (e) determining whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (f) reading the legitimate pair from the first memory portion and the second memory portion.

Abstract: A method of storing an array of digital data into a memory. The memory includes a plurality of memory pages, and each memory page has a first memory section and a second memory section. The method includes a first step of dividing the array of digital data into a plurality of block units, while each of the block units has a plurality of odd rows and a plurality of even rows, and each of the odd rows and the even rows has at least one byte. The method further includes a second step of storing subsequent odd rows of at least one of the block units into consecutive storage locations in the first memory section, and storing subsequent even rows of at least one of the block units into consecutive storage locations in the second memory section. In this way, the memory bandwidth can be used more efficiently.

Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.

Abstract: A control method to control a display unit in which a video signal is supplied by an external device to display the video signal, the control method including: dividing EDID information of the display unit in essential EDID information that is required to display the video signal and non-essential EDID information excluding the essential EDID information; and storing the essential EDID information in a non-changeable memory and at least a part of the non-essential EDID information in the changeable memory.

Abstract: Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A memory control unit controls the transfer of image data from a video buffer to a frame buffer, and from the frame buffer to a display, to be performed block by block. Image data is written from a video buffer to the frame buffer one block at a time. When image data for the entire block has been written to the frame buffer, the data for that block can be refreshed on the display. Image data for the next frame can only be written to the frame buffer once the data in that block has been refreshed on the display. In this way, image tearing can be eliminated. Images can also be successfully rendered when the direction of writing data to the frame buffer is perpendicular to the direction of copying data from the frame buffer and refreshing the display. Thus, landscape images can be rendered on a portrait display, without the need for double buffering.

Abstract: Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a reference frame that overlaps four macroblocks, each of the overlapped macroblocks can be fetched substantially concurrently.

Abstract: An image processing apparatus, able to suppress occurrence of a penalty such as page miss and able to efficiently draw an image, provided with a triangle transfer control device for judging whether a triangle is inside/outside a page, detecting a page where a triangle may be drawn, preparing a list of pages where triangles will be drawn, taking out a page from this list, outputting the triangle data and the corresponding drawing page data to a triangle drawing device so as to draw the object (triangle) for only the interior of the region of that page, erasing the output drawing page from the prepared list, and outputting triangle data and corresponding drawing page data until there are no longer pages on the list so as to draw all triangles in the pages.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: The present invention relates to a way of storing 3D images. The 3D image is composed of a stack of two-dimensional video data subsets represented by arrays of pixel data. Each array of pixel data is partitioned into a plurality of overlapping and adjacent vertical stripes of pixel data having a width at most equal to a cacheline of the memory. The upper most left stripe is stored first and each stripe is stored after the left adjacent stripe. When storing each stripe having multiple rows of pixel data, the upper row is stored first and the first pixel data of each subsequent row of the stripe is stored in a memory location coming after a memory location where the last pixel data of the preceding row in the stripe is stored.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device modified regions of a frame buffer. A frame buffer is divided into the regions, and data in the frame buffer represents pixels on the display device. The frame buffer accumulates writes until the region being written to changes, at which time the region is copied to the display device.

Abstract: A multimedia reproducing apparatus having excellent operability and amenity. In the apparatus, a ROM contains an OS including a system program and a utility program. A control unit controls at suspend function by which data indicating the state of contents of display and contents of execution before interruption of a power supply to a CPU is stored as save data so that the power supply, after interrupted, can be resumed from the state before interruption. A main memory includes a first area for the save data to be written to when suspend is executed, and a second area for data of an external program to be written to when the external program is executed. The system program has the functions of writing the save data to the first area when suspend is executed, and writing the utility program from the ROM to the first area when suspend is not executed and the utility program is called from the external program.

Abstract: A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined number of fragments are statically allocated to each pixel. Additional space for fragment data is dynamically allocated and deallocated. Each dynamically allocated unit of memory contains fragment data for a plurality of pixels. Fragment data are arranged to exploit modem DRAM capabilities by increasing locality of reference within a single DRAM page, by putting other fragments likely to be referenced soon in pages that belong to non-conflicting banks, and by maintaining bookkeeping structures that allow the relevant DRAM precharge and row activate operations to be scheduled far in advance of access to fragment data.

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first, second and third internal memory communicating with the first, second and third data port interface. A first and second memory management unit for communicating data and to control access to and from the second internal memory, are also provided. A communication channel is provided for communicating data and messaging information.

Abstract: A control driver includes a display memory control section which generates a first process control signal when image data includes only first image data which has a pixel size equal to or smaller than that of a display section, and generates a second process control signal when the image data includes first image data and second image data and the first image data has a pixel size equal to that of the display section, and a display memory section which stores upper and lower portions of the first image data as first and second portions of display data in response to the first process control signal, and stores the upper portion of the first image data and an upper portion of the second image data as the first and second portions of the display data in response to the second process control signal. The display data is displayed on the display section.

Abstract: A system and method for capturing and transposing vertically scanned documents in an imaging system uses a paged buffer memory, such as DDR SDRAM. Images are captured in the paged buffer memory by writing the images into memory cells in a series of columns, and images are transposed by reading the images from the memory cells in a series of rows. During transposition, the memory cells are partitioned into a plurality of column groups so that a plurality of consecutive pixels of a digitized image can be written on the same memory page. The image is read from the buffer memory in a series of rows arranged in a plurality of groups of consecutive pixels so that a plurality of consecutive pixels can be read from the same memory page.

Abstract: Numerous shortcomings exist in prior generation adapter cards for supporting remote consoles for multipartition computer systems. Emulation using memory in the adapter card supports some remote functions so that they appear to be resident on the host computer system to each partition. Additionally, the host computer system memory can be used in one mode to support the emulation of extended mode video console support functions. Scoreboarding and hardware compression are used to limit the volume of data required to be updated to support the emulation.

Abstract: A tiled graphics memory permits z data and stencil data to be stored in different portions of a tile. The tile may be further divided into data sections, each of which may have a byte size corresponding to a memory access size.

Abstract: The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels. The compressed stencil buffer is utilized with a compressed stencil buffer cache to perform a stencil shadow volume operation more efficiently than present methods.

Abstract: Multi-component data is managed. Pixel image data is stored in a machine readable memory device. The pixel image data is decomposed into multiple colorspace components. The multiple colorspace components are stored in one continuous machine-readable memory segment of a machine-readable memory. The machine-readable memory has one or more burst boundaries.

Abstract: Disclosed is a system and method for processing graphic operations on a plurality of data structures of an image with a graphics processing unit and memory. The disclosed techniques of the system and method create an accumulation buffer of the data structures for accumulating changes to the data structures. A separate buffer is then created from at least a portion of the data structures of the accumulation buffer. The disclosed techniques read the data structures from the separate buffer with the graphics processing unit. The graphics processing unit operates on the data structures read from the separate buffer with the operation. Then, the disclosed techniques write the results of the operation onto the portion of the accumulation buffer corresponding to the separate buffer.

Abstract: A decoder includes a first bank and a second bank. The first bank is supplied with dynamic control from a microcomputer via a data bus, and the second bank is supplied with static control data from the data bus via the data bus. The dynamic control data or the static control data is read from an address in the bank designated by an address signal. The dynamic control data read from the first bank and second bank is transferred to one of a plurality of registers designated by the address signal.

Abstract: A font memory for a display includes a ROM with a storage region divided into a program storing region and a font data storing region, divided into a mono-font data storing region and a color font data storing region, and designed to map and store data in three segment storage regions in the color font data storing region with respect to a character CRA code defining characteristics of color font data. Three segment storage regions in the color font data storing region, in which color font data corresponding to a CRA code, which is not displayed on a screen, of CRA codes of color font data with respect to a specific font, are to be written, have a mono-font storage diversion changeable storage region that stores therein mono-font data with respect to a font other than the specific font.

Abstract: A controller-driver, a method of driving the controller-driver, and a method of processing image data enabling scroll or other various functions without adding a storage capacity of a display memory nor increasing power consumption. A built-in display memory having a capacity of one frame (H pixels×V pixels×the number of bits) is partitioned into a plurality of memories according to an image type. High order bits are then stored in a first display memory 7a and high order bits of the next frame or low order bits are stored in a second display memory 7b by using a first selector 8 to a third selector 10 controlled by a memory control circuit 6 before they are read out. Thereby, high-level image data of one frame can be displayed when the scroll function is not used and image data of a plurality of frames can be displayed without accessing an image drawing unit 1 when the scroll function is used, thereby reducing power consumption.

Abstract: A networking conferencing and collaboration tool utilizing an enhanced T.128 application sharing protocol. This enhanced protocol is based on a per-host model command, control, and communication structure. This per-host model reduces network traffic, allows greater scalability through dynamic system resource allocation, allows a single host to establish and maintain a share session with no other members present. The per-host model allows private communication between the host and a remote with periodic broadcasts of updates by the host to the entire share group. This per-host model also allows the host to allow, revoke, pause, and invite control of the shared applications. Subsequent passing of control is provided, also with the hosts acceptance. The model contains no fixed limit on the number of participants, and dynamically allocates resources when needed to share or control a shared application. These resources are then freed when no longer needed.

Abstract: A method for communicating digital display data and associated auxiliary processing data from a frame buffer to a post processor. The method includes storing the display data and the auxiliary processing data in the frame buffer, forming video scan lines from the frame buffer by handling both the display data and the auxiliary processing data as video data, and transferring the video scan lines over a digital video interface to a post-processor.

Abstract: A memory model for a run-time environment is disclosed that includes a process-specific area of memory where objects in call-specific area of memory and session-specific area of memory can be migrated to at the end of a database call. User-specific objects can be then migrated to the session-specific area of memory. In one embodiment, the process-specific area of memory can be saved in a disk file and used to hot start another instance of an application server.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: An image processing apparatus capable of performing a refresh operation without causing a drop in performance, an increase in cost, or damage to the apparatus. The apparatus further being capable of achieving a reduction in power consumption, and being provided with a memory I/F circuit able to not only refresh, for example, four DRAM modules simultaneously, but also capable of refreshing two DRAM modules at a same timing, then refreshing the remaining two DRAM modules simultaneously at a next timing, or refreshing the four DRAM modules one by one in order based on given refresh control data, and controlling the timing of the refresh operation for each divided DRAM module.

Abstract: Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Abstract: Provided are a method and apparatus for accelerating graphic data which can reduce the computational complexity of graphic processing data. The method of accelerating two-dimensional graphic data includes: receiving information regarding the width of a graphic window to be processed; reading pixel data from a memory in which pixel data in the graphic window is stored; receiving information regarding two pixel data regions which are divided from the memory area based on the width information of the graphic window, one pixel data region to be processed using a burst mode and the other pixel data region to be processed in units of bytes; and individually performing predetermined graphic processing on the divided pixel data regions.

Abstract: A method for storing data of a plurality of components of an image in a memory system with four banks comprising the steps of (A) placing a first portion of data of a first component of the plurality of components into a first bank of the four banks and (B) placing a second portion of the data of the first component in a second bank of the four banks, where all of the data of the first component is stored in the first and second banks and occupies at least three pages in the memory system.

Abstract: A graphics memory includes a plurality of memory partitions. A memory controller organizes tile data into subpackets that are assigned to subpartitions to improve memory transfer efficiency. Subpackets of different tiles may be further assigned to subpartitions in an interleaved fashion to improve memory operations such as fast clear and compression.

Abstract: A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to generate samples in response to received graphics data, and to forward the samples to the scheduling network for storage in the sample buffer. The filtering engine is configured to send a request for samples to the scheduling network. The scheduling network is configured to compare a video set designation of the request to a previous request designation, to update one or more state registers in one or more memory devices of the sample buffer in response to a determination that the video set designation of the request is different from the previous request designation, and to assert signals inducing a transfer of a collection of samples corresponding to the request from the one or more memory devices to the filtering engine.

Abstract: A system and method is provided for supporting a multiple display configuration through a single connected display device. The present disclosure allows a system desktop to be expanded across multiple virtual displays without a need for extra hardware to support multiple display devices. A display driver partitions a frame buffer of a video card into portions. Each portion is used to support a different virtual display. The display driver reports a number of virtual displays to an operating system and provides pointers to addresses associated with the portions of the frame buffer. The operating system treats each frame buffer portion as a separate frame buffer and stores video data for each virtual display in an associated frame buffer portion. The display driver selects a virtual display from a set of multiple virtual displays and routes video data from the frame buffer portion associated with the selected display for output on a connected display device.

Abstract: An address converting unit receives pixel coordinates of a display screen in sequence and converts the received pixel coordinates to addresses and offsets. The addresses and offsets obtained from the conversions are stored in buffers in sequence respectively. A buffer controlling unit detects that one of the buffers is full. In response to the detection by the buffer controlling unit, a pixel processing unit modifies pixel data corresponding to the plural addresses read from the memory device according to pixel information. The pixel data stored in the memory device are rewritten according to the pieces of pixel information inputted in correspondence with the pixel coordinates. Therefore, the pieces of pixel data corresponding to the plural addresses are rewritten at a time.

Abstract: The present invention relates to an apparatus and method for inputting and displaying data for a refrigerator, and more particularly, to an apparatus and method for inputting and displaying data for a refrigerator wherein various data can be inputted and displayed in the form of images using a touchscreen. To this end, in the present invention the input and display of the characters are not made in a manner that the characters for forming the data are inputted but made in the form of the images corresponding to the characters. Thus, the input and display of the data can be performed regardless of the languages, and the regions and countries where the refrigerators are used. Accordingly, the present invention has an advantage in that the information on various data can be conveniently obtained without limitations on the function, used time and language for inputting the characters.

Abstract: A graphics system and method for displaying lines on a display device. The system may comprise a sample buffer, a rendering unit and a sample-to-pixel calculation unit. The rendering unit may (a) generate a plurality of sample positions in a two-dimensional space, (b) determine a sample normal distance for each of the sample positions with respect to a line defined by the line-draw command, (c) assign sample values to the sample positions based on the sample normal distance of each of the sample positions, and (d) store the sample values in the sample buffer. The sample-to-pixel calculation unit may read sample values from the sample buffer, filter them to determine a pixel value, and transmit the pixel value to the display device. The rendering unit may render the line sample values with a narrower width to pre-compensate for the line-expanding effect of the filtering performed by the sample-to-pixel calculation unit.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: The present invention provides a system and method for checking authorization of remote configuration operations. The method comprises storing at least one image frame such that content of the image frame is stored in a plurality of memory pages in a memory. The method further comprises sending the image frame to the display one memory page at a time to refresh the display.

Abstract: A system and method for rendering a graphics primitive. A two pass method is employed where, in the first pass, for each block affected by the primitive, whether the pixels of the affected block intersect the front and/or back layers of the block is determined. If there are intersected pixels in the block, a flag is set indicating that the z-buffer must be read to determine the visibility of the affected pixels in the block. On a second pass, the blocks affected by the graphics primitive are again examined. If the flag is not set, then the visible pixels are rendered to the frame buffer based on the front and back layers of the block. If the flag is set, then for each sub-block affected by the primitive, the z-buffer is read and the visible pixels are rendered to the frame buffer based on the reading of the z-buffer.

Abstract: An overdrive system for driving a display device. A host machine includes a display interface for connecting with the display device. The display interface includes a display chip and a video memory. The overdrive system includes a frame buffer for holding the display data of the previous frame. The frame buffer uses a portion of the video memory space. The overdrive system also includes an overdrive look-up table coupled to the display chip to provide a correspondence between the overdrive display data, the display data of the previous frame and the display data of the present frame. The display chip retrieves overdrive display data from the overdrive look-up table according to the display data of the previous frame obtained from the frame buffer and the display data of the present frame and transmits the overdrive display data to the display device so that an image is formed on the display panel.

Abstract: A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.

Abstract: This disclosure provides a system for efficiently processing a data set. More particularly, image data such as volumetric data are stored in a spread memory fashion, with image data subsets occupying only a fraction of each page. Each memory page is sized to roughly map to processor cache size (or a section thereof), such that image data is always mapped to one or more predetermined fractions of processor cache. By keeping processing parameters (e.g., look-up tables and buffers) in the remainder of cache, the system effectively locks those parameters against overwrite by the image data. This system facilitates the use of conventional workstations, laptops and other machines not enhanced for processing large or complicated data sets. It also extends capabilities of both un-enhanced and enhance machines, permitting them to process data more efficiently.

Abstract: A size of a partition to be created on a storage device is limited to a size of m to n-th power, where m and n are natural numbers. In creation of the partition, a partition management execution unit is set to dispose the partition from a sector aligned with a size of the partition itself, thereby improving the utilization efficiency of the storage device can be improved.

Abstract: The pseudo-linear frame buffer mapping system and method facilitates the clearing of the frame buffer memory of a graphics display system by subdividing the region of the frame buffer which is to be cleared into a plurality of sub-regions and by initiating the clear command concurrently to each of the plurality of sub-regions.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A method increases the efficiency of a memory bank and greatly reduces the risk of erasure of frame data which are required for coding, decoding or display. FM1a, FM1b, FM2a and FM2b are the first frame area of the first image sequence, the second frame area of the first image sequence, the first frame area of the second image sequence and the second frame area of the second image sequence, respectively. AD12a and AD12b are the first address start location of the first image sequence and the second address start location of the first image sequence, respectively. The frame sizes SZ1a and SZ1b are reserved from the respective start locations toward higher addresses in the first image sequence, respectively. The frame sizes SZ2a and SZ2b are reserved from AD12b-SZ2a and AD34a-SZ2b toward higher addresses in the second image sequence, respectively.