Abstract: A system and method is provided for preventing the occurrence of aliasing at the edges of polygons in 3D graphics. The system may detect both polygon geometric edges and Z edges due to intersection of multiple polygons. In one embodiment, the system includes an edge anti-aliasing module configured to selectively super-sample edge portions of primitives. The system further includes a coarse memory for storing information of pixels that are not super-sampled and a fine memory for storing information of pixels that are super-sampled by the edge anti-aliasing module.

Abstract: A method and apparatus in a data processing system for processing a request to display a pattern. A plurality of partitions is created in a memory in a graphics adapter in the data processing system, wherein each partition within the plurality of partitions has a size equal to each of the other partitions within the plurality partitions. A determination is made as to whether the pattern is present within the plurality of partitions. The pattern is displayed using the plurality of partitions if the pattern is present within the plurality of partitions. The pattern is retrieved from another location if the pattern is absent from the plurality of partitions. Responsive to retrieving the pattern from another location, the pattern is stored if the pattern is within the size.

Abstract: A system and method is disclosed for management of sample data to enable video rate anti-aliasing convolution. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g. 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g. 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.

Abstract: A method for selecting and transmitting selected screen control data for screen displays of a terminal from a server to a client computer uses a first and second screen content array memory each comprising screen cells representing a given screen display. By selectively comparing the contents of the screen cells in the first and second screen content array memory an efficient transmission of selected screen control data from the server to a client computer is achieved.

Abstract: A method for enabling reduced transport display in a computer image generator connected to a host simulator which receives real-time input. The first step is performing real-time matrices calculations with the real-time input. The next step is processing geometry for primitives in a scene and storing the primitives in a double-buffered geometry buffer. The geometry buffer toggles as soon as the geometry processing is done without waiting for a field sync signal which reduces the transport delay normally found in image generation systems. Another step is rendering the primitives into a pixel frame buffer as soon as the geometry buffer toggles. The final step is displaying the pixel frame buffer. The rendering hardware and geometry processing hardware can also include enough processing power to complete the geometric transformations and rendering and in less than one display frame.

Abstract: A method and apparatus for providing a computer system having a plurality of logical partitions with a virtual operator panel is disclosed. The method and apparatus include displaying a plurality of operator panels on a single console corresponding to each of the logical partitions, and providing a buffer for each logical partition. The status codes from each of the logical partitions are then written directly to the corresponding buffer. To display the status codes of one of the logical partitions, the status code from the buffer corresponding the logical partition is read and sent to the corresponding operator panel for display.

Abstract: A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include all arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.

Abstract: The present invention divides a large graphics file into smaller “frames” of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

Abstract: A method for rasterizing a graphic primitive (120) in a graphics system generates, starting from graphic primitive description data, pixel data for the graphic primitive, the graphics system comprising a memory which is divided up into a plurality of blocks (a, a+1, b, b+1) which are each associated with a predetermined one of a plurality of areas on a mapping screen (114). Each block of the plurality of blocks (a, a+1, b, b+1) is associated with a memory page in the memory. The method includes scanning the pixels associated with the graphic primitive (120) in one of the plurality of blocks (a) into which the graphic primitive extends, repeating the preceding steps until all of the pixels associated with the graphic primitive have been scanned in each of the plurality of blocks into which the graphic primitive extends, and outputting the pixel data.

Abstract: A method of storing an array of digital data, for example, pixel data of a picture in a video bit stream, into a memory. In one embodiment, the memory includes a plurality of memory pages, and each memory page has a first memory section and a second memory section. The method includes a first step of dividing the array of digital data into a plurality of block units, while each of the block units has a plurality of odd rows and a plurality of even rows, and each of the odd rows and the even rows has at least one byte. The method further includes a second step of storing subsequent odd rows of at least one of the block units into consecutive storage locations in the first memory section, and storing subsequent even rows of at least one of the block units into consecutive storage locations in the second memory section. In this way, the memory bandwidth can be used more efficiently.

Abstract: Provided are a method and apparatus for accelerating graphic data which can reduce the computational complexity of graphic processing data. The method of accelerating two-dimensional graphic data includes: receiving information regarding the width of a graphic window to be processed; reading pixel data from a memory in which pixel data in the graphic window is stored; receiving information regarding two pixel data regions which are divided from the memory area based on the width information of the graphic window, one pixel data region to be processed using a burst mode and the other pixel data region to be processed in units of bytes; and individually performing predetermined graphic processing on the divided pixel data regions.

Abstract: In a memory consolidated image processing LSI for reading data, a DRAM for storing image data for a plurality of page ranges which are formed by segmenting an image plane corresponding to a display screen in order to page-access a memory region of the DRAM, and image data for a plurality of word ranges which are formed by segmenting each of the page ranges in order to word-access the memory region, is consolidated with an image processing circuit. The size of each of the page ranges is set so that the multiplied value of the power consumption per pre-charge in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value, and the size of each of the word ranges is set so that the multiplied value of the power consumption per word access in the power consumption model of the memory by an average number of word accesses is the substantially minimum value.

Abstract: A system and method for storing data in memory in either a packed or unpacked format contiguously and providing retrieved data in an unpacked format. The memory system includes a memory having packed and unpacked data stored in lines of data and a register to store a line of data it receives from the memory. Further included in the system is a selection circuit coupled to receive data from both the memory and the register. The selection circuit selects a portion of data from the lines of data presented to it by the memory and the register to be provided to a data bus according to a select signal provided by a memory address generator. The select signal is calculated by the memory address generator from an expected address at which the data is expected to be located. A second register and a second selection circuit may also be included in the memory system.

Abstract: A memory system includes a memory cache responsive to a single processing unit. The memory cache is arrangeable to include a first independently cached area assigned to store a first number of data packets based on a first processing unit context, and a second independently cached area assigned to store a second number of data packets based on a second processing unit context. A memory control system is coupled to the memory cache, and is configured to arrange the first independently cached area and the second independently cached area in such a manner that the first number of data packets and the second number of data packets coexist in the memory cache and are available for transfer between the memory cache and the single processing unit.

Abstract: A method and apparatus for updating video graphics changes of a managed server to a remote console independent of an operating system. The screen (e.g. frame buffer) of the managed server is divided into a number of blocks. Each block is periodically monitored for changes by calculating a hash code and storing the code in a hash code table. When the hash code changes, the block is transmitted to the remote console. Color condensing may be performed on the color values of the block before the hash codes are calculated and before transmission. Compression is performed on each block and across blocks to reduce bandwidth requirements on transmission. Periodically, the configuration of a video graphics controller and a pointing device of the managed server are checked for changes, such as changes to resolution, color depth and cursor movement. If changes are found, the changes are transmitted to the remote console.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: The invention relates to a method for displaying screen elements on a reproduction screen. A predetermined number of pixels (Pa1 . . . Pej) of a reproduction line (L1 . . . Lm) are combined to form a cell (C11 . . . Cmn). A reproduction line (L1 . . . Lm) is formed from a fixedly predetermined number of cells (C11 . . . Cmn).

Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system monitor. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.

Abstract: The process for storing, in pages of a memory, image blocks (h, v) consisting of v lines of h pixels, for the reading of image blocks (H, V) consisting of V lines of H pixels, is characterized in that the horizontal shift DI, I+a, in terms of number of blocks (h, v), of the boundary of a page corresponding to any row I of the image with respect to the boundary of a page corresponding to a row I+a is equal to: DI, I+a=a D, ∀ positive integer a less than RM=INT [(V−2)/v]+2, (INT corresponding to the integer part of the division) the value D, which corresponds to the shift between two successive rows being chosen such that: D≧(BM−1), with BM=INT [(H−2)/h]+2. Applications relate, for example to motion estimation and motion compression.

Abstract: An alternate display content controller provides a technique for controlling a video display separately from and potentially in addition to the content displayed on the operating system monitor. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces separate from the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.

Abstract: An overlay video processing system provides an early start to pixel processing for the next overlay scan line. The overlay processor begins processing the next overlay scan line while still displaying the current scan line. A FIFO buffer is used to provide the overlay video data to the display. When it is determined that the buffer is capable of storing the next overlay scan line, a memory read burst is triggered, and the buffer begins to load the data for the next overlay scan line.

Abstract: A method for interfacing to ultra-high resolution output devices. The basic idea of the present invention is to subdivide an ultra-high resolution display screen into narrow strips or column subsections, thereby enabling the mapping of multiple pixel interfaces to it. In this manner, the full pixel display is completely mapped. As such, multiple image generators are able to create in parallel their specific narrow strip of the full pixel display using view frustum culling, which is known by those of ordinary skill in the art. It should be appreciated that an interface in accordance with the present invention is not tied tightly to a scanning architecture. As such, this keeps a level of abstraction between the image generator and the many different types of display devices. Furthermore, since this interface is by design a rasterization interface, more image generators and less expensive image generators can be used for driving the display device.

Abstract: An airline-based video game system includes a multitasking master computer, which preferably stores video game and other application programs on its hard disk. The master computer is coupled to a set of airplane zone control computers which also perform conventional cabin management tasks. The zone control computers receive data from the master control computer and couple data to identified seat controlling processing units (SEBs). Each SEB receives data from, and couples data to, a set of unique seat display units which are associated with each seat in the airplane. The system downloads application software to the seat display units from the master computer. After receipt of a downloading request, the master computer responds by setting up an application program transmission for generating the display menu which appears on each SDU.

Abstract: A system and method is provided for supporting a multiple display configuration through a single connected display device. The present disclosure allows a system desktop to be expanded across multiple virtual displays without a need for extra hardware to support multiple display devices. A display driver partitions a frame buffer of a video card into portions. Each portion is used to support a different virtual display. The display driver reports a number of virtual displays to an operating system and provides pointers to addresses associated with the portions of the frame buffer. The operating system treats each frame buffer portion as a separate frame buffer and stores video data for each virtual display in an associated frame buffer portion. The display driver selects a virtual display from a set of multiple virtual displays and routes video data from the frame buffer portion associated with the selected display for output on a connected display device.

Abstract: A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.

Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Abstract: A method and system for concurrent processing of slices of a bitstream in a multiprocessor (MP) system is disclosed. The MP system includes a number of identical processors and a common memory. The memory is for receiving a plurality of bitstreams (preferably MPEG2 bitstreams) as a plurality of slices. The method and system comprises accessing a semaphore register by one of the plurality of processors and searching for an associated slice within the memory by the one processor. The method and system further comprises processing the associated slice by the one processor. Finally, the method and system comprises updating a memory location which holds the last address of the associated slice by the one processor; wherein subsequent processors search for each of the plurality of slices from the updated last address in the register. A system and method in accordance with the present invention provides for intercommunication between the plurality of processors within a multiprocessing system.

Abstract: A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM.

Abstract: High resolution image data is stored in multiple frame buffers to enable the image data to be coupled to multiple lower resolution video streams. Despite physical address discontinuities at frame buffer crossover boundaries, addressing of the multiple frame buffers as a single logical frame buffer is made possible by first dividing the image data into pages using a page size appropriate for both the video mode and arrangement of the physical frame buffers within the high resolution image. Then a pitch is determined for each of the physical frame buffers that enables the alignment of the memory pages at the frame buffer crossovers. Then for video modes utilizing multiple bytes per pixel, the collection of bytes representing the pixels are aligned on the page boundaries at the frame buffer crossovers. Then linear address space is reserved for storing a single high resolution frame buffer.

Abstract: A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region.

Abstract: An image memory has a random access memory array capable of being randomly accessed; a serial access memory array partitioned into n power of 2 (n>1) divisional areas cyclically and serially accessed in asynchronism with the random access memory; data transfer unit for transferring data between the random access memory array and the serial access memory array; a determined unit for determining a row of data to be transferred from the random access memory array to each of the divisional areas; and a designating unit for designating at least one of a top serial access address and a last serial access address respectively of each divisional area, wherein the data transfer unit executes data transfer from the random access memory array to the serial access memory array in accordance with outputs from the determining unit and the designating unit.

Abstract: An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.

Abstract: A virtual frame buffer controller in a computer's display system manages accesses to a display image stored in discrete compressed and uncompressed blocks distributed in physical memory. The controller maps conventional linear pixel addresses of a virtual frame buffer to pixel locations within blocks stored at arbitrary places in physical memory. The virtual frame buffer controller maintains a data structure, called a pointer list, to keep track of the physical memory location and compression state of each block of pixels in the virtual frame buffer. The virtual frame buffer controller initiates a decompression process to decompress a block when a pixel request maps to a pixel in a compressed block. The block remains decompressed until physical memory needs to be reclaimed to free up memory.

Abstract: In a display system having a predefined number, n, of pixel types, a display processor, such as a digital versatile disc (DVD) display processor, includes a color palette which can store more than n color/contrast values and a subpicture bitmap composed of subpicture pixel values, each of which corresponds to one of the n pixel types. In a DVD display system, for example, the DVD subpicture pixel types are: Background, Pattern, Emphasis 1, and Emphasis 2. Each subpicture pixel value is, in turn, related to a color/contrast combination by the color palette, with each pixel value corresponding to the address of a palette location. The corresponding palette location contains the color/contrast value for the related subpicture pixel type. To modify the color/contrast value of a selected group of the pixels having one of the four DVD subpicture pixel types, the display processor updates the color palette, associating new color/contrast values with previously “unused” palette locations.

Abstract: A system which utilizes dual-port memory to seamlessly display video frames on a raster scanned display device. Dual port memory is partitioned into a ‘single frame buffer’ having sufficient capacity to buffer a full video frame, and an ‘extension buffer’ which is a contiguous extension of the single frame buffer. The two sections together comprise an ‘extended buffer’. As long as the video memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than a predetermined number of lines, the incoming video data for the next several new frames is written using the ‘extended’ buffer, and also read therefrom. After the write and read addresses are again sufficiently separated, video data is written and read using only the single frame buffer.