Abstract: A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.

Abstract: A display driver circuit includes a receiver that receives a still image or a moving image, a frame buffer that stores the still image received by the receiver in a still image mode, an image processor that performs an image enhancement operation on the moving image transferred from the receiver or the still image transferred from the frame buffer, and a motion processor that performs a motion compensation operation using a current frame output from the image processor and a previous frame stored in the frame buffer in a moving image mode. The previous frame is data which, in the moving image mode, are processed by the image processor before the current frame and are then stored in the frame buffer. The previous frame is output from the frame buffer to the motion processor in synchronization with the current frame.

Abstract: Aspects of a storage device including a memory and a controller are provided which allows for reduced latency of read-modify-write operations when a data length from a host is unaligned at two ends with a write length of the controller. When the controller receives from a host device a write command for data, the controller performs a first read of a head portion and a second read of a tail portion immediately after performing the first read. The controller performs a single L2P translation of one of the head or tail portions, senses the data associated with the head and tail portions once into latches, and reads the data from the latches for both the head and tail portions without performing another data sense. The controller then writes the data in response to the write command after performing the first read and the second read.

Abstract: A data storage apparatus, storage medium and method for controlling the data storage apparatus are disclosed in which duplicates of a plurality of data blocks, which are stored in two or more media in a first arrangement and classified according to a plurality of pieces of dimension information, are stored into two or more other media in a second arrangement different from the first arrangement. A data block may be classified into first class data or second class data of a first dimension information or a second dimension information. A processor may store duplicates of first and third data blocks into a third medium, and duplicates of second and forth data blocks into a fourth medium. This can reduce the number of times of changing a medium, and suppress lowering in the capacity efficiency. Dimension information may be an axis of obtaining data.

Abstract: A display apparatus including a display configured to display a pointing object, a communicator configured to perform communication with a remote control device which recognizes a movement and transmits a signal corresponding to the recognized movement, and a processor configured to control a moving state of the pointing object based on the signal received from the remote control device. The processor controls the moving state of the pointing object according to a relative coordinate method for a first area where a screen of the display is included, and controls the moving state of the pointing object according to an absolute coordinate method for a second area outside the first area.

Abstract: Examples allocate and schedule use of graphics processing unit (GPU) resources among a plurality of users executing virtual machines (VMs) or processes. During initialization, shares representing proportional access to the GPU resources are assigned and then adjusted based on graphics command characteristics. Quantum is allocated among the VMs based on the shares. At runtime, graphics commands from the VMs are queued and iteratively sent to the GPU based on a comparison between allocated quantum and a threshold quantum. In this manner, the GPU resources are fairly shared among the VMs.

Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

Abstract: One or more resources for an SoC can be directly mapped to a host address space in a host system as peripheral bus functions. A translation unit can provide translation between the host address space and an SoC address space for transactions targeted for a resource from the one or more resources to facilitate performing the transactions with the resource using the host address space. Some embodiments of the technology can provide peer to peer capability for communication between the SoC resources using the translation unit.

Abstract: Various techniques are provided to capture one or more thermal image frames using an infrared sensor array that is fixably positioned to substantially de-align rows and columns of infrared sensors. In one example, an infrared imaging system includes an infrared sensor array comprising a plurality of infrared sensors arranged in rows and columns and adapted to capture a thermal image frame of a scene exhibiting at least one substantially horizontal or substantially vertical feature. The infrared imaging system also includes a housing. The infrared sensor array is fixably positioned within the housing to substantially de-align the rows and columns from the feature while the thermal image frame is captured.

Abstract: A method for cropping portions of a document comprises displaying an interactive document workspace with a cropping tool on a sub-area thereof, and rendering one or more formatting indicators spatially associated with the sub-area, the indicators indicating formatting properties of the sub-area.

Abstract: A method of controlling polishing of a substrate is described. A controller stores a library having a plurality of reference spectra. The controller polishes a substrate and measures a sequence of spectra of light from the substrate during polishing. For each measured spectrum of the sequence of spectra, the controller finds a best matching reference spectrum from the plurality of reference spectra and generates a sequence of best matching reference spectra. The controller uses a cell counting technique for finding the best matching reference spectrum. The controller determines at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra.

Abstract: A visual debugger provides a three-dimensional view of a user interface of an application. The application's user interface is built from a hierarchy of view objects. The hierarchy of view objects can be displayed as a three-dimensional representation of the view. A set of layers is created, with each layer corresponding to a level in the hierarchy of view objects. The display device on which the application runs has a view area in which the user interface (“UI”) of the application can be displayed. The visual debugger presents a visual representation of the view area for the UI to the application developer. The view bounds are shown as an outline on one or more layers of the three-dimensional representation of the view. Objects outside of the view bounds are highlighted. The visual debugger allows the application developer to select the layer or layers on which the outline appears.

Abstract: Described herein is a system and method that relates to mapping from one color space on a 3D cube to another, and an addressing method used to represent the data. The system organizes the data to reduce memory storage requirements, by re-using redundant information from different cube corners in a lattice structure without re-storing the same data. The lattice structure may repeat for every cube of interest.

Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract: A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream.

Abstract: A memory control device is adapted to derive a two dimensional location on a graphic display surface from address signals of a graphics processing unit (GPU), and to compare the derived two dimensional location to a two dimensional range of authorized locations corresponding to a subset of the display surface; and to modify the address signals of the graphics processing unit (GPU) if the address signals do not fall within the two-dimensional range of authorized locations corresponding to a subset of the display surface, and to propagate the address signals unmodified to a display memory otherwise.

Abstract: Methods, systems, and apparatus, including computer program products, for communicating information. An event is detected. A light effect is emitted in response to the detected event. The emitted light effect simulates the detected event or a sensory output associated with the detected event.

Abstract: A data transfer circuit that transfers a first kind of data stored in an external memory circuit includes: an internal memory circuit that is capable of, by an external circuit, writing and/or rewriting a second kind of data including information for one region as a transfer source in the external memory circuit and another region as a transfer destination in the external memory circuit; a transfer circuit that transfer the first kind of data; and a control circuit that makes the transfer circuit transfer the first kind of data stored in the one region to the other region based on the second kind of data.

Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

Abstract: A rendering process for rendering an image frame and a postprocess for adapting the image frame to a display are separated. A rendering processing unit 42 generates an image frame sequence by performing rendering at a predetermined frame rate regardless of a condition that the image frame should meet for output to the display. A postprocessing unit 50 subjects the image frame sequence generated by the rendering processing unit to a merge process so as to generate and output an updated image frame sequence that meets the condition. Since the rendering process and the postprocess are separated, the image frame sequence can be generated regardless of the specification of the display such as resolution and frame rate of the display.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract: Disclosed is an image processing apparatus for inputting a plurality of rectangular images each composed of n×n pixels and outputting line-by-line image data in which one line is composed of n×n×m pixels. A line buffer stores n lines of image data, each line is composed n×n×m pixels. The apparatus generate a write address for writing a rectangular image to the line buffer memory and a read-out address for reading line-by-line image data out of the line buffer memory, and changes over a method of generating the write address between a first write-address generating method and a second write-address generating method whenever m rectangular images are written to the line buffer, and changes over the read-out address between a first read-out-address generating method and a second read-out-address generating method whenever n lines of image data are read out of the line buffer.

Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

Abstract: The present invention relates to a mobile terminal technology. The present invention discloses a method for processing information displayed on a touch screen of a mobile terminal, and said method comprises steps of: determining whether a touch gesture received by the touch screen is made by at least two contact points; determining whether sliding motions made by each contact point onto the touch screen satisfy criteria set in the mobile terminal; deleting the information displayed on current interface; wherein the criteria are that the at least two contact points on the touch screen are slid parallel to each other, associated sliding motions for each contact point are oriented in opposite directions, and an angle between the associated sliding motions is within an angle threshold. The present invention can delete the information displayed on the interface quickly and conveniently and improve the interactivity of the mobile terminal and the user.

Abstract: Apparatus, systems and methods for handling portrait mode oriented display surfaces without requiring expensive hardware in the display sub-system are disclosed. For example, an apparatus is disclosed such that the rendering of graphics data to the portrait mode display surfaces is redirected at rendering time such that there is no need for adding complicated hardware in the display part of the graphics adapter in order to handle conventional displays—all of which have no circuitry to deal with data natively stored in a portrait mode surface. Additionally, an apparatus to handle direct surface access of a surface through a surface lock which has already been rotated is already described. This can either be done by copying of surface data or by an optimized proposed apparatus which eliminates this copy. Other implementations are also disclosed.

Abstract: A data processing system may include a display, the display having a display surface, and logic to modify the address signals of a graphics processing unit (GPU) if the address signals do not fall within a two-dimensional range of authorized pixel locations corresponding to a subset of the display surface, and to propagate the address signals unmodified to a display memory otherwise.

Abstract: In accordance with one aspect of the invention, a mobile communication terminal comprises a first display and a second display and a user interface for allowing a user to select one or more images to be displayed on either of the first and second displays, wherein images displayed on both the first and the second display are viewable from a first viewing angle.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device has a display memory capable of storing display data in a storage area, and a repair circuit capable of repairing a defect by replacing an area including a defect in the display memory with a spare storage area provided on the outside of a regular storage area for storing the display data. The device further includes a selector circuit provided on a transmission path of output data from the display memory and selectively replacing output data from the regular storage area with output data from the spare storage area in accordance with a control signal from the repair circuit. By selectively replacing the output data from the regular storage area with output data from the spare storage area in accordance with a control signal from the repair circuit, a defective bit is repaired.

Abstract: A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to the selected part of the memory address, and transfers the data, for which it is determined that the first memory does not store the data, and which corresponds to the part of the memory address, from a second memory to the first memory. The data processing apparatus determines to change a part to be selected of the memory address based on the checking result indicating that the first memory does not store the data corresponding to the selected part of the memory address, and changes the part of the memory address corresponding to the characteristics of the memory address.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: A graphics system has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. In one implementation, the memory elements are dynamic random access memories (DRAMs) and the system supports having a non-power of two number of active DRAMs.

Abstract: Disclosed are an information processing apparatus and method, a recording medium and a program, by which an image can be fetched in a size appropriate to a user. An image of a subject picked up by a camera is displayed in a predetermined first range corresponding to a size designated in advance within a predetermined display region of an LCD unit which corresponds to an image pickup range of the camera, but the image of the subject picked up by the camera is not displayed in a surrounding range of the predetermined display region around the first range. If a shutter button is depressed in this state, then the image displayed in the first range is stored in the designated size into a memory. The present invention can be applied typically to a PDA, a mobile terminal, a portable telephone set, a desk-top personal computer or the like which has a function as a digital camera.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: Method for reversing a video signal having sequences of n elements comprises the steps of writing the n elements of a first sequence into memory locations of a memory in a non-reversed order and reading out the memory locations in a reversed order, and in a subsequent step, writing the n elements of a second sequence into the memory locations in a reversed order and reading out the memory locations in a non-reversed order. The memory locations are readout from the memory in particular one element ahead of the write locations of the memory. A method of this kind can be used in particular in a television camera comprising a lens unit, which is designed for film applications.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: A display controller includes a memory storing at least three frames of image data, a write starting address register to which a write starting address is set, a read starting address register to which a read starting address is set, and a rotation control section performing control for reading out from the memory image data corresponding to an image whose orientation is rotated. When writing of the image data to the area designated by the write starting address is completed, the write starting address is updated and the previous value of the updated write starting address is set to the read starting address register. The image data corresponding to the rotated image is read out by the rotation control section 40 from an area of the memory designated by the read starting address, and then supplied to a display driver.

Abstract: A method of storing a digital image in a computer memory includes providing a N-dimensional digital image, defining an offset for each image element (x1, . . . , xN) by the formula offset ? ( x 1 , … ? , x N ) = ? i ? ? n = 1 N ? K x n ? ( i ) ? x ni , where i is summed over all bits and n is summed over all dimensions. The coefficient K for the ith bit of the nth dimension is defined as K x n ? ( i ) = ( ? j = 1 n - 1 ? f ? ( x j , 2 i + 1 , sx j ) ) ? 2 i ? ( ? j = n + 1 N ? f ? ( x j , 2 i , sx j ) ) , where xj is the jth dimension, f(x,G,sxj)=min(G,sxj??x?G) G is a power of 2, sxj represents the size associated with a given dimension, and ?x?G=x?x mod G. Image elements are stored in the computer memory in an order defined by the offset of each image element.

Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.

Abstract: A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: Embodiments include storing graphics instructions at addresses in a memory in an original order, and storing in the memory pointers associated with each instruction pointing to the addresses of the instructions in the original order. A first pointer associated with a first graphics instruction may then be moved from pointing to a first address of the first graphics instruction to point to a second address of a second graphics instruction. Likewise, a second pointer associated with the second graphics instruction may be moved from pointing to the second address to point to the first address by accessing the first pointer before moving the first pointer to determine that the second pointer is to point to the first address (e.g., the address the first instruction points to before being moved). Afterwards, the instructions may be re-ordered into an optimized order for compiling, by switching them to different addresses according to the pointers.

Abstract: A memory write section 2 writes texture data in a number capable of being transferred at a time and written in one address, in one of first through fourth texture memories 1a through 1d in common by single write operation. If the V coordinate of texture data to be written is an even number, the texture data is written in the first, second, third and fourth texture memories 1a, 1b, 1c and 1d in this order. If the V coordinate is an odd number, the data is written in the third, fourth, first and second texture memories 1c, 1d, 1a and 1b in this order.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: An original media object, such as an image, is edited without loss of the data comprising the media object. Changes applied to the media object are defined by metadata associated with the media object. For example, metadata define the cropping of an original JPEG image without loss of the original image. The metadata from a previous editing session can be used to further revising a change to the media object. Preferably, the metadata are stored as a stream in a substorage of an object linking and embedding (OLE) file. For display purposes, and for ease of modification, an edited version of the media object is stored as another stream of data in the substorage of the OLE file. The edited version of the media object is preferably compressed and serves as an intermediate object for faster display during editing and as a surrogate if the original media object is unavailable.

Abstract: A mobile communication terminal comprising a display and a keypad having plural keys. The keypad comprises a frame surrounding the display and the keys are arranged at respective key positions on the frame. The terminal is further configured to display symbols at positions on the display corresponding to the key positions on the frame. Furthermore, said frame is arranged to be rotated between at least a first and a second position whereby each said key becomes associated with a respective first and second operation of the terminal.

Abstract: A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.