Abstract: Data temporarily stored in volatile memory (e.g., RAM) on a host machine can be protected using a component such as an NV-DIMM, which includes components such as an ASIC, non-volatile memory, and a battery. If power is lost to the host, the battery provides the ASIC with the power needed to determine data in the volatile memory that is protected. This protected data then can be transferred to the non-volatile memory on the NV-DIMM. When power is restored, an application or other entity can contact the NV-DIMM to recover the data, which can be transferred over a sideband channel to be restored as appropriate for a prior operation. In at least some embodiments, the NV-DIMM can receive a key over the sideband channel that can be used to encrypt and decrypt the data for further security.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: While a plurality of encoding blocks included in a micro dotmap are used for marking coordinates and locating a frame center on a displaying medium, a resolution of locating the frame center is raised by finding a microdot having a shortest distance from the frame center respectively in two microdot sets of a header region, or by determining a distance scale between an origin of the encoding block and each of two parallel projection points of both the microdot sets corresponding to the frame center. Both the microdot sets correspond to different dimensions in representing the coordinate of the frame center. The closest one-dimensional coordinates are then combined to form a two-dimensional coordinate of the frame center. Therefore, while applying the abovementioned method on a touch screen manipulated with touches of an optical pen, movements of the frame center on the screen can be manipulated skillfully by a user.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to the selected part of the memory address, and transfers the data, for which it is determined that the first memory does not store the data, and which corresponds to the part of the memory address, from a second memory to the first memory. The data processing apparatus determines to change a part to be selected of the memory address based on the checking result indicating that the first memory does not store the data corresponding to the selected part of the memory address, and changes the part of the memory address corresponding to the characteristics of the memory address.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memory in accordance with a first memory address allocation format and the memory addresses are decoded to access the addressable memory locations of a second block of memory in accordance with a second memory address allocation method different from the first memory address allocation format.

Abstract: A fully programmable graphics processing engine is provided. The graphics processing engine includes three independent, programmable processors that run independent sets of instructions from independent instruction storage facilities. Graphics processing tasks may be distributed among the serially pipelined processors to allow for load balancing and parallel processing. The graphics processing engine may be a graphics co-processing core within a larger, general purpose computing system. Register files and storage units may be addressable by the system host processor. Each processor accepts incoming data for state or context updates. Each processor may execute a specific graphics processing function by executing a set of instructions when a predetermined memory address is accessed.

Abstract: A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device with a minimal number of selection inputs required for selection of a desired memory area.

Abstract: A bus compression apparatus for compressing data is provided to suppress an EMI signal and to simplify a data bus structure. In the apparatus, the voltage levels of the digital output signals are summed in accordance with the resistance values of the data compression circuit to produce a compressed analog signal. The compressed analog signal is transmitted through a bus lines to a data decompressor which reproduces the digital data in response to the voltage levels of the compressed analog signal.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module.

Abstract: Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

Abstract: A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real time operation, including a memory array comprised of a matrix of a plurality of memory units each having two memory cells adjacent to each other in the same row, one flag cell, and two transfer gates for transferring flag data of the flag cell to the flag cells of the memory units adjacent in a row direction and a column direction in accordance with the stored data of each memory cell and including a region growing circuit for writing correlation data as results of operation of correlation of adjacent pixels into all memory cells, starting the region growing processing from a designated position (address) to extract an object, and outputting the same to an image combining unit.

Abstract: A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the audio decode processor. The video transport-processor stores the video data in external memory and generates a start code table to index the video data stored the external memory. In the start code table SLICEs of the video data are aligned to a suitable boundary. The compressed data streams may include MPEG Transport streams, and the video data may include SDTV or HDTV data. The video and graphics system may be implemented on an integrated circuit chip.

Abstract: A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode device, a frame buffer range device and a command routing device. The frame buffer range device is used to determine if the access address pointed to a graphic memory. The command-decoding device and the compare logic device are used to determine if the access address points to a memory bank range having an error-check-correction function. The decision device is used to determine if the access address points to a memory bank range having error-check-correction function but outside the graphic memory range. If the access address points to a memory bank range having error-check-correction function but outside the graphic memory range, a memory access command with error checking and correction of data is executed.

Abstract: A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control data. The register may be associated with the block move engine and configured to control the block move engine, in response to the control data. The reader may be configured to read the control data from the memory and apply the control data to the register.

Abstract: A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put together into a data block having a predetermined transfer destination data size. This enhances the efficiency of data transfer from a software program for processing data in several byte units to a memory and a coprocessor optimized for data transfer in block units of several tens of bytes, and thus improves system performance.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data using an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the access to the graphics data pointed to by the selected virtual register.

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD, /WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.

Abstract: A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The compressed data streams may include in-band and out-of-band MPEG Transport streams. The video and graphics system processes the PES into digital audio, MPEG video and message data. A core transport processor includes a PCR recovery module for extracting PCRs contained in the compressed data streams and for providing the extracted PCRs to a video transport processor and an audio decode processor. The PCR recovery module has a direct load capability for receiving user defined PCRs and outputting them instead of outputting the extracted PCRs. The PCR recovery module extracts PCRs from both MPEG Transport streams and DIRECTV transport streams.

Abstract: A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. . The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.

Abstract: Timing signal selection section 124 outputs a frame timing signal output from timing signal generation section 123 to drive section 128 and outputs a read timing signal, which controls timing of reading image data stored in storage section 126 and supplying the image data to drive section 128, to image reading section 127. When a read timing signal is output from timing signal selection section 124, image data reading section 127 reads the image data from storage section 126 according to the timing indicated by the read timing signal and outputs the image data to drive section 128. Drive section 128 outputs the image data to image display section 129 according to the timing of the frame timing signal output from timing signal selection section 124.

Abstract: A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: An orthogonal memory is described that provides an improved method for converting image data into a bit plane format suitable for image compression operations, using a custom dual port memory. The memory comprises a matrix of memory cells that are addressable in orthogonal directions. Upon receipt of image information for storage, the image information is stored in the memory by storing each data word of the image information in a row of the matrix. Individual bit planes of the image information may be easily retrieved from the memory by retrieving individual columns of bits from the corresponding columns of the matrix, thus providing a highly efficient method for storing and accessing image information used to create bit planes.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons during texel accessing. A mipmap page number is generated for texture data of interest. A page residence bit is then selected responsive to the mipmap page number. If the page residence bit is in a first state, then the texture data is retrieved from a memory located within the graphics subsystem; but if the page residence bit is in a second state, then the texture data is retrieved from system memory. System-wide texture offset addressing obviates the constraints associated with fixed relative addressing schemes.

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD,/WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.

Abstract: The present invention relates to a display memory control apparatus which can shorten a waiting time in making an access to a VRAM from a CPU without making large a circuit scale and causing an increase of power consumption. A data width of a VRAM is previously set to plural times as much as a data bus width of a CPU. A write data from the CPU is temporarily stored in a pre-buffer, and is transferred to one of data buffers included in a write buffer. The data buffer is specified by a low-order address. A VRAM control circuit can write all data or data of arbitrary combinations from data buffers into an address of VRAM specified by a high-order address buffer by one-time access.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.