Abstract: Disclosed are systems and methods for determining the logarithmic transfer function of a plurality of analog signals using digital circuitry components. The apparatus is a digital crystal video receiver that includes an analog-to-digital converter and a programmable logic component that determines the logarithmic transfer function of plurality of signals. The programmable logic component may include a FPGA, microprocessor, macroprocessor, combinations of discrete logic components, etc. The programmable logic component includes memory having one of a look-up table and an instruction set that enables the programmable logic component to process or calculate a signal that is logarithmically proportional to the plurality of signals.

Abstract: A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

Abstract: A digital and analog television signal digitization and processing device that performs the digitization and processing functions using a common reference frequency source that is used to generate multiple subclock signals, wherein the reference frequency source is independent of any synchronizing characteristic of the input signal. For dual channel analog signal processing, the common frequency source is not locked to either channel/input signal. Digital signal processing is accomplished based on the same common reference frequency source. Advantageously, the present invention allows all of the analog-to-digital converters and decoder circuitry/logic necessary for simultaneously digitizing and processing several analog and digital television signals to be integrated on a single integrated circuit as well as eliminating duplicate frequency generation circuits.

Abstract: A calibration device for a video circuit input stage comprises an analog-to-digital converter and an input capacitor constantly discharged by a power source and recharged by a charging circuit by means of a first and a second charging current. The charging circuit is controlled by a central processing unit receiving an estimate of the variation between the converter's output code and a clamp value.

Abstract: A method and apparatus for estimating a true horizontal resolution by determining a temporal spacing of a cumulated sum pattern of a detected rising feature edge. If the temporal spacing is approximately equal to n (which is a positive, non-zero integer, and is equal to the number of sub-pixels associated with a pixel) then the estimated horizontal resolution is the true horizontal resolution.

Abstract: An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Abstract: A software decoder for converting standard composite video to RGB color components without a phase-locked loop. Subcarrier phase recovery for each video line is accomplished by performing a single DFT computation on the color burst samples for the frequency closest to the subcarrier frequency. The recovered subcarrier phase is added for each line to the orthogonal subcarriers which are mixed with the modulated chrominance for decoding of color difference signals I and Q. Digital composite video capture and store circuitry may be used to buffer the acquisition of real-time video to the speed of a DSP used for software processing. Interpolation can be used in the processing of digital composite video to improve vertical line alignment. Multiple composite video formats, such as NTSC and PAL, can be decoded with minor modifications in the software decoder operation.

Abstract: An image signal recovering apparatus for converting a composite signal and a component signal of a main picture and a sub picture into digital signals, including: a composite selecting unit which selectively outputs at least one of a plurality of composite signals inputted through first input ports of the composite selecting unit; a component selecting unit which selectively outputs at least one of a plurality of component signals inputted through second input ports of the composite selecting unit; a first converting unit for converting composite signals from the composite selecting unit into digital signals; a second converting unit for converting component signals from the component selecting unit into digital signals; and an input switching unit positioned between the component selecting unit and the second converting unit, for selectively switching composite signals from the composite selecting unit and component signals from the component selecting unit into the second converting unit.

Abstract: An analog Y signal input from an input terminal 101 is clamped at a pedestal level in a clamp circuit 102, and then, is converted to a digital image signal in a quantization circuit 103. The pedestal level Dp of the digital output D(t) 113 is stored in a register 702. A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter 802. The subtraction output 806 is subtracted from the digital output 113 in a subtracter 803. The subtraction output 805 (D(t)?(Dp?Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuit 102 and the quantization circuit 103 has been compensated for. The subtraction output 805 is limited to a predetermined dynamic range by an overflow limiter circuit 807, and output as Dout.

Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.

Abstract: A chroma-decoder 1 has two SRCs 17 and 21. The first SRC 17 performs down-conversion, changing the sampling rate of a composite video signal sampled with a system clock signal Cs to the sampling rate (14.3 MHz) of an NTSC signal. The signal generated by the SRC 17 is output in synchronism with the system clock signal Cs. The signal is then divided into a luminance signal Y and a color-difference signal C, which are subjected to chroma decoding. The second SRC 21 performs down-conversion, changing the sampling rate of the luminance signal and color-difference signal of the NTSC signal to the sampling rate (13.5 MHz) of an ITU-R601 standard.

Abstract: A digital video signal processing system monitors the rate of change of the digital video signal to detect large rates of change that indicate the presence of an object edge in the video image. Upon detection of such an edge, the digital signal is sampled at a variable rate so that more sampling is performed immediately before and after the sudden change in the signal and less sampling is performed during the change. The result is that the edge in the video image occupies less pixels and, therefore, is more clear and defined that would be the case otherwise. Consequently, the appearance of the video image is enhanced. This can be considered as the digital analogue of analog H-sweep velocity modulation.

Abstract: Apparatus and method are provided for using a multi-element field emission cathode in a color cathode ray tube. The field emission cathode may have from four to ten field emission arrays linearly arranged. The arrays are preferably formed from carbon-based material. An electron gun assembly focuses electron beams from each array on to a phosphor stripe or dot on the screen of the cathode ray tube. Deflection apparatus moves the beam from each field emission array according to clock signals. Clock signals also turn on or turn off voltage to contacts controlling electron current from the array. Values of voltage applied, determined by a video signal, determine the intensity of electron current from each array, which controls the intensity of the light emitted by each color stripe or dot of phosphor on the phosphor screen.

Abstract: A video signal sampling apparatus for sampling an input analog video signal by use of a sampling clock, and producing a digital signal which represents a level of a resultant video signal sample as a digital video signal is disclosed. The video signal sampling apparatus includes N (N being an integer equal to or greater than 2) converters for sampling the input analog video signal by use of N sampling clocks having phases that are different from each other to produce N digital signals which represent levels of N resultant video signal samples respectively, and a selector for selecting one digital signal from the N digital signals produced by the N converters in order that an amplitude of the digital video signal output to the outside is maximized.

Abstract: One preferred embodiment of the present invention provides a phase adjusting method of an A/D video signal conversion. A plurality of phase references is applied to convert a number of analog video frames to a number of digital video frames. For each phase reference, an absolute display difference is obtained by adding up absolute differences between corresponding pixels that are at positions in the digital video frames. A target phase reference that produces a smallest absolute display difference is applied to convert a follow-up analog video frame, and a stable high quality digital display is obtained.

Abstract: Disclosed are an apparatus and method for outputting digital video data in a display appliance. The digital video data outputting apparatus includes data converting units for converting various kinds of analog video signals into digital video data, an output signal selector for receiving outputs of the data converting units and selecting any one of the received outputs, and an encoding unit for encoding the output of the output signal selector.

Abstract: A PLL architecture with fast phase acquisition, a stable freerun output frequency, and post-freerun fast phase recovery. The invention is particularly well suited for use in a video graphics a/d conversion circuit. An intelligent phase lock loop is optimized to determine the time difference between the closest rising edge of an PLL output signal and the rising edge of an input signal. The time difference in combination with the current PLL lock state determine an operational code used in a digital signal processing loop filter used to control a digitally controlled oscillator. The PLL also provides a stable output frequency during freerun periods, and a phase booster circuit for post-freerun fast phase recovery.

Abstract: A method and apparatus for adjusting the amplitude and DC bias of a video signal is presented, which may be performed in preparation for analog-to-digital conversion. This is accomplished by first converting a received voltage mode video signal to a current mode video signal. Similarly, a voltage mode bias control signal is converted to a current mode bias control signal. The amplitude of the current mode video signal is then adjusted to produce an amplitude adjusted video signal. Similarly, the amplitude of the current mode bias signal is adjusted to produce an amplitude adjusted bias control signal. The current mode amplitude adjusted signals are then combined to produce a biased adjusted current mode video signal. The biased adjusted current mode video signal is then converted back to a voltage mode signal, which may be provided to an analog-to-digital converter for conversion.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: An A/D conversion apparatus of a digital video system includes an A/D converter for converting an input analog video signal to a digital signal on the basis of a reference voltage value input from the outside and outputting the digital signal; and a reference voltage supplying portion for supplying the A/D converter with a predetermined number of the reference voltage value sequentially and repeatedly during a predetermined time period. Accordingly, since the quantization error can be minimized during the A/D conversion in the digital video system without increasing the number of the quantization bits, the image quality can be improved.

Abstract: A color video display signal processor comprises a source of a color difference signal and an analog to digital converter for converting the color difference signal to a digital signal. A potential divider is coupled to reference voltages of the analog to digital converter for generating a clamp voltage. A clamp arrangement is coupled to the color difference signal and to the analog to digital converter and receives the clamp reference voltage. In response to a clamp pulse the clamp arrangement couples said clamp voltage to said color difference signal.

Abstract: An apparatus and a method for signal processing in a digital video system. The apparatus for signal processing of a digital video system has: an input unit to receive a signal quantized for M bits; and an output unit to output a value of A for (2M-N−B)times and a value of A+1 for B times during vertical scan of 2M-N times when a decimal value of high N bits is A and a decimal value of low bits of (M-N) excluding N bits is B and M>N. Accordingly, as an image signal quantized with a greater number of bits is displayed on a screen with a lesser number of bits, the quality of a picture can be improved.

Abstract: In a method and apparatus for transmitting a video signal, parallel digital video signals output from a graphic controller of a computer are transmitted to a driver of a cathode ray tube monitor by converting the parallel digital video signals to serial digital video signals, transmitting the converted serial digital video signals to the cathode ray tube monitor via a cable, converting the transmitted serial digital video signals to serial analog video signals, and inputting the converted serial analog video signals to the driver of the cathode ray tube monitor.

Abstract: A display interface is arranged to processes analog input signals to provide digital output signals. The display interface includes a series of programmable current sources, an input buffer circuit, a first reference buffer circuit, a second reference buffer circuit, and an analog-to-digital converter. The programmable current sources are arranged to provide first and second reference signals, which are buffered by reference buffer circuits and provided to the analog-to-digital converter. The input buffer circuit provides a buffered input signal to the analog-to-digital converter, and operates in an open-loop configuration for improved operating speed. The analog-to-digital converter is configured to provide a digital output signal (DOUT) in response to the buffered input signal. The analog-to-digital converter includes gain and offset settings that are changed by adjusting the progranmnable current sources. The programmable current sources and reference buffer circuits are outside of the input signal path.

Abstract: The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal is converted into a digital signal by an analog-to-digital converter. The digital signal is then converted into an analog signal having an alternating frequency by a first converter processor and an alternating frequency generator according to a predetermined conversion table. To reproduce the original analog signal, the analog signal having an alternating frequency is first converted back into a digital signal by an alternating frequency measurement means connected to a second converter processor, also in accordance with the predetermined conversion table. The digital signal is then converted to the original analog signal by a digital-to-analog converter.

Abstract: A calibration device for a video circuit input stage comprises an analog-to-digital converter and an input capacitor constantly discharged by a power source and recharged by a charging circuit by means of a first and a second charging current. The charging circuit is controlled by a central processing unit receiving an estimate of the variation between the converter's output code and a clamp value.

Abstract: The present invention provides a technique that facilitates A-D conversion and D-A conversion of high-frequency image signals. Three A-D converters 71 through 73 successively carry out A-D conversion of an analog image signal AV1, in response to three sampling clock signals SAD1 through SAD3, which respectively have a frequency that is ⅓ of a frequency of a dot clock signal DCLK1 and phases that are sequentially shifted by a period of the dot clock signal DCLK1, thereby generating three digital image signals D1 through D3 with respect to three consecutive pixels. The digital image signals for the three pixels are written into consecutive storage areas in a frame memory 26. Reading operation of an image signal from the frame memory 26 is also carried out at a frequency that is ⅓ of a frequency of a read dot clock signal. The working number of A-D converters and the working number of D-A converters are regulated according to the frequency of the analog image signal.

Abstract: A method for initializing a counter within a corresponding set of A/D converters of N sets of A/D converters of a single-chip CMOS-type image sensor in order to minimize none uniformity across the N sets of A/D converters is provided. The single chip CMOS type image sensor includes an image sense array having N columns of output lines for outputting N analog signals respectively; and a signal process device for generating N sets of digital signal each of which corresponds to one of N analog signals respectively. The signal process device has N input lines and N sets of A/D converter each of which including a counter for generating one of the N sets of digital signal respectively. The method comprises the steps of applying a predetermined reference voltage at each of N input lines of the signal process device such that a compensation value corresponding to each set of A/D converter is obtained.

Abstract: An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Abstract: The invention relates to a method for converting analog video signals to digital video signals, in which

Abstract: A method and an apparatus for generating a coast signal for enabling or disabling a phase comparator in a phase-locked loop of image processing apparatus. The phase-locked loop generates a sampling clock signal, which is used to convert an analog image signal into a digital image signal in response to a composite sync signal including a vertical sync signal and a horizontal sync signal. An enabled coast signal is generated at period other than detected horizontal sync period to prevent the phase comparator from comparing the composite synce signal to a reference signal, and a disabled coast is generated at periods corresponding to the horizontal sync period to permit the phase comparator to compare the composite synce signal to the reference signal.

Abstract: A sampling system adapts the sampling rate for sampling analog signals and/or the stored number of samples to the fixed or video image content, such that a higher rate, and equivalently a larger number of samples, are acquired for an image or video segment containing higher spatial frequencies while a lower number of samples (lower sampling rate) are retained for image or video segments containing lower spatial frequencies. The Nyquist theorem may still be satisfied for each individual image segment, while information necessary for edge enhancement is retained.

Abstract: Methods and apparatus for reducing the artifacts associated with still frame display and video capture of interlaced video are provided. Tuner 100 receives an interlaced video signal having an image frame with first and second fields. Motion detector 55 detects whether motion is present between the first and second fields. Memory 40 stores one or both of the fields for processing when motion is detected. Processor 30 processes the stored field(s) to provide an image frame with reduced artifacts. Various processing techniques are provided to generate the image frame from the stored field(s), without duplicating the stored field for use as the other field. Memory 40 stores the image frame. If motion is not detected, the first and second fields are both stored to provide the image frame. The stored image frame can then be continuously displayed to provide still frame display, or can be captured for subsequent use.

Abstract: A method of recovering a pixel clock for generating a digital image from an analog video signal is presented. The on and off-transition times for the active video portion of a digital image and the image size defined in a video standard are used to generate a pixel clock. The analog video signal is digitized according to the pixel clock and the image size of the resulting digital image is compared with the image size defined in the video standard. The pixel clock frequency is adjusted in response to the image size comparison. The optimum phase of the pixel clock relative to the analog video signal is determined through a repetitive phase adjustment technique. A first image coordinate is determined for a pixel clock at one phase and a subsequent image coordinate is determined for a pixel clock after decrementing the phase of the pixel clock. The first image coordinate and the subsequent image are compared.

Abstract: An analog Y signal input from an input terminal 101 is clamped at a pedestal level in a clamp circuit 102, and then, is converted to a digital image signal in a quantization circuit 103. The pedestal level Dp of the digital output D(t) 113 is stored in a register 702. A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter 802. The subtraction output 806 is subtracted from the digital output 113 in a subtracter 803. The subtraction output 805 (D(t)−(Dp−Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuit 102 and the quantization circuit 103 has been compensated for. The subtraction output 805 is limited to a predetermined dynamic range by an overflow limiter circuit 807, and output as Dout.

Abstract: An apparatus for converting analog stroke display signals representing electron beam generated stroke traces into raster display information for producing a raster-scan image display. The apparatus includes a sampling circuit for sampling the analog stroke display signals to produce pixel data representing sub-pixel locations covered by the stroke traces. A frame buffer is coupled to the sampling circuit to temporarily store pixel data. A filter is coupled to the frame buffer for calculating brightness of pixels based upon the amount of coverage of the pixels by a stroke trace. In addition, a raster-scan display device is coupled to the filter for receiving the pixel data from the filter to produce a raster-scan image.

Abstract: Systems and methods provide for interconnection of existing analog set-top box signal conversion hardware with new digital only set-top box conversion systems. In accordance with an exemplary embodiment of present invention, the digital and analog set-top boxes each respectively provide both video and stereo audio outputs which feed a relay or switch. In the preferred exemplary embodiment, the relay or switch is a smart switch which is configured to connect and output from the appropriate decoder or demodulator based on the user's channel selection. The output from the switch feeds a cable subscribers television. Additionally, a variety of different structures and methods are disclosed for connection of digital set-top boxes with analog demodulation hardware.

Abstract: A modular digital television architecture and method of designing the same is disclosed. The television architecture includes a processing chassis module operative to convert an analog input signal into at least a first digital signal for use in providing information to a display; a presentation chassis module operative to convert audio and visual components of the at least first digital signal into a final signal for presentation on the display, the audio and visual conversion being performed in a first domain; and an interface operative to interconnect the processing chassis module and the presentation chassis module. The processing and presentation chassis module are designed and operate independently of one another. The interface is a global interface capable of being used in conjunction with a plurality of chassis architectures. By employing a modular design, a variety of digital television systems can be readily produced.

Abstract: An analog-to-digital converter (ADC) (112) for sampling high speed video signals includes Pre-amplifiers (502, 504, 506) electrically coupled to Post-amplifiers (508, 510, 512) that are electrically coupled to output latches (514, 517, 519, 521, 523, 525, and 527). A sampling clock signal (116) clocks the output latches (514, 517, 519, 521, 523, 525, and 527) to sample an input analog electronic signal to provide a digital representation thereof. The ADC (112) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers (508, 510, 512) during a video signal horizontal blanking time period. The ADC (112) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers (502, 504, 506) increasing bit resolution. The ADC (112) includes wired interconnect interpolation between the Pre-amplifiers (502, 504, 506) and Post-amplifiers (508, 510, 512) and between the Post-amplifiers (508, 510, 512) and the output latches (514, 517, 519, 521, 523, 525, and 527).

Abstract: An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided.

Abstract: A solid state imager includes an arrangement for converting analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output providing a ramp signal with a level that varies corresponding to the contents of the counter. Latches or equivalent digital storage elements are each associated with a respective column. A counter bus connects the counter to latch inputs of said latches, and comparators associated the columns gate the latches when the analog ramp equals the pixel value for that column. The contents of the latch elements are transferred sequentially to a video output bus to produce the digital video signal. There can be additionally black-level readout latch elements, for storing a digital value that corresponds to the dark or black video level, and a subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer latches can be employed.

Abstract: An image encoding device and an image encoding method to be used therein can reduce generated code amount for permitting assignment of large coding amount to a portion where the most significant variation is caused, and whereby improvement of image quality is realized. The device performs image encoding by determining a motion vector amount of an image. The device makes judgment whether a motion vector amount calculated by using a preliminarily set difference threshold value can be replaced with a motion vector amount one preceding macro block.

Abstract: A system includes a signal reconstruction controller (110) electrically coupled to at least one analog-to-digital converter (ADC) (112) and to a phase adjustable clock source (108). A sampling clock signal (116) is electrically coupled from the clock source (108) to the at least one ADC (112). The at least one ADC (112) samples an electronic signal according to the sampling clock signal (116) to provide a digital representation of the electronic signal. The controller (110) samples data from the ADC (112) at different sampling points in the electronic signal and determines the edges (140) of the electronic signal and the noisy samples (142, 144) that are away from the edges (140) of the electronic signal. By finding the least noisy sample (146, 148) that is away from the edges (140) of the electronic signal the controller (110) adjusts the phase of a sampling signal clock (116) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.

Abstract: A video signal sampling apparatus for sampling an input analog video signal by use of a sampling clock, and producing a digital signal which represents a level of a resultant video signal sample as a digital video signal is disclosed. The video signal sampling apparatus includes N (N being an integer equal to or greater than 2) converters for sampling the input analog video signal by use of N sampling clocks having phases that are different from each other to produce N digital signals which represent levels of N resultant video signal samples respectively, and a selector for selecting one digital signal from the N digital signals produced by the N converters in order that an amplitude of the digital video signal output to the outside is maximized.

Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.

Abstract: A signal current corresponding to an incident light intensity is output from a photodiode PD, the signal current is converted into a signal voltage by an integration circuit 10, and the amount of a change in signal voltage in a predetermined time is output from a CDS circuit 20. The difference between two voltage values output from the CDS circuit 20 is obtained by a difference arithmetic circuit 30 and held by a S-H circuit 40. In addition, the maximum value of voltage values obtained by the difference arithmetic circuits 30 of respective units 100n is obtained by comparison circuits 50 of the respective units loon, a reference signal voltage generation circuit 500, a final coincidence determination circuit 200, and a reference voltage hold circuit 300, and on the basis of the maximum value, the A/D conversion range of an A/D conversion circuit 400 is set.

Abstract: The invention overcomes the need to adjust the video level settings of different video capture devices for each source by saving each setting as a difference between the actual setting and a default setting when digitizing source material. These saved differences are called differential settings. An actual setting for another capture device that provides consistent video levels when digitizing the same source may be derived from both the differential setting obtained when digitizing using the first capture device and the default setting of the other capture device. As a result, source material is mapped to consistent internal digital levels when used on the different devices. Accordingly, video characteristics such as gain, black, saturation and hue can be maintained correctly regardless of the unique settings due to manufacturing and calibration tolerances of the different video capture devices.

Abstract: A video signal processing apparatus having first and second analog/digital converters for converting imputted analog luminance and chrominance component signals into digital luminance and chrominance component signal. Frequency band limiting filters, disposed on a pre-stage of the first and second analog/digital converters, limit a frequency band of the analog luminance and chrominance component signals, the chrominance component signal frequency band limiting filter having a group delay characteristic different from a group delay characteristic of the luminance component signal frequency band limiting filter by a predetermined delay time. A time adjustment circuit adjusts the timing of the digital chrominance signal to match with the digital luminance signal.

Abstract: An automatic clock phase adjusting device is employed principally in a picture display to adjust automatically the phase of a clock signal given to an A/D converter which converts an analog image signal into a corresponding digital image signal. The automatic clock phase adjusting device comprises a delay circuit that delays the phase of the clock signal; an image level detecting circuit that detects the image level of a horizontal image starting portion of the digital image signal and the image level of an image terminating portion of the digital image signal; and a control circuit that controls a delay by which the delay circuit delays the clock signal on the basis of the output signal of the image level detecting circuit.

Abstract: An apparatus and method for synchronizing sampling of a video signal to a video synchronization signal of the video signal are provided. The frequency-divided output of an oscillator (or other controllable frequency source) is applied as one input to a phase detector, while the other input to the phase detector is supplied by the video synchronizing signals. The error signal voltage output of the phase detector is applied to correct the frequency, and thereby the phase, of the oscillator output through a dynamically-tuned phase-locked loop filter until the phases of the two input signals are in perfect agreement and no error voltage is produced. After a delay for this phase correction, during which time all video amplification is suspended, an output of the oscillator is then applied to sample the image without the presence of phase disparities while video amplification is restored. Full dynamic range digital acquisition then proceeds with extremely high accuracy at any desired resolution.