Abstract: An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A decoding processor (12) decodes a current block of a generated picture using lines of previously decoded image data from the memory (14) that are selected in dependence upon a motion vector (V1) for the current block. In order to improve access efficiency to the memory (14) the decoding processor (12) concatenates fetches into bursts for different sections of lines of previously decoded data that lie within a predetermined range within the memory addresses of the memory (14).

Abstract: Providing accelerated video processing in a communication device may comprise receiving video data from a video source on a chip, determining a first format for at least a portion of the received video data, and determining a second format of at least a remaining portion of the received video data. At least a portion of the received video data having the first format may be routed to a first device for processing and at least a remaining portion of the received video data having the second format may be routed to a second device for processing. The portion of the received video data with the first format may comprise RGB format, while the remaining portion of the received video data with the second format comprises YUV format. The received video data comprises images with alternating video formats, which are accordingly routed to the first or second device for processing.

Abstract: An apparatus for video decoding and de-interlacing contains a video decoder for decoding video data to generate decoded video data of a next picture; a storage device coupled to the video decoder, the storage device having four frame buffers for buffering the decoded video data of the next picture into one of the four frame buffers according to data stored in the frame buffers; an interlace/progressive converter coupled to the storage device, for de-interlacing data stored in the frame buffers to generate corresponding progressive video data; and a controller coupled to the video decoder and the interlace/progressive converter, for controlling data access of the video decoder and the interlace/progressive converter to the frame buffers of the storage device.

Abstract: In a video display apparatus and method, video data of video being displayed on a display unit are sequentially updated and temporality stored in a storage unit. The video data stored in the storage unit is written into an external storage medium according to a first external operation, and is read from the external storage medium according to a second external operation. Video based on the video data read from the external storage medium is displayed on the display unit.

Abstract: A method for transforming an original image to a new image is provided. The original image includes M rows of original data; the new image includes Q rows of new data. The method first generates a (2i?1)th row and a (2i)th row of intermediate data respectively based on the (2i?1)th row and the (2i)th row of original data. Then, the method generates a (2i+1)th row and a (2i+2)th row of intermediate data respectively based on the (2i+1)th row and the (2i+2)th row of original data. During the process of generating the (2i+1)th row of intermediate data, the (2j?1)th row of new data is simultaneously generated based on the (2i?1)th row and the (2i+1)th row of intermediate data. During the process of generating the (2i+2)th row of intermediate data, the (2j)th row of new data is simultaneously generated based on the (2i)th row and the (2i+2)th row of intermediate data.

Abstract: The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Abstract: An image device capable of reverse play with minimal time delay, and a method thereof. The image device includes a buffer to store a greater number of pictures than constitute a single group of pictures (GOP), and a controller to operate the buffer to store decoded pictures. Accordingly, problems such as cutoff of pictures or time delays are minimized when performing reverse play.

Abstract: In a liquid crystal display (LCD) panel based display, a method of dynamically selecting either frame rate conversion (FRC) or pixel voltage overdrive is disclosed. The method is carried out by performing the following operations. A video vertical refresh rate of an incoming video data stream is determined and based upon the determining, only one video data stream conditioning protocol from a number of available video data stream conditioning protocols is selected. The selected video data stream condition protocol is then applied to the video data stream.

Abstract: A video processing circuit for preventing generation of contour noise irrespective of varied directions of light emission schemes. A first video signal and a second video signal delayed by a predetermined field are received, a first motion detection result is output when a signal level of the first video signal is greater than that of the second video signal, and a second motion detection result is output if the second video signal is greater than the first video signal. A flag is established according to the first motion detection result, and a third video signal generated by delaying the first video signal is output. The lighted pattern of the third video signal is switched according to the second motion detection result and the flag.

Abstract: The present invention provides an image signal processing apparatus and a method thereof which shifts positions of each detected pixel in image signals generated by performing double-speed conversion, wherein a difference value in pixel signal level between a detected pixel in a current field and a detected pixel at the same position in a field which comes one frame behind the current field is calculated, to specify a first field, a motion vector for a field which comes one frame or two frames behind the current field is detected with respect to the detected pixel in the current field, interpolation pixel data for the detected pixel is calculated based on the detected pixel in the current field and the each pixel in the field which comes one frame or two frames behind the current field, the interpolation pixel data is disposed in the pixel position obtained by shifting the position of the detected pixel in the current field in a direction along the motion vector, in a field subsequent to the first field, and

Abstract: An apparatus and method for displaying an out-of-range mode which has a resolution higher than a mode supported by a monitor is provided. The method for displaying an out-of-range mode in monitor displaying includes the steps of (a) sensing received horizontal and vertical synchronizing signals and determining a display mode, and (b) adjusting a sampling rate so that a received video signal is displayed in a supported display mode in a case where the display mode is a mode excluding a supported display mode as a result of determination in step (a). The out-of-range mode which has a resolution higher than a mode supported by an LCD monitor so that a user's system can be easily and conveniently converted into a supported mode without additional apparatus or equipment, can be displayed in the LCD monitor.

Abstract: A receiver of analogue video signal having means for analogue video signal conversion has a receiving block (201) for receiving a first analogue video signal, a conversion block (202) for conversion of the first analogue signal into a digital signal, a buffer controller (203) of frame buffers, a video coder (204) for transforming the digital signal into an analogue signal of a second format, a receiver (205) for displaying the analogue signal of a second format and a processor (206) for data processing and controlling the receiving block, the conversion block, the buffer controller, the video coder and the receiver. The buffers controller (203) has three modules, namely, buffers (203b) linked together, a decoding frame controller (203a) and a displaying frame controller (203c). Certain frames in this device will be omitted when the output frames frequency is lower than the input frequency and displayed more than once when the output frames frequency is higher than the input frequency.

Abstract: A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Abstract: A system and method for displaying frames with dynamically changing display parameters is described herein. The display engine stores new display parameters detected by the decoder in one buffer of a ping pong buffer, while continuing to use another set of display parameters stored in the other ping pong buffer. The display engine switches the buffers when the first frame for which the new display parameters are applicable is to be presented.

Abstract: Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A feeder fetches a first line from a top field, fetches a first line from a bottom field corresponding to the top field, after fetching the first line from the top field, and fetches a second line from the top field after fetching the first line from the bottom field. The second line from the top field is adjacent to the first line in the top field.

Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method for compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.

Abstract: A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a graphics buffer area (45Ai) for storing graphics data, said method including passing graphics data stored in the graphics buffer area to the data buffer area for combination with display data stored therein.

Abstract: A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles.

Abstract: Providing accelerated video processing in a communication device may comprise receiving video data from a video source on a chip, determining a first format for at least a portion of the received video data, and determining a second format of at least a remaining portion of the received video data. At least a portion of the received video data having the first format may be routed to a first device for processing and at least a remaining portion of the received video data having the second format may be routed to a second device for processing. The portion of the received video data with the first format may comprise RGB format, while the remaining portion of the received video data with the second format comprises YUV format. The received video data comprises images with alternating video formats, which are accordingly routed to the first or second device for processing.

Abstract: First selected image frames in a native format are read from a frame storage device (103) and are directly modified in response to a first process. Output signals are supplied to a display device (102) such that the display device displays a view of stored frames. The frames are stored in the native format but appear in the view as if stored in an alternative format. Frames are selected and in response to receiving input selection signals, selected frames are translated into an alternative format and supplied to a second process in the translated formats.

Abstract: A personal optical viewer enables a person to view images of how the person looks wearing an accessory and compare images of how the customer looks wearing different accessories. A seller provides an accessory to a person. A capturing device captures a photograph or a video of the person and stores the image in a memory device. The personal optical viewer displays each image to the person and the person chooses which images to keep, reject, delete, or compare. The personal optical viewer replaces rejected images with other images stored in the memory device, and when the stored images have been exhausted the personal optical viewer automatically enlarges the remaining displayed images.

Abstract: A signal processing unit for a digital TV system comprises a first device which acts on a video signal with graphical picture elements and text characters. A second device performs frame-rate conversion on the output of the first device. The output of the second device drives a display driver.

Abstract: The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected

Abstract: An image binarization method having highest fidelity for multi-digitized luminance data, and a binary image creation method by which images can be obtained in real-time without post-processing. Thresholds in binarization are not fixed, but set in accordance with changes in luminance, thus allowing real time images to be obtained.

Abstract: A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged memory. A page of the paged memory containing Y data is accessed; Y data corresponding to M pixels of video data is then retrieved, where M is a value greater than or equal to two. The retrieved Y data is then stored in a shift register. Similar steps are taken to access, retrieve and store Cb and Cr data. Within the shift register, the Y, Cb, and Cr data is stored as sets of planar video data. The Y, Cb, and Cr data is retrieved from the shift register as a series of pixel data for generating pixels on a video display unit.

Abstract: In a liquid crystal display (LCD) device, two continuous frame image data to be displayed on a display unit are compared with each other by a comparator circuit, and horizontal and vertical synchronizing signals are regulated in accordance with a comparison result. That is, when the two frame image data coincide with each other, the horizontal and vertical synchronizing signals are not output to the display unit through the controller, in order to decrease the number of scannings of frames to be displayed. Also, when the LCD device has a backlight unit and two frame image data coincide with each other, the backlight unit is turned off.

Abstract: An apparatus and a method of controlling image display in an image display apparatus having a panel and wherein an image output is synchronized to a frame synchronization signal of an input signal. The method includes determining whether or not an input synchronization signal is an abnormal synchronization signal, processing the abnormal synchronization signal if the input synchronization is the abnormal synchronization signal, and removing damaged frame data if the abnormal synchronization signal is processed.

Abstract: In the present invention, the same image data, captured by a TV camera, is processed by the use of an image-processing board connected to an extension bus constituted by a personal computer and a CPU board inside the personal computer so that the CPU board and the image-processing board are allowed to execute the image processes in parallel with each other.

Abstract: A picture processing apparatus is composed of a plurality of picture processing systems. Each picture processing system includes an identical picture processing IC (integrated circuit) and a plurality of memories each capable of memorizing a picture frame and including at least two memories operating at different timings. The picture processing IC includes a picture processing unit, an operation timing signal generator, a plurality of control timing signal generators for controlling different memories, and a memory control signal selection circuit for selectively outputting one of at least two memory control timing signals. As a result, the number of output pins of each picture processing IC for outputting memory control signal can be reduced, whereby the picture processing apparatus can be produced at a lower cost while retaining an identically large size of the picture processing ICs.

Abstract: A digital still camera with video playback capabilities including a hybrid buffer for variable length frame decoding, the hybrid having two buffers with each buffer having full/not-full indicators and filling plus a single circular read out position indicator.

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: The invention relates to a method and apparatus for vertically scaling a video picture comprising receiving and storing lines of a video frame of a video picture, reading lines of the frame into linestores, applying the lines to a vertical filter and providing an output video line as a function of the lines. Reading the lines of the frame into linestores comprises reading M lines of each successive 2nd line of the frame lines into the linestores. Following generation of the output video line, a further X lines are read from the framestore into the linestores to provide a further set of M lines in the linestores. The M lines are applied to the vertical filter to provide a further output video line as a function of the lines.

Abstract: A cache memory system for use in a motion estimation system is disclosed. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.

Abstract: A method and apparatus are provided for catching-up on viewing a program on a viewing device. The apparatus according to an embodiment of the invention includes a storing mechanism configured for simultaneously recording and playing back digital video and audio streams. A controller is configured to control the storing mechanism to record and play back the digital video and audio streams. The controller is also configured to determine an accelerated playback speed that allows a viewer to catch-up to a real time viewing of the program. A playback mechanism operatively coupled between the storing mechanism and the viewing device is configured to control a playback speed of the video and audio streams provided to the viewing device from the storage mechanism in accordance with the accelerated playback speed.

Abstract: Imaging apparatus having a video memory function includes a video memory having a plurality of read ports and a capacity of storing images in two fields or more, wherein CCD storage sensitivity enhancement means is connected to a write port; a write control circuit for storing a single-field image in each memory area provided by dividing the storage space of the video memory into a plurality of sub-spaces; a plurality of read control sections for reading a single-field image stored in each memory area; and memory control means for reading an image from the video memory by a delay amount corresponding to the timing of a synchronization signal from the CCD storage sensitivity enhancement means. This configuration allows adjustment of the delay amount and prevents an image write address from passing by an image read address so that image data given CCD storage sensitivity enhancement is processed normally.

Abstract: A digital signal processing apparatus for parallel executing a plurality of data processes with a single common command is disclosed, that comprises a plurality of input storing means, each of which is composed of a plurality of storing elements, an input controlling means for controlling the input storing means, a calculating means, having a plurality of element calculating means corresponding to the plurality of the storing elements of the input storing means, for parallel calculating data stored in each storing element of the input storing means, a data storing means, having a plurality of storing elements corresponding to the plurality of element calculating means of the calculating means, for storing calculated result data of the element calculating means corresponding to the storing elements, a plurality of output storing means, each of which is composed of a plurality of storing elements corresponding to the plurality of element calculating means of the calculating means, for storing the calculated res

Abstract: A method of rapidly generating motion vector predictions based on vertical and horizontal position categorization of macroblocks within a video object plane (VOP) for use within a video decoder or encoder. By way of example, the location of the subject macroblock is categorized vertically as either Upper_Edge or Not_Upper_Edge, and horizontally as either Left_Edge, Right_Edge, or Not_Edge. The position categories are utilized in conjunction with selected block number (Block1 through Block4) within the luminance macroblock within a decision-tree which generates three predictors MV1, MV2, and MV3. The prediction rules may be implemented within hardware, software, or combinations thereof, within both video encoders and decoders, such as according to the MPEG-4, H.263, or similar standards.

Abstract: A method and apparatus for video signal frame rate matching using three buffers. The method and apparatus reads frame data out of the third buffer. At substantially the same time, the method and apparatus fills the first buffer with the next sequence of frame data and then fills the second buffer with the next sequence of frame data, continuing to alternate the fills between the first buffer and the second buffer until all of the frame data has been read from the third buffer. Next, the method and apparatus determines which of the first buffer or second buffer has been filled with the most current and most complete frame data. Last, the method and apparatus reads the frame data out of the determined buffer.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A memory management process for buffering progressive, interlaced, CCIR 601/656 compliant, and MPEG compliant video signals in a video memory that is partitioned into first and second buffers. The process includes identifying the format of a received video signal, buffering the received video signal in the video memory in accordance with a standard buffering mode if the video signal is in an interlaced, CCIR 601/656 compliant, or MPEG compliant format, and buffering the received video signal in the video memory in accordance with an override buffering mode if the video signal is in a progressive format such as a 240p signal generated by a game console, VCR, cable text generator, and the like.

Abstract: Plural encoders operating in parallel to achieve a desired data rate have their respective outputs combined by an autonomously operating arrangement for transfer of data to a direct memory access arrangement from respective encoders in order in response to a signal asserted upon completion of encoding and output of encoded data corresponding to a predetermined portion of input data. buffering of encoder output can be either internal or external to the encoders. Zero bytes which may be inherently generated at the beginning and end of an encoder output stream may be suppressed to improve encoded signal quality and efficiency.

Abstract: The present invention provides a technique that facilitates A-D conversion and D-A conversion of high-frequency image signals. Three A-D converters 71 through 73 successively carry out A-D conversion of an analog image signal AV1, in response to three sampling clock signals SAD1 through SAD3, which respectively have a frequency that is ⅓ of a frequency of a dot clock signal DCLK1 and phases that are sequentially shifted by a period of the dot clock signal DCLK1, thereby generating three digital image signals D1 through D3 with respect to three consecutive pixels. The digital image signals for the three pixels are written into consecutive storage areas in a frame memory 26. Reading operation of an image signal from the frame memory 26 is also carried out at a frequency that is ⅓ of a frequency of a read dot clock signal. The working number of A-D converters and the working number of D-A converters are regulated according to the frequency of the analog image signal.

Abstract: In order to reduce memory requirements in a chip for demodulating digital video broadcast signals, symbol data values stored for a channel equalisation process have their scattered pilots removed, to achieve a 9% reduction in memory space required. This is achieved by providing a write pointer and a read pointer, the write pointer being arranged to exclude carriers carrying scattered pilots, and the read pointer being arranged to read the stored symbol data, but to add nominal data values at positions of excluded scattered pilots.

Abstract: A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.

Abstract: In a method of controlling a memory (5) to allow for a display of at least two images, write and read speeds of writing image data into and reading image data from the memory (5) are measured (9-15) to predict a crossing where a write action overtakes a read action or reversely, where a new field of said image data is written (13, 3) into the memory (5) from a same initial position as from which a previous field of the image data was written into the memory (5) if no crossing is predicted, and the new field of said image data is written (13, 3) into the memory (5) from an end position in the memory (5) at which an end of the previous field of the image data was written into the memory (5) if a crossing is indeed predicted, the memory (5) having a size being larger than that needed for one field but less than that needed for two fields of the image data at its largest read-out size.

Abstract: A method and apparatus for video motion compensation, power of two reduction and color format conversion is disclosed. The motion compensation engine performs the MPEG-2 functions of half pel compensation, inverse discrete cosine transform and merge. Dual prime, field-based and frame-based macroblocks are supported. Data reduction may be performed in the vertical direction, the horizontal direction, or both.

Abstract: A method and apparatus for retiming video. Vertical synchronization information (VSI) is detected in an incoming video stream. A VSI is also detected in both as output video stream and a reference video stream. Based on the difference between the VSI of the reference and output video stream reads or writes to a FIFO are suppressed until the VSI's are coincident.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: An image processing device of the present invention includes a plurality of processing sections for successively receiving and decoding a plurality of data blocks, which have been obtained by encoding a plurality of image blocks of an image. The plurality of processing sections include an inverse discrete cosine transform processing section for performing two-dimensional inverse discrete cosine transform. When one of the processing sections is unable to receive the data block, the one of the processing sections sends a busy signal to preceding one of the processing sections. When one of processing sections receives the busy signal, the one of the processing sections discontinues data block transfer to following one of the processing sections.

Abstract: An image frame synchronizing apparatus and a method thereof which receive image signals from a plurality of image signal sources, detect a synchronous signal from the image signal of one image signal source among the plurality of image signal sources, and synchronize the image frames of image signals from the image signal sources according to the frame synchronous signal, in order to display the images in one frame unit.